2020-02-17 18:06:38 +01:00
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#include <gint/dma.h>
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#include <gint/mpu/dma.h>
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#include <gint/display.h>
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#include <gint/keyboard.h>
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2021-04-24 16:11:47 +02:00
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#include <gint/mmu.h>
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2020-02-17 18:06:38 +01:00
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#include <gintctl/util.h>
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#include <gintctl/gint.h>
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2021-06-08 10:45:51 +02:00
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#include <stdio.h>
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2020-02-17 18:06:38 +01:00
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#define DMA SH7305_DMA
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2020-06-18 19:56:32 +02:00
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#define dprint(x, y, ...) dprint(x, y, C_BLACK, __VA_ARGS__)
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2020-02-17 18:06:38 +01:00
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2021-04-24 16:11:47 +02:00
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void show_dma(int x, int y, GUNUSED int channel, sh7305_dma_channel_t *dma)
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2020-02-17 18:06:38 +01:00
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{
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#ifdef FX9860G
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int dx=60, dy=8;
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2021-04-24 16:11:47 +02:00
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dprint(x, y, "SAR:");
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dprint(x, y+1*dy, "DAR:");
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dprint(x, y+2*dy, "TCR:");
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dprint(x, y+3*dy, "CHCR:");
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dprint(x+dx, y, "%08X", dma->SAR);
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2020-02-17 18:06:38 +01:00
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dprint(x+dx, y+1*dy, "%08X", dma->DAR);
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2021-04-24 16:11:47 +02:00
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dprint(x+dx, y+2*dy, "%08X", dma->TCR);
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dprint(x+dx, y+3*dy, "%08X", dma->CHCR);
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2020-02-17 18:06:38 +01:00
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#endif
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#ifdef FXCG50
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int dx=45, dy=14;
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dprint(x, y, "DMA%d:", channel);
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dprint(x, y+1*dy, "SAR");
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dprint(x+dx, y+1*dy, "%08X", dma->SAR);
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dprint(x, y+2*dy, "DAR");
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dprint(x+dx, y+2*dy, "%08X", dma->DAR);
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dprint(x, y+3*dy, "TCR");
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dprint(x+dx, y+3*dy, "%08X", dma->TCR);
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dprint(x, y+4*dy, "CHCR");
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dprint(x+dx, y+4*dy, "%08X", dma->CHCR);
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#endif
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}
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/* gintctl_gint_dma(): Test the Direct Access Memory Controller */
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void gintctl_gint_dma(void)
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{
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2021-04-24 16:11:47 +02:00
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/* We'll display the DMA status at "full speed", without sleeping. */
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int key=0, timeout=1;
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/* Test channel, interrupts, and source; successful attempts */
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int channel=0, interrupts=0, source=0, successes=0;
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2020-02-17 18:06:38 +01:00
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2021-04-24 16:11:47 +02:00
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/* Get the physical VRAM address */
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void *vram_address = gint_vram;
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2020-02-17 18:06:38 +01:00
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#ifdef FX9860G
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2021-04-24 16:11:47 +02:00
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uint32_t virt_page = (uint32_t)vram_address & 0xfffff000;
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uint32_t phys_page = 0x80000000 + mmu_translate(virt_page, NULL);
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vram_address = (void *)phys_page + (vram_address - (void *)virt_page);
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2020-02-17 18:06:38 +01:00
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#endif
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2021-04-24 16:11:47 +02:00
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sh7305_dma_channel_t *addr[6] = {
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&DMA.DMA0, &DMA.DMA1, &DMA.DMA2, &DMA.DMA3, &DMA.DMA4, &DMA.DMA5,
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};
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2020-02-17 18:06:38 +01:00
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while(key != KEY_EXIT)
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{
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dclear(C_WHITE);
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#ifdef FX9860G
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2021-04-24 16:11:47 +02:00
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show_dma(1, 0, channel, addr[channel]);
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dprint(1, 32, "Channel DMA%d", channel);
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2020-02-17 18:06:38 +01:00
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dprint(1, 40, "Interrupts %s", interrupts ? "Yes" : "No");
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dprint(1, 48, "Source %s", source ? "IL" : "RAM");
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dprint(103, 40, "%d", successes);
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2020-06-01 12:12:21 +02:00
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extern bopti_image_t img_opt_gint_dma;
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2020-02-17 18:06:38 +01:00
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dimage(0, 56, &img_opt_gint_dma);
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#endif
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#ifdef FXCG50
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row_title("Direct Memory Access status");
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2020-05-31 15:56:22 +02:00
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show_dma(6, 24, 0, addr[0]);
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show_dma(138, 24, 1, addr[1]);
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show_dma(270, 24, 2, addr[2]);
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2020-02-17 18:06:38 +01:00
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dprint(6, 102, "DMAOR: %08X", DMA.OR);
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dprint(6, 130, "Channel");
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dprint(96, 130, "%d", channel);
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dprint(6, 144, "Interrupt");
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dprint(96, 144, "%s", interrupts ? "Yes" : "No");
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dprint(6, 158, "Source");
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dprint(96, 158, "%s", source ? "IL" : "RAM");
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2020-05-16 15:56:06 +02:00
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fkey_action(1, "RUN");
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2020-02-17 18:06:38 +01:00
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2020-05-16 15:56:06 +02:00
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fkey_button(4, "CHANNEL");
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fkey_button(5, "INT");
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fkey_button(6, "SOURCE");
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2020-02-17 18:06:38 +01:00
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#endif
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dupdate();
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key = getkey_opt(GETKEY_DEFAULT, &timeout).key;
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2021-04-24 16:11:47 +02:00
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/* On F1, start a 1024-byte DMA transfer and see what happens */
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2020-02-17 18:06:38 +01:00
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if(key == KEY_F1)
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{
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void *src = (void *)(source ? 0xe5200000 : 0x88000000);
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2021-04-24 16:11:47 +02:00
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void *dst = vram_address;
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2020-02-17 18:06:38 +01:00
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int blocks = 256;
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2021-04-28 17:54:49 +02:00
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if(interrupts) dma_transfer_sync(channel, DMA_4B,
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blocks, src, DMA_INC, dst, DMA_INC);
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else dma_transfer_atomic(channel, DMA_4B, blocks, src,
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DMA_INC, dst, DMA_INC);
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2020-02-17 18:06:38 +01:00
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successes++;
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}
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if(key == KEY_F4) channel = (channel + 1) % 6;
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if(key == KEY_F5) interrupts = !interrupts;
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if(key == KEY_F6) source = !source;
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}
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}
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