perf/cpucache: evidence the 32-kiB operand cache
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# We put all the code in ILRAM to avoid measurement variations caused by code
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# being fetched from ROM. The ILRAM is ideal for this task because successive
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# instruction accesses take only 1 cycle (assuming no interference, which there
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# is none).
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.section .ilram
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# Test prologue for COUNT iterations (must be a multiple of 256). Note that the
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# prologue has an even number of instructions, which results in the loop code
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# being 4-aligned, which is of extreme importance.
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#define PROLOGUE(COUNT) \
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mov #(COUNT/256), r0 ; \
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shll8 r0 ; \
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ldrs 1f ; \
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ldre 2f ; \
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ldrc r0 ; \
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nop
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# Test epilogue
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#define EPILOGUE() \
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rts ; \
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nop
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/* [Baseline]
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In this first section, we want to establish an approximate cost of the
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setup, which consists of TMU access for libprof, function calls, and the
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loop setup for the DSP. */
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.global _perf_cpu_empty
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# Empty setup (0 iterations), as baseline
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.align 4
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_perf_cpu_empty:
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PROLOGUE(0)
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1: 2: EPILOGUE()
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/* [Loop control]
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In this section, we want to check whether the DSP repeat system has any
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added cost per-loop, and we do this by executing the same instructions with
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a varying number of DSP repeat jumps.
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The DSP jump has no additional cost, which makes testing much simpler by
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avoiding loop unrolls (that would otherwise be needed to amortize the cost
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of the jump). In addition, this allows for tighter loops in real-world
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programs, and tigher code first better in cache. */
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.global _perf_cpu_nop_2048x1
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.global _perf_cpu_nop_1024x2
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.global _perf_cpu_nop_512x4
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.global _perf_cpu_nop_256x8
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# nop loop (2048 iterations of 1 nop) -> 2 cycles /i
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# Parallel execution likely cannot read through the DSP jump for architectural
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# reasons; my guess is that the next instruction isn't fetched yet.
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.align 4
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_perf_cpu_nop_2048x1:
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PROLOGUE(2048)
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1: 2: nop
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EPILOGUE()
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# nop loop (1024 iterations of 2 nop) -> 1 cycle /i
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.align 4
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_perf_cpu_nop_1024x2:
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PROLOGUE(1024)
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1: nop
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2: nop
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EPILOGUE()
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# nop loop (512 iterations of 4 nop) -> 2 cycles /i
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.align 4
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_perf_cpu_nop_512x4:
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PROLOGUE(512)
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1: nop
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nop
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nop
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2: nop
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EPILOGUE()
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# nop loop (256 iterations of 8 nop) -> 4 cycles/i
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.align 4
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_perf_cpu_nop_256x8:
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PROLOGUE(256)
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1: nop
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nop
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nop
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nop
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nop
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nop
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nop
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2: nop
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EPILOGUE()
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/* [Parallel execution]
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In this section, we reproduce simple cases of superscalar parallelism for
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instructions of different types, using only instructions that have trivial
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pipelines with no extra cycles. */
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.global _perf_cpu_EX_EX
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.global _perf_cpu_MT_MT
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.global _perf_cpu_LS_LS
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# EX/EX (1024 iterations of 2 non-parallel instructions) -> 2 cycles /i
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.align 4
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_perf_cpu_EX_EX:
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PROLOGUE(1024)
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1: add #0, r0
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2: add #0, r1
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EPILOGUE()
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# MT/MT (1024 iterations of 2 parallel instructions) -> 1 cycle /i
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.align 4
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_perf_cpu_MT_MT:
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PROLOGUE(1024)
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1: mov r0, r1
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2: mov r2, r3
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EPILOGUE()
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# LS/LS (1024 iterations of 2 non-parallel instructions) -> 2 cycles /i
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.align 4
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_perf_cpu_LS_LS:
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PROLOGUE(1024)
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1: mov.l @r15, r0
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2: mov.l @r15, r1
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EPILOGUE()
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@ -0,0 +1,122 @@
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#include <gint/display.h>
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#include <gint/keyboard.h>
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#include <gint/clock.h>
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#include <gintctl/perf.h>
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#include <gintctl/util.h>
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#include <libprof.h>
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/* Baseline */
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void perf_cpu_empty(void);
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/* Loop control */
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void perf_cpu_nop_2048x1(void);
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void perf_cpu_nop_1024x2(void);
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void perf_cpu_nop_512x4(void);
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void perf_cpu_nop_256x8(void);
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/* Parallel execution */
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void perf_cpu_EX_EX(void);
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void perf_cpu_MT_MT(void);
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void perf_cpu_LS_LS(void);
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/* Is subtracted from result times if specified; in TMU units (prof.elapsed) */
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static uint32_t baseline_ticks = 0;
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/* Number of CPU cycles spent executing a function */
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uint32_t Iphi_cycles(void (*function)(void))
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{
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prof_t perf = prof_make();
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prof_enter(perf);
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(*function)();
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prof_leave(perf);
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clock_frequency_t const *freq = clock_freq();
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uint32_t TMU_cycles = perf.elapsed - baseline_ticks;
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uint32_t PLL_cycles = (TMU_cycles * 4) * freq->Pphi_div;
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return PLL_cycles / freq->Iphi_div;
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}
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/* Number of CPU cycles per iteration; the number of iterations must obviously
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match assembler code for that test */
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float Iphi_per_iteration(void (*function)(void), int count)
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{
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return (float)Iphi_cycles(function) / count;
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}
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/* Number of TMU cycles for an empty function */
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uint32_t TMU_baseline(void)
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{
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prof_t perf = prof_make();
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for(int i = 0; i < 16; i++)
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{
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prof_enter(perf);
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perf_cpu_empty();
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prof_leave(perf);
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}
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return perf.elapsed / 16;
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}
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//---
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void gintctl_perf_cpu(void)
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{
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int key = 0;
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/* Measure baseline time */
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baseline_ticks = TMU_baseline();
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uint32_t Iphi_cpu_nop_2048x1 = 0;
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uint32_t Iphi_cpu_nop_1024x2 = 0;
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uint32_t Iphi_cpu_nop_512x4 = 0;
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uint32_t Iphi_cpu_nop_256x8 = 0;
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uint32_t Iphi_cpu_EX_EX = 0;
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uint32_t Iphi_cpu_MT_MT = 0;
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uint32_t Iphi_cpu_LS_LS = 0;
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while(key != KEY_EXIT)
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{
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dclear(C_WHITE);
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#ifdef FXCG50
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row_title("CPU instruction parallelism and pipelining");
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row_print(1, 1, "Baseline ticks: %d",
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baseline_ticks);
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row_print(3, 1, "Iphi cycles for 2048x1 nop: %d",
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Iphi_cpu_nop_2048x1);
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row_print(4, 1, "Iphi cycles for 1024x2 nop: %d",
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Iphi_cpu_nop_1024x2);
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row_print(5, 1, "Iphi cycles for 512x4 nop: %d",
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Iphi_cpu_nop_512x4);
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row_print(6, 1, "Iphi cycles for 256x8 nop: %d",
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Iphi_cpu_nop_256x8);
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row_print(8, 1, "Iphi cycles for EX/EX: %d",
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Iphi_cpu_EX_EX);
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row_print(9, 1, "Iphi cycles for MT/MT: %d",
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Iphi_cpu_MT_MT);
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row_print(10, 1, "Iphi cycles for LS/LS: %d",
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Iphi_cpu_LS_LS);
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fkey_button(1, "RUN");
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#endif
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dupdate();
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key = getkey().key;
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if(key == KEY_F1)
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{
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Iphi_cpu_nop_2048x1 = Iphi_cycles(perf_cpu_nop_2048x1);
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Iphi_cpu_nop_1024x2 = Iphi_cycles(perf_cpu_nop_1024x2);
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Iphi_cpu_nop_512x4 = Iphi_cycles(perf_cpu_nop_512x4);
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Iphi_cpu_nop_256x8 = Iphi_cycles(perf_cpu_nop_256x8);
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Iphi_cpu_EX_EX = Iphi_cycles(perf_cpu_EX_EX);
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Iphi_cpu_MT_MT = Iphi_cycles(perf_cpu_MT_MT);
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Iphi_cpu_LS_LS = Iphi_cycles(perf_cpu_LS_LS);
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}
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}
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}
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@ -17,20 +17,27 @@ _cpucache_nop1024:
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# r4: Buffer to read from
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# r5: Buffer size (multiple of 4)
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# r5: Buffer size (multiple of 32)
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# r6: Number of rounds
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_cpucache_rounds:
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mov r4, r1
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add r5, r1
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add #-1, r1
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mov r4, r0
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mov r5, r2
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mov #-5, r3
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shld r3, r2
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1: mov.b @r0+, r2
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mov.b @r0+, r2
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mov.b @r0+, r2
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cmp/ge r1, r0
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bf 1b
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mov.b @r0+, r2
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ldrs 1f
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ldre 2f
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ldrc r2
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nop
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1: mov.l @r0+, r1
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mov.l @r0+, r1
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mov.l @r0+, r1
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mov.l @r0+, r1
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mov.l @r0+, r1
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mov.l @r0+, r1
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mov.l @r0+, r1
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2: mov.l @r0+, r1
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dt r6
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bf _cpucache_rounds
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@ -9,8 +9,9 @@
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#include <libprof.h>
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#include <stdio.h>
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#include <stdlib.h>
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#define CACHE_MAX 4096
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#define CACHE_MAX 65536
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#define SAMPLES 129
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extern void cpucache_nop1024(int repeats);
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@ -60,7 +61,9 @@ void gintctl_perf_cpucache(void)
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uint32_t nop4096 = test_nop4096();
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nop4096 = test_nop4096();
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uint8_t buf[CACHE_MAX];
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uint8_t *buf = malloc(CACHE_MAX);
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if(!buf) return;
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int32_t x_size[SAMPLES];
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int32_t y_time[SAMPLES];
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@ -103,7 +106,7 @@ void gintctl_perf_cpucache(void)
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.subtick_divisions = 4,
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},
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.ticks_y = {
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.multiples = 10000,
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.multiples = 125000,
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.subtick_divisions = 2,
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},
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.grid = {
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@ -122,7 +125,7 @@ void gintctl_perf_cpucache(void)
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for(int i = 0; i < SAMPLES; i++)
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{
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x_size[i] = (CACHE_MAX / (SAMPLES-1)) * i;
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y_time[i] = test_cpucache_rounds(buf, x_size[i], 16);
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y_time[i] = test_cpucache_rounds(buf, x_size[i], 8);
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if(y_time[i] < y_min || y_min == -1) y_min = y_time[i];
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if(y_time[i] > y_max || y_max == -1) y_max = y_time[i];
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@ -149,9 +152,9 @@ void gintctl_perf_cpucache(void)
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plot(&plotspec);
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row_print(12, 1, "X: Size of buffer (bytes)");
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row_print(13, 1, "Y: Iphi cycles for 16 8-bit traversals");
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row_print(13, 1, "Y: Iphi cycles for 8x 32-bit traversals");
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row_print(14, 1, "Last samples suggests: %.2D Iphi/byte access",
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100 * y_time[SAMPLES-1] / x_size[SAMPLES-1] / 16);
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100 * y_time[SAMPLES-1] / x_size[SAMPLES-1] / 8);
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#endif
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dupdate();
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