perf/cpu: more documentation on pipeline stalls
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@ -233,6 +233,7 @@ _perf_cpu_pipeline_3:
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.global _perf_cpu_raw_EX_EX
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/* Forwarding after the ALU is seamless, no delay -> 2 cycles /i */
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.align 4
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_perf_cpu_raw_EX_EX:
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PROLOGUE(1024)
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@ -242,6 +243,8 @@ _perf_cpu_raw_EX_EX:
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.global _perf_cpu_raw_LS_LS
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/* Value is available immediately for memory... at a *different address* (the
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same addresse would give 4 cycles /i) -> 2 cycles /i */
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.align 4
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_perf_cpu_raw_LS_LS:
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PROLOGUE(1024)
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@ -249,11 +252,12 @@ _perf_cpu_raw_LS_LS:
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nop
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1: mov.l @r4, r0
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2: mov.l r0, @r4
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2: mov.l r0, @(4,r4)
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EPILOGUE()
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.global _perf_cpu_raw_EX_LS
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/* Perfect forwarding from ALU to memory access -> 1 cycle /i */
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.align 4
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_perf_cpu_raw_EX_LS:
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PROLOGUE(1024)
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@ -266,30 +270,40 @@ _perf_cpu_raw_EX_LS:
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.global _perf_cpu_raw_LS_EX
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/* 1-cycle stall after loading a register from memory -> 3 cycles /i */
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.align 4
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_perf_cpu_raw_LS_EX:
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PROLOGUE(1024)
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mov.l .buffer, r4
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nop
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1: mov.l @r4, r0
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1: mov.l @r15, r0
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2: add #1, r0
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EPILOGUE()
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.global _perf_cpu_raw_LS_MT
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/* Same - it's not like you could move to avoid the stall -> 3 cycles /i */
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.align 4
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_perf_cpu_raw_LS_MT:
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PROLOGUE(1024)
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1: mov.l @r15, r0
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2: mov r0, r1
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EPILOGUE()
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.global _perf_cpu_noraw_LS_LS
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/* Still efficient as long as the addresses are different -> 2 cycles /i */
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.align 4
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_perf_cpu_noraw_LS_LS:
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PROLOGUE(1024)
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mov.l .buffer, r4
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nop
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mov r4, r5
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1: mov.l @r4, r0
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2: mov.l r1, @r4
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2: mov.l r1, @(4,r5)
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EPILOGUE()
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.global _perf_cpu_noraw_LS_EX
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/* Normal superscalar parallelism at work -> 1 cycle /i */
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.align 4
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_perf_cpu_noraw_LS_EX:
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PROLOGUE(1024)
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@ -302,6 +316,8 @@ _perf_cpu_noraw_LS_EX:
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.global _perf_cpu_raw_EX_LS_addr
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/* There is no forwarding on the address, so similar to loading this actually
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takes much longer than when modifying the operand -> 3 cycles /i */
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.align 4
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_perf_cpu_raw_EX_LS_addr:
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PROLOGUE(1024)
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@ -312,13 +328,29 @@ _perf_cpu_raw_EX_LS_addr:
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2: mov.l r0, @r4
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EPILOGUE()
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.global _perf_cpu_raw_LS_LS_addr
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/* The worst of all; 2-cycle stall to use a loaded address -> 4 cycles /i */
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.align 4
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_perf_cpu_raw_LS_LS_addr:
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PROLOGUE(1024)
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mov.l .buffer, r4
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mov.l r15, @r4
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1: mov.l @r4, r5
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2: mov.l @r5, r6
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EPILOGUE()
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.global _perf_cpu_raw_DSPLS_DSPLS
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/* As previously, the addresses must be different -> 2 cycles /i */
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.align 4
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_perf_cpu_raw_DSPLS_DSPLS:
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PROLOGUE(512)
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mov.l .buffer, r4
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mov r4, r5
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add #2, r5
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nop
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1: movs.w @r4, x0
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2: movs.w x0, @r5
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@ -327,10 +359,14 @@ _perf_cpu_raw_DSPLS_DSPLS:
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/* [Iteration weaving]
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In this section we analyze how iterations can be woven and opened to improve
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performance by reducing RAW dependencies. */
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performance by reducing RAW dependencies. This is illustrated with a
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function that darkens a continuous section of VRAM. The initial version
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takes 3 cycles /pixel, whereas the optimized takes 1.25 cycle /pixel. */
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.global _perf_cpu_darken_1
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/* Darkening RGB565 by (color = (color & 0xf7de) >> 1). This base version does
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two pixels at a time but has pretty complex RAWs -> 6 cycles /i */
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.align 4
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_perf_cpu_darken_1:
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PROLOGUE(512)
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@ -340,14 +376,17 @@ _perf_cpu_darken_1:
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nop
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1: mov.l @r4+, r1
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/* Stall because of loading r1 */
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and r2, r1
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add #4, r5
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shlr r1
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/* Stall because of access to r5 as address */
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2: mov.l r1, @r5
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EPILOGUE()
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.global _perf_cpu_darken_2
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/* Here the change to r5 is moved to eliminate both stalls -> 4 cycles /i */
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.align 4
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_perf_cpu_darken_2:
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PROLOGUE(512)
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@ -359,12 +398,17 @@ _perf_cpu_darken_2:
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1: mov.l @r4+, r1
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add #4, r5
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and r2, r1
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/* The EX/LS pair below is the only one parallelized */
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shlr r1
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2: mov.l r1, @r5
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EPILOGUE()
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.global _perf_cpu_darken_3
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/* Here iterations are woven together to increase the amount of independent
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data. Each iteration processes twice as much data and uses EX cycles of the
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first longword to do LS work on the second one. Plus r5 is incremented only
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once -> 6 cycles /i */
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.align 4
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_perf_cpu_darken_3:
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PROLOGUE(256)
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@ -375,17 +419,25 @@ _perf_cpu_darken_3:
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1: mov.l @r4+, r1
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add #8, r5
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mov.l @r4+, r3
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and r2, r1
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shlr r1
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mov.l r1, @r5
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and r2, r3
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shlr r3
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2: mov.l r3, @(4,r5)
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EPILOGUE()
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.global _perf_cpu_darken_4
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/* Finally iterations are opened here to eliminate the long chain of dependency
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from the loads to the stores. Late EX instructions are parallelized with
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loads for the next iteration -> 5 cycles/i */
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.align 4
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_perf_cpu_darken_4:
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PROLOGUE(256)
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@ -413,6 +465,7 @@ _perf_cpu_darken_4:
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.global _perf_cpu_double_read
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/* No problem here -> 2 cycles /i */
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.align 4
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_perf_cpu_double_read:
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PROLOGUE(1024)
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@ -425,6 +478,7 @@ _perf_cpu_double_read:
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.global _perf_cpu_double_incr_read
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/* Post-increment feeds into address much faster than ALU -> 2 cycles /i */
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.align 4
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_perf_cpu_double_incr_read:
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PROLOGUE(1024)
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@ -435,6 +489,21 @@ _perf_cpu_double_incr_read:
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2: mov.b @r4+, r0
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EPILOGUE()
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.global _perf_cpu_double_write
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/* No delay writing twice, whether with r4/r4 or r4/r5 -> 2 cycles/i */
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.align 4
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_perf_cpu_double_write:
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PROLOGUE(1024)
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mov.l .buffer, r4
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mov.l @r4, r0
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mov r0, r1
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mov r4, r5
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1: mov.l r0, @r4
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2: mov.l r1, @r5
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EPILOGUE()
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/* [2D texture copy]
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This section is used to investigate the performance of the 2D texture shader
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@ -41,9 +41,9 @@ int Iphi_cycles_per_iteration(int total, int count)
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{
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div_t d = div(total, count);
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if(d.rem < 128)
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if(d.rem < 192)
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return d.quot;
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if(d.rem > count - 128)
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if(d.rem > count - 192)
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return d.quot + 1;
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return -1;
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@ -72,11 +72,11 @@ struct results {
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int EX_EX, MT_MT, LS_LS;
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int align_4, align_2;
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int pipeline_1, pipeline_2, pipeline_3;
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int raw_EX_EX, raw_LS_LS, raw_EX_LS, raw_LS_EX;
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int raw_EX_EX, raw_LS_LS, raw_EX_LS, raw_LS_EX, raw_LS_MT;
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int noraw_LS_LS, noraw_LS_EX;
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int raw_EX_LS_addr, raw_DSPLS_DSPLS;
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int raw_EX_LS_addr, raw_LS_LS_addr, raw_DSPLS_DSPLS;
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int darken_1, darken_2, darken_3, darken_4;
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int double_read, double_incr_read;
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int double_read, double_incr_read, double_write;
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#ifdef FXCG50
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int tex2d;
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#endif
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@ -94,13 +94,13 @@ static void table_gen(gtable *t, int row)
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"mac.w/nop pipeline", "mac.w/mac.w pipeline",
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"mac.w/nop*5 pipeline",
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"RAW dep.: EX/EX", "RAW dep.: LS/LS", "RAW dep.: EX/LS",
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"RAW dep.: LS/EX",
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"RAW dep.: LS/EX", "RAW dep.: LS/MT",
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"No dep.: LS/LS", "No dep.: LS/EX",
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"RAW on address: EX/LS",
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"RAW on address: EX/LS", "RAW on address: LS/LS",
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"RAW dep.: DSP-LS/DSP-LS",
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"32-bit VRAM darken #1", "32-bit VRAM darken #2",
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"Interwoven darken", "Interwoven open darken",
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"Double read", "Double increment read",
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"Double read", "Double increment read", "Double write",
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"Texture2D shader",
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};
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@ -177,9 +177,11 @@ void gintctl_perf_cpu(void)
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run(raw_LS_LS, 1024);
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run(raw_EX_LS, 1024);
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run(raw_LS_EX, 1024);
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run(raw_LS_MT, 1024);
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run(noraw_LS_LS, 1024);
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run(noraw_LS_EX, 1024);
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run(raw_EX_LS_addr, 1024);
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run(raw_LS_LS_addr, 1024);
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run(raw_DSPLS_DSPLS, 512);
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run(darken_1, 512);
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@ -189,6 +191,7 @@ void gintctl_perf_cpu(void)
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run(double_read, 1024);
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run(double_incr_read, 1024);
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run(double_write, 1024);
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#ifdef FXCG50
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run(tex2d, 512);
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