From 11afe8f6b65d391ab47e3948c469a0c28c1b41eb Mon Sep 17 00:00:00 2001 From: Jeff Johnston Date: Mon, 2 May 2016 12:04:40 -0400 Subject: [PATCH] Fix support ARC processors without barrel-shifter crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores except ARC601. However instructions which shift more than 1 bit are optional, so this crt0.S didn't worked for all ARC cores. Luckily this is a shift just by 2 bits on all occassions, so fix is trivial - use two single-bit shifts. libgloss/ChangeLog 2016-04-29 Anton Kolesov * arc/crt0.S: Fix support for processors without barrel-shifter. Signed-off-by: Anton Kolesov --- libgloss/arc/crt0.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/libgloss/arc/crt0.S b/libgloss/arc/crt0.S index b93b63e4c..99c871f21 100644 --- a/libgloss/arc/crt0.S +++ b/libgloss/arc/crt0.S @@ -135,7 +135,12 @@ __start: mov_s r2, @__sbss_start ; r2 = start of the bss section sub r3, @_end, r2 ; r3 = size of the bss section in bytes ; set up the loop counter register to the size (in words) of the bss section - asr.f lp_count, r3, 2 +#if defined (__ARC_BARREL_SHIFTER__) + asr.f lp_count, r3, 2 +#else + asr_s r13, r3 + asr.f lp_count, r13 +#endif #if defined (__ARC600__) ; loop to zero out the bss. Enter loop only if lp_count != 0 lpnz @.Lend_zbss