2006-12-18 Kazu Hirata <kazu@codesourcery.com>
Merge from newlib-csl-20060320-branch:
2006-12-15 Daniel Jacobowitz <dan@codesourcery.com>
* m68k/fido-crt0.S (_vector_table): Reference
_PrivilegeViolationHandler.
2006-12-15 Daniel Jacobowitz <dan@codesourcery.com>
* m68k/fido-crt0.S (_start): Set %vbr for context 0 in
RAM configs.
* m68k/fido.sc: Clean up formatting. Add comments. Move
stack and heap end to SDRAM for SRAM and SDRAM configurations.
Put RedBoot application text in SRAM.
2006-12-13 Nathan Sidwell <nathan@codesourcery.com>
* m68k/Makefile (install_cf): Don't loop over files here. Only
install sources for the default multilib.
(install_fido): Likewise.
(install_io): Install bsps in one go.
2006-12-01 Nathan Sidwell <nathan@codesourcery.com>
Kazu Hirata <kazu@codesourcery.com>
* configure.in: Recognize fido-*-*.
* configure: Regenerate.
* m68k/Makefile.in (CF_ISRS): Use addprefix.
(FIDO_CRT0, FIDO_BSP, FIDO_OBJS, FIDO_HANDLERS,
FIDO_UNHOSTED_SCRIPTS, FIDO_HOSTED_SCRIPTS, FIDO_SCRIPTS,
FIDO_SOURCES, all_fido, fido-%-crt0.o, fido-rom.ld,
fido-rom-hosted.ld, fido-sram.ld, fido-sram-hosted.ld,
fido-sdram.ld, fido-sdram-hosted.ld, fido-redboot.ld,
install_fido): New.
* m68k/asm.h (mbb): New.
* m68k/configure.in (DO): Check for __mfido__.
* m68k/configure: Regenerate.
* m68k/fido-_exit.c, m68k/fido-crt0.S, m68k/fido-handler.c,
m68k/fido-hosted.S, m68k/fido-sbrk.c, m68k/fido.h,
m68k/fido.sc, m68k/fido_profiling.h: New.
This commit is contained in:
Jeff Johnston
parent
e09c8fde55
commit
1b69cb3ac5
|
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@ -1,3 +1,45 @@
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|||
2006-12-18 Kazu Hirata <kazu@codesourcery.com>
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Merge from newlib-csl-20060320-branch:
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2006-12-15 Daniel Jacobowitz <dan@codesourcery.com>
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* m68k/fido-crt0.S (_vector_table): Reference
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_PrivilegeViolationHandler.
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2006-12-15 Daniel Jacobowitz <dan@codesourcery.com>
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* m68k/fido-crt0.S (_start): Set %vbr for context 0 in
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RAM configs.
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* m68k/fido.sc: Clean up formatting. Add comments. Move
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stack and heap end to SDRAM for SRAM and SDRAM configurations.
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Put RedBoot application text in SRAM.
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2006-12-13 Nathan Sidwell <nathan@codesourcery.com>
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* m68k/Makefile (install_cf): Don't loop over files here. Only
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install sources for the default multilib.
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(install_fido): Likewise.
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(install_io): Install bsps in one go.
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2006-12-01 Nathan Sidwell <nathan@codesourcery.com>
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Kazu Hirata <kazu@codesourcery.com>
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* configure.in: Recognize fido-*-*.
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* configure: Regenerate.
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* m68k/Makefile.in (CF_ISRS): Use addprefix.
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(FIDO_CRT0, FIDO_BSP, FIDO_OBJS, FIDO_HANDLERS,
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FIDO_UNHOSTED_SCRIPTS, FIDO_HOSTED_SCRIPTS, FIDO_SCRIPTS,
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FIDO_SOURCES, all_fido, fido-%-crt0.o, fido-rom.ld,
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fido-rom-hosted.ld, fido-sram.ld, fido-sram-hosted.ld,
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fido-sdram.ld, fido-sdram-hosted.ld, fido-redboot.ld,
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install_fido): New.
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* m68k/asm.h (mbb): New.
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* m68k/configure.in (DO): Check for __mfido__.
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* m68k/configure: Regenerate.
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* m68k/fido-_exit.c, m68k/fido-crt0.S, m68k/fido-handler.c,
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m68k/fido-hosted.S, m68k/fido-sbrk.c, m68k/fido.h,
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m68k/fido.sc, m68k/fido_profiling.h: New.
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2006-12-18 Ben Elliston <bje@au.ibm.com>
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* spu/stat.c (stat): Cast new sys.pathname value to unsigned int.
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@ -1847,7 +1847,7 @@ subdirs="$subdirs m68hc11"
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config_testsuite=true
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;;
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m68*-*-*)
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fido-*-* | m68*-*-*)
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subdirs="$subdirs m68k"
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@ -42,7 +42,7 @@ case "${target}" in
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AC_CONFIG_SUBDIRS(m68hc11)
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config_testsuite=true
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;;
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m68*-*-*)
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fido-*-* | m68*-*-*)
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AC_CONFIG_SUBDIRS(m68k)
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config_testsuite=true
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;;
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@ -152,6 +152,36 @@ CF_HOSTED_SCRIPTS := $(patsubst %.ld,%-hosted.ld,$(CF_RAM_SCRIPTS) $(CF_ROM_SCRI
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CF_SCRIPTS = $(CF_RAM_SCRIPTS) $(CF_ROM_SCRIPTS) $(CF_HOSTED_SCRIPTS)
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CF_SOURCES = cf-isv.S cf-crt0.S cf-crt1.c asm.h
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# Fido board.
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# Programs built with the ROM linker script are designed to be
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# executed from flash. Programs built with the RAM linker script are
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# designed to be run via JTAG. Program built with the RedBoot linker
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# script are designed to be run from the RedBoot boot loader.
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FIDO_CRT0S = fido-rom-crt0.o fido-ram-crt0.o fido-redboot-crt0.o
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FIDO_BSP = libfido.a
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FIDO_OBJS = fido-hosted.o getpid.o kill.o fido-sbrk.o fido-_exit.o \
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$(patsubst %,fido-%Handler.o,$(FIDO_HANDLERS))
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FIDO_HANDLERS:= BusError AddressError IllegalInstruction DivideByZero Chk \
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Trapcc PrivilegeViolation Trace ALine FLine HwBreakpoint Reserved0 \
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FormatError UnitializedInt SoftwareInt \
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$(addprefix Unassigned,0 1 2 3 4 5 6) \
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$(addprefix Int,0 1 2 3 4 5 6 7) \
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$(addprefix Trap,00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15) \
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$(addprefix Reserved,048 049 050 051 052 053 054 055 056 057 058 \
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059 060 061 062 063) \
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ContextOvertime MpuError \
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$(addprefix SystemTimer,0 1 2 3 4) \
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WatchdogTimer TimerCounter0 TimerCounter1 DMA0 DMA1 AtoDConversion \
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$(addprefix Pdma,0 1 2 3) \
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$(addprefix Reserved,081 082 083 084 085 086 087 088 089 \
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090 091 092 093 094 095) \
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$(addprefix Trapx,00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15) \
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Dummy
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FIDO_UNHOSTED_SCRIPTS:= fido-rom.ld fido-sram.ld fido-sdram.ld
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FIDO_HOSTED_SCRIPTS:=$(patsubst %.ld,%-hosted.ld,$(FIDO_UNHOSTED_SCRIPTS))
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FIDO_SCRIPTS = $(FIDO_UNHOSTED_SCRIPTS) $(FIDO_HOSTED_SCRIPTS) fido-redboot.ld
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FIDO_SOURCES = fido-crt0.S asm.h fido.h
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#
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# here's all the unhosted stuff
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#
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@ -183,6 +213,10 @@ all_m68k :: ${SIM_CRT0} ${SIM_BSP} ${CRT0} ${BCC_BSP} ${IDP_BSP} \
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.PHONY: all_cf
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all_cf :: ${CF_CRT0S} ${CF_BSP} ${CF_SCRIPTS} ${HOSTED_BSP} ${UNHOSTED_BSP}
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.PHONY: all_fido
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all_fido :: ${FIDO_CRT0S} ${FIDO_BSP} ${FIDO_SCRIPTS} \
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${HOSTED_BSP} ${UNHOSTED_BSP}
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${SIM_BSP}: ${SIM_OBJS}
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${AR} ${ARFLAGS} $@ ${SIM_OBJS}
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${RANLIB} $@
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@ -246,6 +280,39 @@ m%-rom-hosted.ld : cf.sc Makefile
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IO=hosted RAM=$(word 1,$(m$*)) RAM_SIZE=$(word 2,$(m$*)) \
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ROM=$(word 3,$(m$*)) ROM_SIZE=$(word 4,$(m$*)) ${SHELL} $< >$@
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#build fido library
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fido-%-crt0.o : fido-crt0.S asm.h fido.h
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$(CC) $(CFLAGS_FOR_TARGET) $(CFLAGS) $(INCLUDES) \
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-DFIDO_$* -c -o $@ $<
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$(patsubst %,fido-%Handler.o,${FIDO_HANDLERS}) : fido-handler.c
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$(CC) $(CFLAGS_FOR_TARGET) -fomit-frame-pointer $(CFLAGS) $(INCLUDES) \
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-c $< -o $@ -DHANDLER=$(patsubst fido-%.o,_%,$@)
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${FIDO_BSP}: ${FIDO_OBJS}
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${AR} ${ARFLAGS} $@ ${FIDO_OBJS}
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${RANLIB} $@
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fido-rom.ld: fido.sc
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MODE=rom IO=unhosted ${SHELL} $< > $@
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fido-rom-hosted.ld: fido.sc
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MODE=rom IO=hosted ${SHELL} $< > $@
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fido-sram.ld: fido.sc
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MODE=sram IO=unhosted ${SHELL} $< > $@
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fido-sram-hosted.ld: fido.sc
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MODE=sram IO=hosted ${SHELL} $< > $@
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fido-sdram.ld: fido.sc
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MODE=sdram IO=unhosted ${SHELL} $< > $@
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fido-sdram-hosted.ld: fido.sc
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MODE=sdram IO=hosted ${SHELL} $< > $@
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fido-redboot.ld: fido.sc
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MODE=redboot IO=unhosted ${SHELL} $< > $@
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leds.o: ${srcdir}/leds.c
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$(CC) $(CFLAGS_FOR_TARGET) $(CFLAGS) $(INCLUDES) -c $<
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@ -372,22 +439,32 @@ install_m68k::
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.PHONY: install_cf
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install_cf:: install_io
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# install CF stuff
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for crt in $(CF_CRT0S) ; \
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do $(INSTALL_DATA) $$crt $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$$crt ; \
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done
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$(INSTALL_DATA) $(CF_BSP) $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$(CF_BSP)
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for script in $(CF_SCRIPTS) ; \
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do $(INSTALL_DATA) $$script $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$$script ; \
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done
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for src in $(CF_SOURCES) ; \
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do $(INSTALL_DATA) ${srcdir}/$$src $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$$src ; \
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done
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$(INSTALL_DATA) $(CF_CRT0S) $(CF_BSP) \
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$(DESTDIR)$(tooldir)/lib${MULTISUBDIR}
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$(INSTALL_DATA) $(CF_SCRIPTS) $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}
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ifeq ($(MULTISUBDIR),)
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# only install sources for the default multilib
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$(INSTALL_DATA) $(addprefix ${srcdir}/,$(CF_SOURCES)) \
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$(DESTDIR)$(tooldir)/lib${MULTISUBDIR}
|
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endif
|
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|
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.PHONY: install_fido
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install_fido:: install_io
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$(INSTALL_DATA) $(FIDO_CRT0S) $(FIDO_BSP) \
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$(DESTDIR)$(tooldir)/lib$(MULTISUBDIR)
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$(INSTALL_DATA) $(FIDO_SCRIPTS) $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}
|
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ifeq ($(MULTISUBDIR),)
|
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# only install sources for the default multilib
|
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$(INSTALL) -d $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/src
|
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$(INSTALL_DATA) $(addprefix $(srcdir)/,$(FIDO_SOURCES)) \
|
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$(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/src
|
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endif
|
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|
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.PHONY: install_io
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install_io::
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# install IO stuff
|
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$(INSTALL_DATA) $(HOSTED_BSP) $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$(HOSTED_BSP)
|
||||
$(INSTALL_DATA) $(UNHOSTED_BSP) $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$(UNHOSTED_BSP)
|
||||
$(INSTALL_DATA) $(HOSTED_BSP) $(UNHOSTED_BSP) \
|
||||
$(DESTDIR)$(tooldir)/lib${MULTISUBDIR}
|
||||
|
||||
# target specific makefile fragment comes in here.
|
||||
@target_makefile_frag@
|
||||
|
|
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|||
|
|
@ -3173,6 +3173,37 @@ else
|
|||
sed 's/^/| /' conftest.$ac_ext >&5
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||||
|
||||
|
||||
fi
|
||||
rm -f conftest.err conftest.$ac_ext
|
||||
cat >conftest.$ac_ext <<_ACEOF
|
||||
#ifndef __mfido__
|
||||
#error we are not fido
|
||||
#endif
|
||||
_ACEOF
|
||||
if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
|
||||
(eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
|
||||
ac_status=$?
|
||||
grep -v '^ *+' conftest.er1 >conftest.err
|
||||
rm -f conftest.er1
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:$LINENO: \$? = $ac_status" >&5
|
||||
(exit $ac_status); } >/dev/null; then
|
||||
if test -s conftest.err; then
|
||||
ac_cpp_err=$ac_c_preproc_warn_flag
|
||||
ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
|
||||
else
|
||||
ac_cpp_err=
|
||||
fi
|
||||
else
|
||||
ac_cpp_err=yes
|
||||
fi
|
||||
if test -z "$ac_cpp_err"; then
|
||||
DO="fido"
|
||||
else
|
||||
echo "$as_me: failed program was:" >&5
|
||||
sed 's/^/| /' conftest.$ac_ext >&5
|
||||
|
||||
|
||||
fi
|
||||
rm -f conftest.err conftest.$ac_ext
|
||||
LDFLAGS=$saved_LDFLAGS
|
||||
|
|
|
|||
|
|
@ -58,6 +58,10 @@ AC_PREPROC_IFELSE([#ifndef __mcoldfire__
|
|||
#error we are not coldfire
|
||||
#endif],
|
||||
DO="cf",)
|
||||
AC_PREPROC_IFELSE([#ifndef __mfido__
|
||||
#error we are not fido
|
||||
#endif],
|
||||
DO="fido",)
|
||||
LDFLAGS=$saved_LDFLAGS
|
||||
AC_MSG_RESULT($DO)
|
||||
AC_SUBST(DO)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2006 CodeSourcery, Inc.
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
__attribute__((noreturn))
|
||||
void
|
||||
_exit (int code)
|
||||
{
|
||||
while (1)
|
||||
asm volatile ("stop #0");
|
||||
}
|
||||
|
|
@ -0,0 +1,600 @@
|
|||
/**
|
||||
* fido-crt0.S -- Simple startup code
|
||||
*
|
||||
* Copyright (c) 1995, 1996, 1998 Cygnus Support
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*
|
||||
* Copyright 2006 Innovasic Semiconductor, All Rights Reserved.
|
||||
* Part of the fido Realtime Support Library
|
||||
*
|
||||
* Description:
|
||||
* This routine performs initializations assuming a Fido
|
||||
* development board. In order, the following functions are performed:
|
||||
*
|
||||
* -- memory offset register initialization
|
||||
* -- chip select register initialization for external memory
|
||||
* -- SDRAM ctrl register initialization for external memory
|
||||
* -- in line test of external SRAM
|
||||
* -- sets user SP for MasterContext0 (main)
|
||||
* -- copies the bss section to RAM
|
||||
* -- transfers control to MasterContext0 (main)
|
||||
*
|
||||
*/
|
||||
|
||||
#include "asm.h"
|
||||
#include "fido.h"
|
||||
|
||||
.title "fido-crt0.S for Fido"
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
//--------- 66 MHz values --------
|
||||
// set up CS0 for flash
|
||||
#define CS0_CTRL_VAL 0x0000024A
|
||||
#define CS0_TIMING_VAL 0x01000000
|
||||
|
||||
// set up CS1 for SDRAM
|
||||
#define CS1_CTRL_VAL 0x0200030A /* selects SDRAM ctrl instead of CS1 */
|
||||
#define CS1_TIMING_VAL 0x00000000 /* N/A for SDRAM operation */
|
||||
#define SDRAM_TIMING_0_VAL 0x00022522 /* TRP=0x2, TRCD=0x2, TRF=0x5, TWR=0x5 TCL=0x5 */
|
||||
#define SDRAM_TIMING_1_VAL 0x00120407 /* INI_PREC=0x1, INI_REFT=0x2, REF_INTV=0x407 */
|
||||
#define SDRAM_CONFIG_0_VAL 0x00002113 /* MA2T=0, DDW=x16device=0x2, dsz=64MBit, mbw=16bit, bnksz=8Mbyte */
|
||||
#define SDRAM_CONFIG_1_VAL 0x00000000 /* IPREC=0, IREF=0, ISMR=0, PWDN=0, SREF=0 */
|
||||
#define SDRAM_EXT_BANK_1_VAL 0x00001020 /* SDRAM memory bank 0 at addr 0x0200_0000 */
|
||||
|
||||
// set up CS2 for SRAM
|
||||
#define CS2_CTRL_VAL 0x03000267
|
||||
#define CS2_TIMING_VAL 0x08400000
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#define EXT_SRAM_END_ADDR 0x30FFFFC /* 1 MB of ext. SRAM (2-512Kx8 chips) */
|
||||
#define PERP_PWRUP_MASK 0x0000 /* turn on all peripherals */
|
||||
|
||||
/*
|
||||
* Define an empty environment.
|
||||
*/
|
||||
.data 2
|
||||
.align 2
|
||||
SYM (environ):
|
||||
.long 0
|
||||
|
||||
.align 2
|
||||
.text 2
|
||||
|
||||
/*
|
||||
* These symbols are defined in C code, so they need to always be
|
||||
* named with SYM because of the difference between object file formats.
|
||||
*/
|
||||
|
||||
/* These are defined in C code. */
|
||||
/* .extern SYM (main) */
|
||||
.extern SYM (exit)
|
||||
.extern SYM (hardware_init_hook)
|
||||
.extern SYM (software_init_hook)
|
||||
.extern SYM (atexit)
|
||||
.extern SYM (__do_global_dtors)
|
||||
/*
|
||||
* These values are set in the linker script, so they must be
|
||||
* explicitly named here without SYM.
|
||||
*/
|
||||
#ifdef FIDO_rom
|
||||
.extern __stack
|
||||
#endif
|
||||
.extern __bss_start
|
||||
.extern _end
|
||||
|
||||
/*
|
||||
* set things up so application will run. This *must* be called _start.
|
||||
*/
|
||||
.global SYM (_start)
|
||||
|
||||
SYM (_start):
|
||||
|
||||
#ifdef FIDO_rom
|
||||
/* save initial value of base offset register */
|
||||
movec mbb,d7
|
||||
|
||||
/* Initialize memory offset register to offset value in FIDOmemmap.h */
|
||||
movel #FIDO_MEM_OFFSET,d0 /* Load memory offset into REG d0 */
|
||||
movec d0,mbb
|
||||
|
||||
movel #0x011, FIDO_DBG_CTRL /* set the debug control reg */
|
||||
|
||||
/* At POR the PerpPowerCtrlReg is set to 0x3F0F, all peripherals off
|
||||
See PerpPowerCtrlReg definition, this example turns ON everything */
|
||||
movel #PERP_PWRUP_MASK,FIDO_CLOCK_MASK_REGISTER
|
||||
|
||||
/* Set up chip selects for ROM, SRAM, and SDRAM (all external mem.) */
|
||||
movel #CS0_CTRL_VAL, FIDO_BIU_CS0_CONTROL /* flash memory CS0 */
|
||||
movel #CS0_TIMING_VAL, FIDO_BIU_CS0_TIMING
|
||||
|
||||
movel #CS2_CTRL_VAL, FIDO_BIU_CS2_CONTROL /* SRAM memory CS2 */
|
||||
movel #CS2_TIMING_VAL, FIDO_BIU_CS2_TIMING
|
||||
|
||||
/* if this is not POR then say so */
|
||||
movel FIDO_POR_REG,d6
|
||||
|
||||
/* test external SRAM -- */
|
||||
/* a0 == working pointer */
|
||||
/* a1 == pointer to base of memory */
|
||||
/* a2 == pointer to end of memory */
|
||||
/* d0,d1,d2,d3 working registers */
|
||||
|
||||
moveal #0x3000000,a1
|
||||
moveal #0x30FFFFC,a2
|
||||
|
||||
movel a1,a0
|
||||
/* walking ones */
|
||||
movel #1,d0
|
||||
|
||||
.LWalkOnes:
|
||||
movel d0, (a0) /* write value out */
|
||||
cmpl (a0), d0 /* read it back */
|
||||
bne .LFailOnes
|
||||
lsl.l #1, d0 /* move to next value */
|
||||
bne .LWalkOnes /* when it goes to zero you're done */
|
||||
bra .LValTest
|
||||
.LFailOnes:
|
||||
movel #0x01, d0
|
||||
bra .LMemTestEnd
|
||||
|
||||
.LValTest:
|
||||
/* ffff's */
|
||||
/* 5555's */
|
||||
/* aaaa's */
|
||||
/* 0000's */
|
||||
movel a1,a0
|
||||
movel #0xFFFFFFFF,d0
|
||||
|
||||
.LValLoop:
|
||||
movel d0,(a0) /* write value out */
|
||||
cmpl (a0)+, d0 /* compare and move to next */
|
||||
bne .LFailVal
|
||||
cmpl a0,a2 /* at end of memory? */
|
||||
bge .LValLoop
|
||||
movel d0,d0 /* done writing zeros? */
|
||||
beq .LAddrTest
|
||||
movel a1,a0 /* go back to start with next value */
|
||||
subl #0x55555555,d0 /* get next value (f->a->5->0) */
|
||||
bra .LValLoop
|
||||
.LFailVal:
|
||||
movel #0x02, d0
|
||||
bra .LMemTestEnd
|
||||
|
||||
.LAddrTest:
|
||||
/* unique values */
|
||||
movel a1,a0
|
||||
.LWriteLoop:
|
||||
movel a0, (a0)+ /* write value out and move one */
|
||||
cmpl a0,a2 /* look for end of memory */
|
||||
bge .LWriteLoop
|
||||
|
||||
movel a1,a0
|
||||
.LReadLoop:
|
||||
cmpl (a0), a0 /* compare value and move on */
|
||||
bne .LFailAddr
|
||||
addql #4,a0
|
||||
cmpl a0,a2 /* look for end of memory */
|
||||
bge .LReadLoop
|
||||
clrl d0 /* everything passed */
|
||||
bra .LMemTestEnd
|
||||
|
||||
.LFailAddr:
|
||||
movel #0x03, d0
|
||||
|
||||
.LMemTestEnd:
|
||||
movel d0,d4 /* mem test result in d4 0 == pass */
|
||||
#endif /* ROM */
|
||||
|
||||
/* See if user supplied their own stack (__stack != 0). If not, then
|
||||
* default to using the value of %sp as set by the ROM monitor */
|
||||
movel IMM(__stack), a0
|
||||
cmpl IMM(0), a0
|
||||
jbeq .Lloc1
|
||||
movel a0, sp
|
||||
.Lloc1:
|
||||
/* set up initial stack frame */
|
||||
link a6, IMM(-8)
|
||||
|
||||
#ifdef FIDO_rom
|
||||
/*
|
||||
* Now set up the SDRAM (waited to let the controller spin up)
|
||||
*/
|
||||
/* always initialize SDRAM regs, they're cleared by any reset */
|
||||
/* SDRAM enbl bit set in CS1 re-directs to SDRAM controller regs */
|
||||
|
||||
movel #CS1_CTRL_VAL, FIDO_BIU_CS1_CONTROL /* SDRAM memory CS1 */
|
||||
movel #SDRAM_TIMING_0_VAL, FIDO_SDRAM_TIMING_0 /* SDRAM TIMING REG0 */
|
||||
movel #SDRAM_TIMING_1_VAL, FIDO_SDRAM_TIMING_1 /* SDRAM TIMING REG1 */
|
||||
movel #SDRAM_CONFIG_0_VAL, FIDO_SDRAM_CONFIG_0 /* SDRAM CONFIG REG */
|
||||
movel #0x0000001c, FIDO_SDRAM_CONFIG_1 /* SDRAM CONFIG REG */
|
||||
|
||||
.LsdConfigLoop:
|
||||
movel FIDO_SDRAM_CONFIG_1,d0
|
||||
cmpl #0x00000000,d0
|
||||
bne .LsdConfigLoop
|
||||
|
||||
movel #SDRAM_EXT_BANK_1_VAL, FIDO_SDRAM_EXT_BANK_1 /* BANK 1 REG */
|
||||
|
||||
/*
|
||||
* copy data from ROM to RAM
|
||||
*/
|
||||
|
||||
moval IMM(__start_romdata),a0 /* begin data in ROM */
|
||||
moval IMM(_data), a1 /* begin data in RAM */
|
||||
moval IMM(_edata),a2 /* end of data in RAM */
|
||||
|
||||
/* while(a1 < a2) *a1++ = *a0++; */
|
||||
.LdataCopyLoop:
|
||||
movel (a0)+,(a1)+
|
||||
cmpal a1,a2
|
||||
bgt .LdataCopyLoop
|
||||
#endif /* ROM */
|
||||
|
||||
#ifdef FIDO_ram
|
||||
/* For ROM configs, the linker script ensures that
|
||||
_vector_table is placed at the proper place. For RAM
|
||||
configs, we have to adjust it ourselves. */
|
||||
movel IMM (SYM (_vector_table)), FIDO_CTX0_VBR
|
||||
#endif
|
||||
|
||||
#ifndef FIDO_redboot
|
||||
/* Setup interrupt vectors for secondary contexts. */
|
||||
movel IMM (SYM (_vector_table1)), FIDO_CTX1_VBR
|
||||
movel IMM (SYM (_vector_table2)), FIDO_CTX2_VBR
|
||||
movel IMM (SYM (_vector_table3)), FIDO_CTX3_VBR
|
||||
movel IMM (SYM (_vector_table4)), FIDO_CTX4_VBR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* zero out the bss section.
|
||||
*/
|
||||
movel IMM(__bss_start), d1
|
||||
movel IMM(_end), d0
|
||||
cmpl d0, d1
|
||||
jbeq .Lloc3
|
||||
movl d1, a0
|
||||
subl d1, d0
|
||||
subql IMM(1), d0
|
||||
2:
|
||||
clrb (a0)+
|
||||
#ifndef __mcf5200__
|
||||
dbra d0, 2b
|
||||
clrw d0
|
||||
subql IMM(1), d0
|
||||
jbcc 2b
|
||||
#else
|
||||
subql IMM(1), d0
|
||||
jbpl 2b
|
||||
#endif
|
||||
|
||||
.Lloc3:
|
||||
|
||||
#ifdef ADD_DTORS
|
||||
/* put __do_global_dtors in the atexit list so the destructors get run */
|
||||
movel IMM (SYM(__do_global_dtors)),(sp)
|
||||
jsr SYM (atexit)
|
||||
#endif
|
||||
movel IMM (__FINI_SECTION__),(sp)
|
||||
jsr SYM (atexit)
|
||||
|
||||
jsr __INIT_SECTION__
|
||||
|
||||
/*
|
||||
* call the main routine from the application to get it going.
|
||||
* main (argc, argv, environ)
|
||||
* we pass argv as a pointer to NULL.
|
||||
*/
|
||||
|
||||
pea 0
|
||||
pea SYM (environ)
|
||||
pea sp@(4)
|
||||
pea 0
|
||||
jsr SYM (main) /* call to main */
|
||||
movel d0, sp@-
|
||||
|
||||
/*
|
||||
* drop down into exit in case the user doesn't. This should drop
|
||||
* control back to the ROM monitor, if there is one. This calls the
|
||||
* exit() from the C library so the C++ tables get cleaned up right.
|
||||
*/
|
||||
jsr SYM (exit)
|
||||
|
||||
#ifndef FIDO_redboot
|
||||
/* Define the interrupt vector table. The linker script
|
||||
ensures that the table is placed at address zero. */
|
||||
.section .vector_table,"a"
|
||||
|
||||
.global SYM (_vector_table)
|
||||
|
||||
SYM (_vector_table):
|
||||
|
||||
dc.l __stack /* 000 Initial Stack */
|
||||
dc.l _start /* 001 Context 0 Start */
|
||||
dc.l _BusErrorHandler /* 002 Bus Error */
|
||||
dc.l _AddressErrorHandler /* 003 Address Error */
|
||||
dc.l _IllegalInstructionHandler /* 004 Illegal Instruction */
|
||||
dc.l _DivideByZeroHandler /* 005 Divide by Zero */
|
||||
dc.l _ChkHandler /* 006 CHK, CHK2 Instructions */
|
||||
dc.l _TrapccHandler /* 007 TRAPcc, TRAPV Instructions */
|
||||
dc.l _PrivilegeViolationHandler /* 008 Privilege Violation */
|
||||
dc.l _TraceHandler /* 009 Trace */
|
||||
dc.l _ALineHandler /* 010 A-Line Unimplemented Instr */
|
||||
dc.l _FLineHandler /* 011 F-Line Unimplemented Instr */
|
||||
dc.l _HwBreakpointHandler /* 012 Hardware Breakpoint */
|
||||
dc.l _Reserved0Handler /* 013 Reserved */
|
||||
dc.l _FormatErrorHandler /* 014 Format Error */
|
||||
dc.l _UnitializedIntHandler /* 015 Unitialized Interrupt */
|
||||
dc.l _SoftwareIntHandler /* 016 Software Interrupt */
|
||||
dc.l _Unassigned0Handler /* 017 Unassigned */
|
||||
dc.l _Unassigned1Handler /* 018 Unassigned */
|
||||
dc.l _Unassigned2Handler /* 019 Unassigned */
|
||||
dc.l _Unassigned3Handler /* 020 Unassigned */
|
||||
dc.l _Unassigned4Handler /* 021 Unassigned */
|
||||
dc.l _Unassigned5Handler /* 022 Unassigned */
|
||||
dc.l _Unassigned6Handler /* 023 Unassigned */
|
||||
dc.l _Int0Handler /* 024 Interrupt 0 */
|
||||
dc.l _Int1Handler /* 025 Interrupt 1 */
|
||||
dc.l _Int2Handler /* 026 Interrupt 2 */
|
||||
dc.l _Int3Handler /* 027 Interrupt 3 */
|
||||
dc.l _Int4Handler /* 028 Interrupt 4 */
|
||||
dc.l _Int5Handler /* 029 Interrupt 5 */
|
||||
dc.l _Int6Handler /* 030 Interrupt 6 */
|
||||
dc.l _Int7Handler /* 031 Interrupt 7 */
|
||||
dc.l _Trap00Handler /* 032 Trap #00 Instruction */
|
||||
dc.l _Trap01Handler /* 033 Trap #01 Instruction */
|
||||
dc.l _Trap02Handler /* 034 Trap #02 Instruction */
|
||||
dc.l _Trap03Handler /* 035 Trap #03 Instruction */
|
||||
dc.l _Trap04Handler /* 036 Trap #04 Instruction */
|
||||
dc.l _Trap05Handler /* 037 Trap #05 Instruction */
|
||||
dc.l _Trap06Handler /* 038 Trap #06 Instruction */
|
||||
dc.l _Trap07Handler /* 039 Trap #07 Instruction */
|
||||
dc.l _Trap08Handler /* 040 Trap #08 Instruction */
|
||||
dc.l _Trap09Handler /* 041 Trap #09 Instruction */
|
||||
dc.l _Trap10Handler /* 042 Trap #10 Instruction */
|
||||
dc.l _Trap11Handler /* 043 Trap #11 Instruction */
|
||||
dc.l _Trap12Handler /* 044 Trap #12 Instruction */
|
||||
dc.l _Trap13Handler /* 045 Trap #13 Instruction */
|
||||
dc.l _Trap14Handler /* 046 Trap #14 Instruction */
|
||||
dc.l _Trap15Handler /* 047 Trap #15 Instruction */
|
||||
dc.l _Reserved048Handler /* 048 Reserved */
|
||||
dc.l _Reserved049Handler /* 049 Reserved */
|
||||
dc.l _Reserved050Handler /* 050 Reserved */
|
||||
dc.l _Reserved051Handler /* 051 Reserved */
|
||||
dc.l _Reserved052Handler /* 052 Reserved */
|
||||
dc.l _Reserved053Handler /* 053 Reserved */
|
||||
dc.l _Reserved054Handler /* 054 Reserved */
|
||||
dc.l _Reserved055Handler /* 055 Reserved */
|
||||
dc.l _Reserved056Handler /* 056 Reserved */
|
||||
dc.l _Reserved057Handler /* 057 Reserved */
|
||||
dc.l _Reserved058Handler /* 058 Reserved */
|
||||
dc.l _Reserved059Handler /* 059 Reserved */
|
||||
dc.l _Reserved060Handler /* 060 Reserved */
|
||||
dc.l _Reserved061Handler /* 061 Reserved */
|
||||
dc.l _Reserved062Handler /* 062 Reserved */
|
||||
dc.l _Reserved063Handler /* 063 Reserved */
|
||||
dc.l _ContextOvertimeHandler /* 064 Context Overtime */
|
||||
dc.l _MpuErrorHandler /* 065 MPU Error */
|
||||
dc.l _SystemTimer0Handler /* 066 System Timer 0 */
|
||||
dc.l _SystemTimer1Handler /* 067 System Timer 1 */
|
||||
dc.l _SystemTimer2Handler /* 068 System Timer 2 */
|
||||
dc.l _SystemTimer3Handler /* 069 System Timer 3 */
|
||||
dc.l _SystemTimer4Handler /* 070 System Timer 4 */
|
||||
dc.l _WatchdogTimerHandler /* 071 Watchdog Timer */
|
||||
dc.l _TimerCounter0Handler /* 072 Timer Counter 1 */
|
||||
dc.l _TimerCounter1Handler /* 073 Timer Counter 2 */
|
||||
dc.l _DMA0Handler /* 074 DMA Channel 0 */
|
||||
dc.l _DMA1Handler /* 075 DMA Channel 1 */
|
||||
dc.l _AtoDConversionHandler /* 076 A/D Conversion Complete */
|
||||
dc.l _Pdma0Handler /* 077 PDMA Ch 0 Interrupt */
|
||||
dc.l _Pdma1Handler /* 078 PDMA Ch 1 Interrupt */
|
||||
dc.l _Pdma2Handler /* 079 PDMA Ch 2 Interrupt */
|
||||
dc.l _Pdma3Handler /* 080 PDMA Ch 3 Interrupt */
|
||||
dc.l _Reserved081Handler /* 081 Reserved */
|
||||
dc.l _Reserved082Handler /* 082 Reserved */
|
||||
dc.l _Reserved083Handler /* 083 Reserved */
|
||||
dc.l _Reserved084Handler /* 084 Reserved */
|
||||
dc.l _Reserved085Handler /* 085 Reserved */
|
||||
dc.l _Reserved086Handler /* 086 Reserved */
|
||||
dc.l _Reserved087Handler /* 087 Reserved */
|
||||
dc.l _Reserved088Handler /* 088 Reserved */
|
||||
dc.l _Reserved089Handler /* 089 Reserved */
|
||||
dc.l _Reserved090Handler /* 090 Reserved */
|
||||
dc.l _Reserved091Handler /* 091 Reserved */
|
||||
dc.l _Reserved092Handler /* 092 Reserved */
|
||||
dc.l _Reserved093Handler /* 093 Reserved */
|
||||
dc.l _Reserved094Handler /* 094 Reserved */
|
||||
dc.l _Reserved095Handler /* 095 Reserved */
|
||||
dc.l _Trapx00Handler /* 096 Trapx 00 Instruction */
|
||||
dc.l _Trapx01Handler /* 097 Trapx 01 Instruction */
|
||||
dc.l _Trapx02Handler /* 098 Trapx 02 Instruction */
|
||||
dc.l _Trapx03Handler /* 099 Trapx 03 Instruction */
|
||||
dc.l _Trapx04Handler /* 100 Trapx 04 Instruction */
|
||||
dc.l _Trapx05Handler /* 101 Trapx 05 Instruction */
|
||||
dc.l _Trapx06Handler /* 102 Trapx 06 Instruction */
|
||||
dc.l _Trapx07Handler /* 103 Trapx 07 Instruction */
|
||||
dc.l _Trapx08Handler /* 104 Trapx 08 Instruction */
|
||||
dc.l _Trapx09Handler /* 105 Trapx 09 Instruction */
|
||||
dc.l _Trapx10Handler /* 106 Trapx 10 Instruction */
|
||||
dc.l _Trapx11Handler /* 107 Trapx 11 Instruction */
|
||||
dc.l _Trapx12Handler /* 108 Trapx 12 Instruction */
|
||||
dc.l _Trapx13Handler /* 109 Trapx 13 Instruction */
|
||||
dc.l _Trapx14Handler /* 110 Trapx 14 Instruction */
|
||||
dc.l _Trapx15Handler /* 111 Trapx 15 Instruction */
|
||||
dc.l _DummyHandler /* 112 */
|
||||
dc.l _DummyHandler /* 113 */
|
||||
dc.l _DummyHandler /* 114 */
|
||||
dc.l _DummyHandler /* 115 */
|
||||
dc.l _DummyHandler /* 116 */
|
||||
dc.l _DummyHandler /* 117 */
|
||||
dc.l _DummyHandler /* 118 */
|
||||
dc.l _DummyHandler /* 119 */
|
||||
dc.l _DummyHandler /* 120 */
|
||||
dc.l _DummyHandler /* 121 */
|
||||
dc.l _DummyHandler /* 122 */
|
||||
dc.l _DummyHandler /* 123 */
|
||||
dc.l _DummyHandler /* 124 */
|
||||
dc.l _DummyHandler /* 125 */
|
||||
dc.l _DummyHandler /* 126 */
|
||||
dc.l _DummyHandler /* 127 */
|
||||
dc.l _DummyHandler /* 128 */
|
||||
dc.l _DummyHandler /* 129 */
|
||||
dc.l _DummyHandler /* 130 */
|
||||
dc.l _DummyHandler /* 131 */
|
||||
dc.l _DummyHandler /* 132 */
|
||||
dc.l _DummyHandler /* 133 */
|
||||
dc.l _DummyHandler /* 134 */
|
||||
dc.l _DummyHandler /* 135 */
|
||||
dc.l _DummyHandler /* 136 */
|
||||
dc.l _DummyHandler /* 137 */
|
||||
dc.l _DummyHandler /* 138 */
|
||||
dc.l _DummyHandler /* 139 */
|
||||
dc.l _DummyHandler /* 140 */
|
||||
dc.l _DummyHandler /* 141 */
|
||||
dc.l _DummyHandler /* 142 */
|
||||
dc.l _DummyHandler /* 143 */
|
||||
dc.l _DummyHandler /* 144 */
|
||||
dc.l _DummyHandler /* 145 */
|
||||
dc.l _DummyHandler /* 146 */
|
||||
dc.l _DummyHandler /* 147 */
|
||||
dc.l _DummyHandler /* 148 */
|
||||
dc.l _DummyHandler /* 149 */
|
||||
dc.l _DummyHandler /* 150 */
|
||||
dc.l _DummyHandler /* 151 */
|
||||
dc.l _DummyHandler /* 152 */
|
||||
dc.l _DummyHandler /* 153 */
|
||||
dc.l _DummyHandler /* 154 */
|
||||
dc.l _DummyHandler /* 155 */
|
||||
dc.l _DummyHandler /* 156 */
|
||||
dc.l _DummyHandler /* 157 */
|
||||
dc.l _DummyHandler /* 158 */
|
||||
dc.l _DummyHandler /* 159 */
|
||||
dc.l _DummyHandler /* 160 */
|
||||
dc.l _DummyHandler /* 161 */
|
||||
dc.l _DummyHandler /* 162 */
|
||||
dc.l _DummyHandler /* 163 */
|
||||
dc.l _DummyHandler /* 164 */
|
||||
dc.l _DummyHandler /* 165 */
|
||||
dc.l _DummyHandler /* 166 */
|
||||
dc.l _DummyHandler /* 167 */
|
||||
dc.l _DummyHandler /* 168 */
|
||||
dc.l _DummyHandler /* 169 */
|
||||
dc.l _DummyHandler /* 170 */
|
||||
dc.l _DummyHandler /* 171 */
|
||||
dc.l _DummyHandler /* 172 */
|
||||
dc.l _DummyHandler /* 173 */
|
||||
dc.l _DummyHandler /* 174 */
|
||||
dc.l _DummyHandler /* 175 */
|
||||
dc.l _DummyHandler /* 176 */
|
||||
dc.l _DummyHandler /* 177 */
|
||||
dc.l _DummyHandler /* 178 */
|
||||
dc.l _DummyHandler /* 179 */
|
||||
dc.l _DummyHandler /* 180 */
|
||||
dc.l _DummyHandler /* 181 */
|
||||
dc.l _DummyHandler /* 182 */
|
||||
dc.l _DummyHandler /* 183 */
|
||||
dc.l _DummyHandler /* 184 */
|
||||
dc.l _DummyHandler /* 185 */
|
||||
dc.l _DummyHandler /* 186 */
|
||||
dc.l _DummyHandler /* 187 */
|
||||
dc.l _DummyHandler /* 188 */
|
||||
dc.l _DummyHandler /* 189 */
|
||||
dc.l _DummyHandler /* 190 */
|
||||
dc.l _DummyHandler /* 191 */
|
||||
dc.l _DummyHandler /* 192 */
|
||||
dc.l _DummyHandler /* 193 */
|
||||
dc.l _DummyHandler /* 194 */
|
||||
dc.l _DummyHandler /* 195 */
|
||||
dc.l _DummyHandler /* 196 */
|
||||
dc.l _DummyHandler /* 197 */
|
||||
dc.l _DummyHandler /* 198 */
|
||||
dc.l _DummyHandler /* 199 */
|
||||
dc.l _DummyHandler /* 200 */
|
||||
dc.l _DummyHandler /* 201 */
|
||||
dc.l _DummyHandler /* 202 */
|
||||
dc.l _DummyHandler /* 203 */
|
||||
dc.l _DummyHandler /* 204 */
|
||||
dc.l _DummyHandler /* 205 */
|
||||
dc.l _DummyHandler /* 206 */
|
||||
dc.l _DummyHandler /* 207 */
|
||||
dc.l _DummyHandler /* 208 */
|
||||
dc.l _DummyHandler /* 209 */
|
||||
dc.l _DummyHandler /* 210 */
|
||||
dc.l _DummyHandler /* 211 */
|
||||
dc.l _DummyHandler /* 212 */
|
||||
dc.l _DummyHandler /* 213 */
|
||||
dc.l _DummyHandler /* 214 */
|
||||
dc.l _DummyHandler /* 215 */
|
||||
dc.l _DummyHandler /* 216 */
|
||||
dc.l _DummyHandler /* 217 */
|
||||
dc.l _DummyHandler /* 218 */
|
||||
dc.l _DummyHandler /* 219 */
|
||||
dc.l _DummyHandler /* 220 */
|
||||
dc.l _DummyHandler /* 221 */
|
||||
dc.l _DummyHandler /* 222 */
|
||||
dc.l _DummyHandler /* 223 */
|
||||
dc.l _DummyHandler /* 224 */
|
||||
dc.l _DummyHandler /* 225 */
|
||||
dc.l _DummyHandler /* 226 */
|
||||
dc.l _DummyHandler /* 227 */
|
||||
dc.l _DummyHandler /* 228 */
|
||||
dc.l _DummyHandler /* 229 */
|
||||
dc.l _DummyHandler /* 230 */
|
||||
dc.l _DummyHandler /* 231 */
|
||||
dc.l _DummyHandler /* 232 */
|
||||
dc.l _DummyHandler /* 233 */
|
||||
dc.l _DummyHandler /* 234 */
|
||||
dc.l _DummyHandler /* 235 */
|
||||
dc.l _DummyHandler /* 236 */
|
||||
dc.l _DummyHandler /* 237 */
|
||||
dc.l _DummyHandler /* 238 */
|
||||
dc.l _DummyHandler /* 239 */
|
||||
dc.l _DummyHandler /* 240 */
|
||||
dc.l _DummyHandler /* 241 */
|
||||
dc.l _DummyHandler /* 242 */
|
||||
dc.l _DummyHandler /* 243 */
|
||||
dc.l _DummyHandler /* 244 */
|
||||
dc.l _DummyHandler /* 245 */
|
||||
dc.l _DummyHandler /* 246 */
|
||||
dc.l _DummyHandler /* 247 */
|
||||
dc.l _DummyHandler /* 248 */
|
||||
dc.l _DummyHandler /* 249 */
|
||||
dc.l _DummyHandler /* 250 */
|
||||
dc.l _DummyHandler /* 251 */
|
||||
dc.l _DummyHandler /* 252 */
|
||||
dc.l _DummyHandler /* 253 */
|
||||
dc.l _DummyHandler /* 254 */
|
||||
dc.l _DummyHandler /* 255 */
|
||||
|
||||
/*
|
||||
* Define weak symbols for four alternate interrupt vectors.
|
||||
* These will be used as the interrupt vectors for the four
|
||||
* secondary contexts.
|
||||
*/
|
||||
.section .data
|
||||
|
||||
.global SYM (_vector_table1)
|
||||
.weak SYM (_vector_table1)
|
||||
.set SYM (_vector_table1), SYM (_vector_table)
|
||||
|
||||
.global SYM (_vector_table2)
|
||||
.weak SYM (_vector_table2)
|
||||
.set SYM (_vector_table2), SYM (_vector_table)
|
||||
|
||||
.global SYM (_vector_table3)
|
||||
.weak SYM (_vector_table3)
|
||||
.set SYM (_vector_table3), SYM (_vector_table)
|
||||
|
||||
.global SYM (_vector_table4)
|
||||
.weak SYM (_vector_table4)
|
||||
.set SYM (_vector_table4), SYM (_vector_table)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2006 CodeSourcery, Inc.
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
__attribute__((interrupt_handler)) void
|
||||
HANDLER()
|
||||
{
|
||||
/* Load the status register into %d0 and the program counter at
|
||||
which the interrupt occured into %d1 for ease of inspection in
|
||||
the debugger. */
|
||||
asm("move.l %sp @(0),%d0\n\t"
|
||||
"move.l %sp @(-4),%d1\n\t"
|
||||
"sleep");
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* fido-hosted.S --
|
||||
*
|
||||
* Copyright (c) 2006 CodeSourcery Inc
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
/* Semihosting function. The debugger intercepts the halt, and
|
||||
determines that it is followed by the sentinel pattern. */
|
||||
|
||||
.globl __hosted
|
||||
__hosted:
|
||||
linkw %fp,#0
|
||||
movel %fp@(8),%d0
|
||||
movel %fp@(12),%d1
|
||||
.align 4
|
||||
nop
|
||||
bkpt #0
|
||||
|
||||
/* This sentinel instruction value must be immediately after
|
||||
the bkpt instruction. The debugger will adjust the pc, so
|
||||
that it is never executed. This instruction is
|
||||
'movec %sp,0'. */
|
||||
.long 0x4e7bf000
|
||||
unlk %fp
|
||||
rts
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#include <stddef.h>
|
||||
|
||||
extern char _end[];
|
||||
static char *curbrk = _end;
|
||||
extern char _heapend; /* End of heap */
|
||||
|
||||
void *
|
||||
sbrk (ptrdiff_t incr)
|
||||
{
|
||||
char *oldbrk = curbrk;
|
||||
if (curbrk + incr > &_heapend)
|
||||
return (void *) -1;
|
||||
curbrk += incr;
|
||||
return oldbrk;
|
||||
}
|
||||
|
|
@ -0,0 +1,704 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @defgroup FIDOmemmap.h Memory map include file for Fido
|
||||
****************************************************************************@{
|
||||
*
|
||||
* @par COPYRIGHT:
|
||||
* COPYRIGHT 2005-2006 INNOVASIC SEMICONDUCTOR, ALL RIGHTS RESERVED.\n
|
||||
* Part of the FIDO REALTIME SUPPORT LIBRARY
|
||||
*
|
||||
* @par Created:
|
||||
* Wed, 1 June 2005 David L. Deis [DD]
|
||||
*
|
||||
* @par CVS-Info:
|
||||
* $Revision$
|
||||
* $Author$
|
||||
* $Date$
|
||||
*
|
||||
* @par Description:
|
||||
* Contains board-specific and onchip memory-mapped register and internal
|
||||
* memory definitions.
|
||||
*/
|
||||
#ifndef FIDOmemmap_h
|
||||
#define FIDOmemmap_h
|
||||
|
||||
/******************************************************************************
|
||||
* Board-specific definitions specify the location and size of all external
|
||||
* memories and the board operating frequency. These values must be specified
|
||||
* based upon the physical board design. These definitions are used by the
|
||||
* software libraries.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* External memory base addresses controlled by chip selects 0,1, and 2.
|
||||
* Specify -1 for any absent memories. The defaults are for the Innovasic
|
||||
* development board.
|
||||
*/
|
||||
#define FLASH_BASE_ADDR 0x00000000
|
||||
#define FLASH_SIZE (8 * 1024 * 1024L)
|
||||
|
||||
#define SDRAM_BASE_ADDR 0x02000000
|
||||
#define SDRAM_SIZE (8 * 1024 * 1024L)
|
||||
|
||||
#define SRAM_BASE_ADDR 0x03000000
|
||||
#define SRAM_SIZE (1 * 1024 * 1024L)
|
||||
|
||||
/**
|
||||
* System clock frequency
|
||||
*/
|
||||
#define FIDO_CLOCK_FREQUENCY (66 * (1000 * 1000))
|
||||
|
||||
/******************************************************************************
|
||||
* Onchip memory-mapped register and internal memory definitions.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Memory offset register value loaded during crt0. This offset applies to
|
||||
* the onchip SRAM, cache, and frame buffer memories and all memory-mapped
|
||||
* registers and cannot conflict with any external memory regions.
|
||||
*/
|
||||
#define FIDO_MEM_OFFSET 0x01000000
|
||||
|
||||
/**
|
||||
* Onchip SRAM
|
||||
*/
|
||||
#define FIDO_SRAM_BASE_ADDR (0x00000000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SRAM_SIZE ((6 * 1024) * sizeof (unsigned long))
|
||||
|
||||
/**
|
||||
* Onchip relocatable cache RAM
|
||||
*/
|
||||
#define FIDO_CACHE_BASE_ADDR (0x00080000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CACHE_BLOCK_SIZE (2 * 1024)
|
||||
#define FIDO_CACHE_BLOCK_MAX 16
|
||||
#define FIDO_CACHE_SIZE (FIDO_CACHE_BLOCK_SIZE * FIDO_CACHE_BLOCK_MAX)
|
||||
#define FIDO_CACHE_BLOCK_ENABLE (1 << 0)
|
||||
|
||||
/**
|
||||
* Memory-mapped registers
|
||||
*/
|
||||
#ifndef __ASSEMBLER__
|
||||
typedef unsigned long volatile FIDO_Register_t;
|
||||
#define FIDO_REGISTER_DEF (FIDO_Register_t*)
|
||||
#else
|
||||
#define FIDO_REGISTER_DEF
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
/* CPU DMA channel 0 and channel 1 registers */
|
||||
#define FIDO_DMACH0_CONTROL FIDO_REGISTER_DEF(0xA0000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH0_COUNT FIDO_REGISTER_DEF(0xA0004 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH0_DEST FIDO_REGISTER_DEF(0xA0008 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH0_SOURCE FIDO_REGISTER_DEF(0xA000C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH1_CONTROL FIDO_REGISTER_DEF(0xA0010 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH1_COUNT FIDO_REGISTER_DEF(0xA0014 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH1_DEST FIDO_REGISTER_DEF(0xA0018 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DMACH1_SOURCE FIDO_REGISTER_DEF(0xA001C + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_DMACH_MAX 2
|
||||
|
||||
/* Timer-Counter unit 0 registers */
|
||||
#define FIDO_TCU00_STATUS FIDO_REGISTER_DEF(0xA0280 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_MODE FIDO_REGISTER_DEF(0xA0284 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_COUNTER FIDO_REGISTER_DEF(0xA0288 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH0_IOMODE FIDO_REGISTER_DEF(0xA0290 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH1_IOMODE FIDO_REGISTER_DEF(0xA0294 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH2_IOMODE FIDO_REGISTER_DEF(0xA0298 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH3_IOMODE FIDO_REGISTER_DEF(0xA029C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH0_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02A0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH1_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02A4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH2_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02A8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH3_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02AC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH0_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02B0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH1_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02B4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH2_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02B8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU00_CH3_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02BC + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Timer-Counter unit 1 registers */
|
||||
#define FIDO_TCU01_STATUS FIDO_REGISTER_DEF(0xA02C0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_MODE FIDO_REGISTER_DEF(0xA02C4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_COUNTER FIDO_REGISTER_DEF(0xA02C8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH0_IOMODE FIDO_REGISTER_DEF(0xA02D0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH1_IOMODE FIDO_REGISTER_DEF(0xA02D4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH2_IOMODE FIDO_REGISTER_DEF(0xA02D8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH3_IOMODE FIDO_REGISTER_DEF(0xA02DC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH0_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02E0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH1_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02E4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH2_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02E8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH3_INPUTCAPTURE FIDO_REGISTER_DEF(0xA02EC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH0_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02F0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH1_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02F4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH2_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02F8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TCU01_CH3_OUTPUTCOMPARE FIDO_REGISTER_DEF(0xA02FC + FIDO_MEM_OFFSET)
|
||||
|
||||
/* SystemTimer interrupt control registers, main ctrl reg, and prescale */
|
||||
#define FIDO_SYSTIMER_INT00CONTROL FIDO_REGISTER_DEF(0xA0300 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SYSTIMER_INT01CONTROL FIDO_REGISTER_DEF(0xA0304 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SYSTIMER_INT02CONTROL FIDO_REGISTER_DEF(0xA0308 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SYSTIMER_INT03CONTROL FIDO_REGISTER_DEF(0xA030C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SYSTIMER_INT04CONTROL FIDO_REGISTER_DEF(0xA0310 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SYSTIMER_CONTROL FIDO_REGISTER_DEF(0xA0314 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SYSTIMER_PRESCALE FIDO_REGISTER_DEF(0xA0318 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Watchdog timer control and reload registers */
|
||||
#define FIDO_WDTTIMER_CONTROL FIDO_REGISTER_DEF(0xA0340 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_WDTTIMER_RELOAD FIDO_REGISTER_DEF(0xA0344 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_WDTTIMER_CONTROL_RELOAD (1 << 0)
|
||||
#define FIDO_WDTTIMER_CONTROL_ENABLE (1 << 1)
|
||||
#define FIDO_WDTTIMER_CONTROL_INTENABLE (1 << 2)
|
||||
|
||||
/* Power on reset register */
|
||||
#define FIDO_POR_REG FIDO_REGISTER_DEF(0xA0360 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Clock mask register, fixed at 0x00003F0F */
|
||||
#define FIDO_CLOCK_MASK_REGISTER FIDO_REGISTER_DEF(0xA0380 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CLOCK_MASK_TCU1 (unsigned long)(1 << 13)
|
||||
#define FIDO_CLOCK_MASK_TCU0 (unsigned long)(1 << 12)
|
||||
#define FIDO_CLOCK_MASK_SYSTIMER (unsigned long)(1 << 11)
|
||||
#define FIDO_CLOCK_MASK_SDRAM (unsigned long)(1 << 10)
|
||||
#define FIDO_CLOCK_MASK_ATOD (unsigned long)(1 << 9)
|
||||
#define FIDO_CLOCK_MASK_PMU (unsigned long)(1 << 8)
|
||||
#define FIDO_CLOCK_MASK_UIC3 (unsigned long)(1 << 3)
|
||||
#define FIDO_CLOCK_MASK_UIC2 (unsigned long)(1 << 2)
|
||||
#define FIDO_CLOCK_MASK_UIC1 (unsigned long)(1 << 1)
|
||||
#define FIDO_CLOCK_MASK_UIC0 (unsigned long)(1 << 0)
|
||||
|
||||
/* Device ID register, fixed at 0x29811000 */
|
||||
#define FIDO_DEVICE_ID_REGISTER FIDO_REGISTER_DEF(0xA0400 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Debug control registers for use by GDB and ROM monitor */
|
||||
#define FIDO_DBG_CTRL FIDO_REGISTER_DEF(0xA0404 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TRCBUF_CTRL FIDO_REGISTER_DEF(0xA0408 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_TRCBUF_BASE FIDO_REGISTER_DEF(0xA040C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK00_BASE FIDO_REGISTER_DEF(0xA0410 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK00_DATA FIDO_REGISTER_DEF(0xA0414 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK00_DATAMASK FIDO_REGISTER_DEF(0xA0418 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK00_CTRL FIDO_REGISTER_DEF(0xA041C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK01_BASE FIDO_REGISTER_DEF(0xA0420 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK01_DATA FIDO_REGISTER_DEF(0xA0424 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK01_DATAMASK FIDO_REGISTER_DEF(0xA0428 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK01_CTRL FIDO_REGISTER_DEF(0xA042C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK02_BASE FIDO_REGISTER_DEF(0xA0430 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK02_DATA FIDO_REGISTER_DEF(0xA0434 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK02_DATAMASK FIDO_REGISTER_DEF(0xA0438 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK02_CTRL FIDO_REGISTER_DEF(0xA043C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK03_BASE FIDO_REGISTER_DEF(0xA0440 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK03_DATA FIDO_REGISTER_DEF(0xA0444 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK03_DATAMASK FIDO_REGISTER_DEF(0xA0448 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK03_CTRL FIDO_REGISTER_DEF(0xA044C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK04_BASE FIDO_REGISTER_DEF(0xA0450 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK04_DATA FIDO_REGISTER_DEF(0xA0454 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK04_DATAMASK FIDO_REGISTER_DEF(0xA0458 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK04_CTRL FIDO_REGISTER_DEF(0xA045C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK05_BASE FIDO_REGISTER_DEF(0xA0460 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK05_DATA FIDO_REGISTER_DEF(0xA0464 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK05_DATAMASK FIDO_REGISTER_DEF(0xA0468 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK05_CTRL FIDO_REGISTER_DEF(0xA046C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK06_BASE FIDO_REGISTER_DEF(0xA0470 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK06_DATA FIDO_REGISTER_DEF(0xA0474 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK06_DATAMASK FIDO_REGISTER_DEF(0xA0478 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK06_CTRL FIDO_REGISTER_DEF(0xA047C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK07_BASE FIDO_REGISTER_DEF(0xA0480 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK07_DATA FIDO_REGISTER_DEF(0xA0484 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK07_DATAMASK FIDO_REGISTER_DEF(0xA0488 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BRK07_CTRL FIDO_REGISTER_DEF(0xA048C + FIDO_MEM_OFFSET)
|
||||
|
||||
/* A/D registers */
|
||||
#define FIDO_A2D0_REG00 FIDO_REGISTER_DEF(0xA0600 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG01 FIDO_REGISTER_DEF(0xA0604 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG02 FIDO_REGISTER_DEF(0xA0608 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG03 FIDO_REGISTER_DEF(0xA060C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG04 FIDO_REGISTER_DEF(0xA0610 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG05 FIDO_REGISTER_DEF(0xA0614 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG06 FIDO_REGISTER_DEF(0xA0618 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG07 FIDO_REGISTER_DEF(0xA061C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG08 FIDO_REGISTER_DEF(0xA0620 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_A2D0_REG09 FIDO_REGISTER_DEF(0xA0624 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Chip select control&timing register pairs */
|
||||
#define FIDO_BIU_CS0_CONTROL FIDO_REGISTER_DEF(0xA0680 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS0_TIMING FIDO_REGISTER_DEF(0xA0684 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS1_CONTROL FIDO_REGISTER_DEF(0xA0688 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS1_TIMING FIDO_REGISTER_DEF(0xA068C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS2_CONTROL FIDO_REGISTER_DEF(0xA0690 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS2_TIMING FIDO_REGISTER_DEF(0xA0694 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS3_CONTROL FIDO_REGISTER_DEF(0xA0698 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS3_TIMING FIDO_REGISTER_DEF(0xA069C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS4_CONTROL FIDO_REGISTER_DEF(0xA06A0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS4_TIMING FIDO_REGISTER_DEF(0xA06A4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS5_CONTROL FIDO_REGISTER_DEF(0xA06A8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS5_TIMING FIDO_REGISTER_DEF(0xA06AC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS6_CONTROL FIDO_REGISTER_DEF(0xA06B0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS6_TIMING FIDO_REGISTER_DEF(0xA06B4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS7_CONTROL FIDO_REGISTER_DEF(0xA06B8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_CS7_TIMING FIDO_REGISTER_DEF(0xA06BC + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_BIU_PRIORITY FIDO_REGISTER_DEF(0xA0700 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_BIU_DEF_TIMING FIDO_REGISTER_DEF(0xA0704 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* SDRAM timing, control, and bank select registers */
|
||||
#define FIDO_SDRAM_TIMING_0 FIDO_REGISTER_DEF(0xA0800 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_TIMING_1 FIDO_REGISTER_DEF(0xA0804 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_CONFIG_0 FIDO_REGISTER_DEF(0xA0808 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_CONFIG_1 FIDO_REGISTER_DEF(0xA080C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_0 FIDO_REGISTER_DEF(0xA0810 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_1 FIDO_REGISTER_DEF(0xA0814 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_2 FIDO_REGISTER_DEF(0xA0818 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_3 FIDO_REGISTER_DEF(0xA081C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_4 FIDO_REGISTER_DEF(0xA0820 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_5 FIDO_REGISTER_DEF(0xA0824 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_6 FIDO_REGISTER_DEF(0xA0828 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SDRAM_EXT_BANK_7 FIDO_REGISTER_DEF(0xA082C + FIDO_MEM_OFFSET)
|
||||
|
||||
/* External interrupt control registers */
|
||||
#define FIDO_INTCONTROLCH0 FIDO_REGISTER_DEF(0xA0900 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH1 FIDO_REGISTER_DEF(0xA0904 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH2 FIDO_REGISTER_DEF(0xA0908 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH3 FIDO_REGISTER_DEF(0xA090C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH4 FIDO_REGISTER_DEF(0xA0910 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH5 FIDO_REGISTER_DEF(0xA0914 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH6 FIDO_REGISTER_DEF(0xA0918 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_INTCONTROLCH7 FIDO_REGISTER_DEF(0xA091C + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Software interrupt control registers */
|
||||
#define FIDO_CTX0_INT_CTRL FIDO_REGISTER_DEF(0xA0980 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_INT_CTRL FIDO_REGISTER_DEF(0xA0984 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_INT_CTRL FIDO_REGISTER_DEF(0xA0988 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_INT_CTRL FIDO_REGISTER_DEF(0xA098C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_INT_CTRL FIDO_REGISTER_DEF(0xA0990 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_PMU_MAC_FILTER_MODE FIDO_REGISTER_DEF(0xA0A00 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMU_FILTER_DATA_HEAD FIDO_REGISTER_DEF(0xA0A04 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMU_FILTER_RDDATA_HEAD FIDO_REGISTER_DEF(0xA0A08 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* PMU channel 0 (tied to UIC 0) registers */
|
||||
#define FIDO_PMUCH0A_CONTROL FIDO_REGISTER_DEF(0xA0A40 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_STATUS FIDO_REGISTER_DEF(0xA0A44 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0A48 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0A4C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0A50 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_XMITFBUFEND FIDO_REGISTER_DEF(0xA0A54 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0A58 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0A5C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0A60 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_RCVFBUFEND FIDO_REGISTER_DEF(0xA0A64 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0A68 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0A6C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_XMITDATA FIDO_REGISTER_DEF(0xA0A70 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0A_RCVDATA FIDO_REGISTER_DEF(0xA0A74 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_PMUCH0B_CONTROL FIDO_REGISTER_DEF(0xA0A80 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_STATUS FIDO_REGISTER_DEF(0xA0A84 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0A88 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0A8C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0A90 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_XMITFBUFEND FIDO_REGISTER_DEF(0xA0A94 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0A98 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0A9C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0AA0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_RCVFBUFEND FIDO_REGISTER_DEF(0xA0AA4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0AA8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0AAC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_XMITDATA FIDO_REGISTER_DEF(0xA0AB0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH0B_RCVDATA FIDO_REGISTER_DEF(0xA0AB4 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* PMU channel 1 (tied to UIC 1) registers */
|
||||
#define FIDO_PMUCH1A_CONTROL FIDO_REGISTER_DEF(0xA0AC0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_STATUS FIDO_REGISTER_DEF(0xA0AC4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0AC8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0ACC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0AD0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_XMITFBUFEND FIDO_REGISTER_DEF(0xA0AD4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0AD8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0ADC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0AE0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_RCVFBUFEND FIDO_REGISTER_DEF(0xA0AE4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0AE8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0AEC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_XMITDATA FIDO_REGISTER_DEF(0xA0AF0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1A_RCVDATA FIDO_REGISTER_DEF(0xA0AF4 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_PMUCH1B_CONTROL FIDO_REGISTER_DEF(0xA0B00 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_STATUS FIDO_REGISTER_DEF(0xA0B04 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0B08 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0B0C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0B10 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_XMITFBUFEND FIDO_REGISTER_DEF(0xA0B14 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0B18 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0B1C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0B20 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_RCVFBUFEND FIDO_REGISTER_DEF(0xA0B24 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0B28 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0B2C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_XMITDATA FIDO_REGISTER_DEF(0xA0B30 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH1B_RCVDATA FIDO_REGISTER_DEF(0xA0B34 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* PMU channel 2 (tied to UIC 2) registers */
|
||||
#define FIDO_PMUCH2A_CONTROL FIDO_REGISTER_DEF(0xA0B40 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_STATUS FIDO_REGISTER_DEF(0xA0B44 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0B48 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0B4C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0B50 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_XMITFBUFEND FIDO_REGISTER_DEF(0xA0B54 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0B58 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0B5C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0B60 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_RCVFBUFEND FIDO_REGISTER_DEF(0xA0B64 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0B68 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0B6C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_XMITDATA FIDO_REGISTER_DEF(0xA0B70 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2A_RCVDATA FIDO_REGISTER_DEF(0xA0B74 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_PMUCH2B_CONTROL FIDO_REGISTER_DEF(0xA0B80 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_STATUS FIDO_REGISTER_DEF(0xA0B84 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0B88 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0B8C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0B90 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_XMITFBUFEND FIDO_REGISTER_DEF(0xA0B94 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0B98 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0B9C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0BA0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_RCVFBUFEND FIDO_REGISTER_DEF(0xA0BA4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0BA8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0BAC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_XMITDATA FIDO_REGISTER_DEF(0xA0BB0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH2B_RCVDATA FIDO_REGISTER_DEF(0xA0BB4 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* PMU channel 3 (tied to UIC 3) registers */
|
||||
#define FIDO_PMUCH3A_CONTROL FIDO_REGISTER_DEF(0xA0BC0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_STATUS FIDO_REGISTER_DEF(0xA0BC4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0BC8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0BCC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0BD0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_XMITFBUFEND FIDO_REGISTER_DEF(0xA0BD4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0BD8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0BDC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0BE0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_RCVFBUFEND FIDO_REGISTER_DEF(0xA0BE4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0BE8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0BEC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_XMITDATA FIDO_REGISTER_DEF(0xA0BF0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3A_RCVDATA FIDO_REGISTER_DEF(0xA0BF4 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_PMUCH3B_CONTROL FIDO_REGISTER_DEF(0xA0C00 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_STATUS FIDO_REGISTER_DEF(0xA0C04 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_PCKXMITSIZE FIDO_REGISTER_DEF(0xA0C08 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_PCKRCVSIZE FIDO_REGISTER_DEF(0xA0C0C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_XMITFBUFSTART FIDO_REGISTER_DEF(0xA0C10 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_XMITFBUFEND FIDO_REGISTER_DEF(0xA0C14 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_XMITFBUFRDPTR FIDO_REGISTER_DEF(0xA0C18 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_XMITFBUFWRPTR FIDO_REGISTER_DEF(0xA0C1C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_RCVFBUFSTART FIDO_REGISTER_DEF(0xA0C20 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_RCVFBUFEND FIDO_REGISTER_DEF(0xA0C24 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_RCVFBUFRDPTR FIDO_REGISTER_DEF(0xA0C28 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_RCVFBUFWRPTR FIDO_REGISTER_DEF(0xA0C2C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_XMITDATA FIDO_REGISTER_DEF(0xA0C30 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_PMUCH3B_RCVDATA FIDO_REGISTER_DEF(0xA0C34 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* 4 PMU/UICs with 2 UIC channels (A and B) each */
|
||||
#define FIDO_PMUCH_MAX 4
|
||||
#define FIDO_UIC_MAX FIDO_PMUCH_MAX
|
||||
#define FIDO_UICCH_MAX 2
|
||||
|
||||
/* FIDO_PMUCHXX_Control register definitions */
|
||||
#define FIDO_PMU_RCV_PACKET_SIZE_EN ( 1 << 18)
|
||||
#define FIDO_PMU_UIC_INT_EN ( 1 << 17)
|
||||
#define FIDO_PMU_PMU_INT_EN ( 1 << 16)
|
||||
#define FIDO_PMU_PRI_SHIFT 13
|
||||
#define FIDO_PMU_PRI_MASK ( 7 << FIDO_PMU_PRI_SHIFT)
|
||||
#define FIDO_PMU_CONTEXT_SHIFT 8
|
||||
#define FIDO_PMU_CONTEXT_MASK ( 7 << FIDO_PMU_CONTEXT_SHIFT)
|
||||
#define FIDO_PMU_CHANNEL_EN ( 1 << 7)
|
||||
#define FIDO_PMU_XMIT_START ( 1 << 6)
|
||||
#define FIDO_PMU_XMIT_IRQ_EN ( 1 << 4)
|
||||
#define FIDO_PMU_RCV_IRQ_EN ( 1 << 3)
|
||||
#define FIDO_PMU_ERROR_IRQ_EN ( 1 << 2)
|
||||
#define FIDO_PMU_MODE_FIFO ( 0 << 0)
|
||||
#define FIDO_PMU_MODE_RANDOM ( 1 << 0)
|
||||
#define FIDO_PMU_MODE_MASK ( 3 << 0)
|
||||
|
||||
/* FIDO_PMUCHXX_Status register definitions */
|
||||
#define FIDO_PMU_RCV_FIFO_FULL ( 1 << 11)
|
||||
#define FIDO_PMU_RCV_FIFO_EMPTY ( 1 << 10)
|
||||
#define FIDO_PMU_XMIT_FIFO_FULL ( 1 << 9)
|
||||
#define FIDO_PMU_XMIT_FIFO_EMPTY ( 1 << 8)
|
||||
#define FIDO_PMU_INTERRUPT ( 1 << 7)
|
||||
#define FIDO_PMU_RCV_BUFF_OVERFLOW ( 1 << 3)
|
||||
#define FIDO_PMU_UIC_ERROR ( 1 << 2)
|
||||
#define FIDO_PMU_RCV_COMPLETE ( 1 << 1)
|
||||
#define FIDO_PMU_XMIT_COMPLETE ( 1 << 0)
|
||||
|
||||
/* PMU interrupt vector definitions */
|
||||
#define FIDO_PMU0_INT_VECTOR 77
|
||||
#define FIDO_PMU1_INT_VECTOR 78
|
||||
#define FIDO_PMU2_INT_VECTOR 79
|
||||
#define FIDO_PMU3_INT_VECTOR 80
|
||||
|
||||
/* Context claim and software interrupt registers */
|
||||
#define FIDO_SWINTACT0 FIDO_REGISTER_DEF(0xA110C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_CLAIM FIDO_REGISTER_DEF(0xA1110 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_PENDING FIDO_REGISTER_DEF(0xA1114 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_PRI_INHER FIDO_REGISTER_DEF(0xA1118 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SWINTACT1 FIDO_REGISTER_DEF(0xA111C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_CLAIM FIDO_REGISTER_DEF(0xA1120 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_PENDING FIDO_REGISTER_DEF(0xA1124 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_PRI_INHER FIDO_REGISTER_DEF(0xA1128 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SWINTACT2 FIDO_REGISTER_DEF(0xA112C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_CLAIM FIDO_REGISTER_DEF(0xA1130 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_PENDING FIDO_REGISTER_DEF(0xA1134 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_PRI_INHER FIDO_REGISTER_DEF(0xA1138 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SWINTACT3 FIDO_REGISTER_DEF(0xA113C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_CLAIM FIDO_REGISTER_DEF(0xA1140 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_PENDING FIDO_REGISTER_DEF(0xA1144 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_PRI_INHER FIDO_REGISTER_DEF(0xA1148 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_SWINTACT4 FIDO_REGISTER_DEF(0xA114C + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context0 data registers and address registers */
|
||||
#define FIDO_CTX0_D0 FIDO_REGISTER_DEF(0xA8100 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D1 FIDO_REGISTER_DEF(0xA8104 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D2 FIDO_REGISTER_DEF(0xA8108 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D3 FIDO_REGISTER_DEF(0xA810C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D4 FIDO_REGISTER_DEF(0xA8110 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D5 FIDO_REGISTER_DEF(0xA8114 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D6 FIDO_REGISTER_DEF(0xA8118 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_D7 FIDO_REGISTER_DEF(0xA811C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A0 FIDO_REGISTER_DEF(0xA8120 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A1 FIDO_REGISTER_DEF(0xA8124 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A2 FIDO_REGISTER_DEF(0xA8128 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A3 FIDO_REGISTER_DEF(0xA812C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A4 FIDO_REGISTER_DEF(0xA8130 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A5 FIDO_REGISTER_DEF(0xA8134 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A6 FIDO_REGISTER_DEF(0xA8138 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A7 FIDO_REGISTER_DEF(0xA813C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_A7S FIDO_REGISTER_DEF(0xA8140 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_PC FIDO_REGISTER_DEF(0xA8144 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_SR FIDO_REGISTER_DEF(0xA8148 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_VBR FIDO_REGISTER_DEF(0xA814C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_SFC FIDO_REGISTER_DEF(0xA8150 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX0_DFC FIDO_REGISTER_DEF(0xA8154 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context1 data registers and address registers */
|
||||
#define FIDO_CTX1_D0 FIDO_REGISTER_DEF(0xA8180 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D1 FIDO_REGISTER_DEF(0xA8184 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D2 FIDO_REGISTER_DEF(0xA8188 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D3 FIDO_REGISTER_DEF(0xA818C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D4 FIDO_REGISTER_DEF(0xA8190 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D5 FIDO_REGISTER_DEF(0xA8194 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D6 FIDO_REGISTER_DEF(0xA8198 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_D7 FIDO_REGISTER_DEF(0xA819C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A0 FIDO_REGISTER_DEF(0xA81A0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A1 FIDO_REGISTER_DEF(0xA81A4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A2 FIDO_REGISTER_DEF(0xA81A8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A3 FIDO_REGISTER_DEF(0xA81AC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A4 FIDO_REGISTER_DEF(0xA81B0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A5 FIDO_REGISTER_DEF(0xA81B4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A6 FIDO_REGISTER_DEF(0xA81B8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A7 FIDO_REGISTER_DEF(0xA81BC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_A7S FIDO_REGISTER_DEF(0xA81C0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_PC FIDO_REGISTER_DEF(0xA81C4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_SR FIDO_REGISTER_DEF(0xA81C8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_VBR FIDO_REGISTER_DEF(0xA81CC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_SFC FIDO_REGISTER_DEF(0xA81D0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_DFC FIDO_REGISTER_DEF(0xA81D4 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context2 data registers and address registers */
|
||||
#define FIDO_CTX2_D0 FIDO_REGISTER_DEF(0xA8200 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D1 FIDO_REGISTER_DEF(0xA8204 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D2 FIDO_REGISTER_DEF(0xA8208 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D3 FIDO_REGISTER_DEF(0xA820C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D4 FIDO_REGISTER_DEF(0xA8210 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D5 FIDO_REGISTER_DEF(0xA8214 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D6 FIDO_REGISTER_DEF(0xA8218 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_D7 FIDO_REGISTER_DEF(0xA812C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A0 FIDO_REGISTER_DEF(0xA8220 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A1 FIDO_REGISTER_DEF(0xA8224 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A2 FIDO_REGISTER_DEF(0xA8228 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A3 FIDO_REGISTER_DEF(0xA822C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A4 FIDO_REGISTER_DEF(0xA8230 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A5 FIDO_REGISTER_DEF(0xA8234 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A6 FIDO_REGISTER_DEF(0xA8238 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A7 FIDO_REGISTER_DEF(0xA823C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_A7S FIDO_REGISTER_DEF(0xA8240 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_PC FIDO_REGISTER_DEF(0xA8244 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_SR FIDO_REGISTER_DEF(0xA8248 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_VBR FIDO_REGISTER_DEF(0xA824C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_SFC FIDO_REGISTER_DEF(0xA8250 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_DFC FIDO_REGISTER_DEF(0xA8254 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context3 data registers and address registers */
|
||||
#define FIDO_CTX3_D0 FIDO_REGISTER_DEF(0xA8280 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D1 FIDO_REGISTER_DEF(0xA8284 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D2 FIDO_REGISTER_DEF(0xA8288 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D3 FIDO_REGISTER_DEF(0xA828C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D4 FIDO_REGISTER_DEF(0xA8290 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D5 FIDO_REGISTER_DEF(0xA8294 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D6 FIDO_REGISTER_DEF(0xA8298 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_D7 FIDO_REGISTER_DEF(0xA829C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A0 FIDO_REGISTER_DEF(0xA82A0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A1 FIDO_REGISTER_DEF(0xA82A4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A2 FIDO_REGISTER_DEF(0xA82A8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A3 FIDO_REGISTER_DEF(0xA82AC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A4 FIDO_REGISTER_DEF(0xA82B0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A5 FIDO_REGISTER_DEF(0xA82B4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A6 FIDO_REGISTER_DEF(0xA82B8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A7 FIDO_REGISTER_DEF(0xA82BC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_A7S FIDO_REGISTER_DEF(0xA82C0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_PC FIDO_REGISTER_DEF(0xA82C4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_SR FIDO_REGISTER_DEF(0xA82C8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_VBR FIDO_REGISTER_DEF(0xA82CC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_SFC FIDO_REGISTER_DEF(0xA82D0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_DFC FIDO_REGISTER_DEF(0xA82D4 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context4 data registers and address registers */
|
||||
#define FIDO_CTX4_D0 FIDO_REGISTER_DEF(0xA8300 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D1 FIDO_REGISTER_DEF(0xA8304 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D2 FIDO_REGISTER_DEF(0xA8308 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D3 FIDO_REGISTER_DEF(0xA830C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D4 FIDO_REGISTER_DEF(0xA8310 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D5 FIDO_REGISTER_DEF(0xA8314 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D6 FIDO_REGISTER_DEF(0xA8318 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_D7 FIDO_REGISTER_DEF(0xA831C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A0 FIDO_REGISTER_DEF(0xA8320 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A1 FIDO_REGISTER_DEF(0xA8324 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A2 FIDO_REGISTER_DEF(0xA8328 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A3 FIDO_REGISTER_DEF(0xA832C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A4 FIDO_REGISTER_DEF(0xA8330 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A5 FIDO_REGISTER_DEF(0xA8334 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A6 FIDO_REGISTER_DEF(0xA8338 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A7 FIDO_REGISTER_DEF(0xA833C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_A7S FIDO_REGISTER_DEF(0xA8340 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_PC FIDO_REGISTER_DEF(0xA8344 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_SR FIDO_REGISTER_DEF(0xA8348 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_VBR FIDO_REGISTER_DEF(0xA834C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_SFC FIDO_REGISTER_DEF(0xA8350 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_DFC FIDO_REGISTER_DEF(0xA8354 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_CTX_MAX 5
|
||||
|
||||
/* MPU Block control register */
|
||||
#define FIDO_MPU_BLK00CTRL FIDO_REGISTER_DEF(0xAA000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK01CTRL FIDO_REGISTER_DEF(0xAA004 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK02CTRL FIDO_REGISTER_DEF(0xAA008 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK03CTRL FIDO_REGISTER_DEF(0xAA00C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK04CTRL FIDO_REGISTER_DEF(0xAA010 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK05CTRL FIDO_REGISTER_DEF(0xAA014 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK06CTRL FIDO_REGISTER_DEF(0xAA018 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK07CTRL FIDO_REGISTER_DEF(0xAA01C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK08CTRL FIDO_REGISTER_DEF(0xAA020 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK09CTRL FIDO_REGISTER_DEF(0xAA024 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK10CTRL FIDO_REGISTER_DEF(0xAA028 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK11CTRL FIDO_REGISTER_DEF(0xAA02C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK12CTRL FIDO_REGISTER_DEF(0xAA030 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK13CTRL FIDO_REGISTER_DEF(0xAA034 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK14CTRL FIDO_REGISTER_DEF(0xAA038 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK15CTRL FIDO_REGISTER_DEF(0xAA03C + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_MPU_BLOCK_MAX 16
|
||||
#define FIDO_MPU_BLOCK_BASE_ALIGN 64
|
||||
|
||||
/* MPU Block attribute register */
|
||||
#define FIDO_MPU_BLK00ATTRIB FIDO_REGISTER_DEF(0xAA080 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK01ATTRIB FIDO_REGISTER_DEF(0xAA084 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK02ATTRIB FIDO_REGISTER_DEF(0xAA088 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK03ATTRIB FIDO_REGISTER_DEF(0xAA08C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK04ATTRIB FIDO_REGISTER_DEF(0xAA090 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK05ATTRIB FIDO_REGISTER_DEF(0xAA094 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK06ATTRIB FIDO_REGISTER_DEF(0xAA098 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK07ATTRIB FIDO_REGISTER_DEF(0xAA09C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK08ATTRIB FIDO_REGISTER_DEF(0xAA0A0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK09ATTRIB FIDO_REGISTER_DEF(0xAA0A4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK10ATTRIB FIDO_REGISTER_DEF(0xAA0A8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK11ATTRIB FIDO_REGISTER_DEF(0xAA0AC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK12ATTRIB FIDO_REGISTER_DEF(0xAA0B0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK13ATTRIB FIDO_REGISTER_DEF(0xAA0B4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK14ATTRIB FIDO_REGISTER_DEF(0xAA0B8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_MPU_BLK15ATTRIB FIDO_REGISTER_DEF(0xAA0BC + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_MPU_ATTRIB_SIZE_SHIFT 2
|
||||
#define FIDO_MPU_ATTRIB_ENABLE (1 << 0)
|
||||
#define FIDO_MPU_ATTRIB_READONLY (1 << 1)
|
||||
|
||||
/* MPU allocation registers */
|
||||
#define FIDO_CTX0_MPUALLOCATION FIDO_REGISTER_DEF(0xAA100 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_MPUALLOCATION FIDO_REGISTER_DEF(0xAA104 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_MPUALLOCATION FIDO_REGISTER_DEF(0xAA108 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_MPUALLOCATION FIDO_REGISTER_DEF(0xAA10C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_MPUALLOCATION FIDO_REGISTER_DEF(0xAA110 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* DCACHE relocatable registers */
|
||||
#define FIDO_DCACHE_RELOCATBLK00 FIDO_REGISTER_DEF(0xAA180 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK01 FIDO_REGISTER_DEF(0xAA184 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK02 FIDO_REGISTER_DEF(0xAA188 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK03 FIDO_REGISTER_DEF(0xAA18C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK04 FIDO_REGISTER_DEF(0xAA190 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK05 FIDO_REGISTER_DEF(0xAA194 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK06 FIDO_REGISTER_DEF(0xAA198 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK07 FIDO_REGISTER_DEF(0xAA19C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK08 FIDO_REGISTER_DEF(0xAA1A0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK09 FIDO_REGISTER_DEF(0xAA1A4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK10 FIDO_REGISTER_DEF(0xAA1A8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK11 FIDO_REGISTER_DEF(0xAA1AC + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK12 FIDO_REGISTER_DEF(0xAA1B0 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK13 FIDO_REGISTER_DEF(0xAA1B4 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK14 FIDO_REGISTER_DEF(0xAA1B8 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_DCACHE_RELOCATBLK15 FIDO_REGISTER_DEF(0xAA1BC + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context control registers */
|
||||
#define FIDO_CTX0_CONTROL FIDO_REGISTER_DEF(0xAA400 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_CONTROL FIDO_REGISTER_DEF(0xAA404 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_CONTROL FIDO_REGISTER_DEF(0xAA408 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_CONTROL FIDO_REGISTER_DEF(0xAA40C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_CONTROL FIDO_REGISTER_DEF(0xAA410 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_CTX_CONTROL_STATE_MASK ( 3 << 0)
|
||||
#define FIDO_CTX_CONTROL_STATE_HALTED ( 0 << 0)
|
||||
#define FIDO_CTX_CONTROL_STATE_NOTREADY ( 1 << 0)
|
||||
#define FIDO_CTX_CONTROL_STATE_READY ( 2 << 0)
|
||||
|
||||
#define FIDO_CTX_CONTROL_PRIORITY_MASK 7
|
||||
#define FIDO_CTX_CONTROL_PRIORITY_SHIFT 8
|
||||
|
||||
#define FIDO_CTX_CONTROL_MODE_MASK ( 3 << 13)
|
||||
#define FIDO_CTX_CONTROL_MODE_STANDARD ( 0 << 13)
|
||||
#define FIDO_CTX_CONTROL_MODE_FAST ( 1 << 13)
|
||||
#define FIDO_CTX_CONTROL_MODE_FAST_ST ( 3 << 13)
|
||||
|
||||
#define FIDO_CTX0_MAXTIME FIDO_REGISTER_DEF(0xAA480 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_MAXTIME FIDO_REGISTER_DEF(0xAA484 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_MAXTIME FIDO_REGISTER_DEF(0xAA488 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_MAXTIME FIDO_REGISTER_DEF(0xAA48C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_MAXTIME FIDO_REGISTER_DEF(0xAA490 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Context timer registers */
|
||||
#define FIDO_CTX0_TIME FIDO_REGISTER_DEF(0xAA500 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX1_TIME FIDO_REGISTER_DEF(0xAA504 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX2_TIME FIDO_REGISTER_DEF(0xAA508 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX3_TIME FIDO_REGISTER_DEF(0xAA50C + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX4_TIME FIDO_REGISTER_DEF(0xAA510 + FIDO_MEM_OFFSET)
|
||||
|
||||
#define FIDO_CTXN_TIMECLR FIDO_REGISTER_DEF(0xAA580 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX_IDLETIME FIDO_REGISTER_DEF(0xAA584 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTXN_TIMEEN FIDO_REGISTER_DEF(0xAA588 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_CTX_FAULTID FIDO_REGISTER_DEF(0xAA600 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* Current context register, contains id of currently executing context */
|
||||
#define FIDO_CURRENT_CONTEXT_REGISTER FIDO_REGISTER_DEF(0xAA604 + FIDO_MEM_OFFSET)
|
||||
|
||||
/* UIC Frame Buffer transmit and receive memory */
|
||||
#define FIDO_FB_XMIT_BASE_ADDR (0xB0000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_FB_XMIT_SIZE ((1 * 1024) * sizeof (unsigned long))
|
||||
|
||||
#define FIDO_FB_RCV_BASE_ADDR (0xB4000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_FB_RCV_SIZE ((2 * 1024) * sizeof (unsigned long))
|
||||
|
||||
/* UIC register file base addresses */
|
||||
#define FIDO_UIC0_BASE (0x00B8000 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_UIC1_BASE (0x00B8200 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_UIC2_BASE (0x00B8400 + FIDO_MEM_OFFSET)
|
||||
#define FIDO_UIC3_BASE (0x00B8600 + FIDO_MEM_OFFSET)
|
||||
|
||||
#endif /* FIDOmemmap_h */
|
||||
|
||||
///@}
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
SRAM_ORIGIN=0x03000000
|
||||
SRAM_LENGTH=0x00100000
|
||||
|
||||
# HEAPEND must be in the same memory region as DATA. STACK should be
|
||||
# above HEAPEND, also in the same region, for configurations which
|
||||
# need __stack.
|
||||
|
||||
case $MODE in
|
||||
rom)
|
||||
CRT0=rom
|
||||
TEXT=rom
|
||||
DATA=sram
|
||||
DATALOAD="rom"
|
||||
STACK=0x030ffffc
|
||||
HEAPEND=0x03080000
|
||||
;;
|
||||
sram)
|
||||
CRT0=ram
|
||||
TEXT=sram
|
||||
DATA=sdram
|
||||
STACK=0x021ffffc
|
||||
HEAPEND=0x02180000
|
||||
# Leave the rest of SDRAM for manual use.
|
||||
;;
|
||||
sdram)
|
||||
CRT0=ram
|
||||
TEXT=sdram
|
||||
DATA=sdram
|
||||
STACK=0x021ffffc
|
||||
HEAPEND=0x02180000
|
||||
# Leave the rest of SDRAM for manual use.
|
||||
;;
|
||||
redboot)
|
||||
CRT0=redboot
|
||||
# We need to avoid the area used by RedBoot
|
||||
SRAM_ORIGIN=0x3080000
|
||||
SRAM_LENGTH=0x80000
|
||||
# Put code for RedBoot apps in SRAM, since the fido1100 has
|
||||
# trouble running code from SDRAM.
|
||||
TEXT=sram
|
||||
DATA=sdram
|
||||
STACK=0
|
||||
HEAPEND=0x027f0000
|
||||
;;
|
||||
*)
|
||||
ERROR
|
||||
;;
|
||||
esac
|
||||
|
||||
cat <<EOF
|
||||
/*
|
||||
* Setup the memory map of the Innovasic SBC
|
||||
* stack grows down from high memory.
|
||||
*
|
||||
* The memory map for the ROM model looks like this:
|
||||
*
|
||||
* +--------------------+ <-address 0 in Flash
|
||||
* | .vector_table |
|
||||
* +--------------------+ <- low memory
|
||||
* | .text |
|
||||
* | _etext |
|
||||
* | ctor list | the ctor and dtor lists are for
|
||||
* | dtor list | C++ support
|
||||
* +--------------------+
|
||||
* | DCACHE_CODE | code to be loaded into DCACHE
|
||||
* | _dcache_start |
|
||||
* | _dcache_end |
|
||||
* +--------------------+
|
||||
* | .data | initialized data goes here
|
||||
* +--------------------+
|
||||
* . .
|
||||
* . .
|
||||
* . .
|
||||
* +--------------------+ <- The beginning of the SRAM area
|
||||
* | .data | a wriable copy of data goes here.
|
||||
* | _edata |
|
||||
* +--------------------+
|
||||
* | .bss |
|
||||
* | __bss_start | start of bss, cleared by crt0
|
||||
* | _end | start of heap, used by sbrk()
|
||||
* | _heapend | End of heap, used by sbrk()
|
||||
* +--------------------+
|
||||
* . .
|
||||
* . .
|
||||
* . .
|
||||
* | __stack | top of stack
|
||||
* +--------------------+
|
||||
*
|
||||
*
|
||||
* The memory map for the RAM model looks like this:
|
||||
*
|
||||
* +--------------------+ <- The beginning of the SRAM or SDRAM area.
|
||||
* | .vector_table |
|
||||
* +--------------------+ <- low memory
|
||||
* | .text |
|
||||
* | _etext |
|
||||
* | ctor list | the ctor and dtor lists are for
|
||||
* | dtor list | C++ support
|
||||
* +--------------------+
|
||||
* | DCACHE_CODE | code to be loaded into DCACHE
|
||||
* | _dcache_start |
|
||||
* | _dcache_end |
|
||||
* +--------------------+
|
||||
* | .data | initialized data goes here
|
||||
* | _edata |
|
||||
* +--------------------+
|
||||
* | .bss |
|
||||
* | __bss_start | start of bss, cleared by crt0
|
||||
* | _end | start of heap, used by sbrk()
|
||||
* | _heapend | End of heap, used by sbrk()
|
||||
* +--------------------+
|
||||
* . .
|
||||
* . .
|
||||
* . .
|
||||
* | __stack | top of stack
|
||||
* +--------------------+
|
||||
*/
|
||||
|
||||
STARTUP(fido-${CRT0}-crt0.o)
|
||||
OUTPUT_ARCH(m68k)
|
||||
ENTRY(_start);
|
||||
GROUP(-l${IO} -lfido -lc -lgcc)
|
||||
|
||||
MEMORY {
|
||||
/* Flash ROM. */
|
||||
rom (rx) : ORIGIN = 0x0000000, LENGTH = 0x800000
|
||||
/* Internal SRAM. */
|
||||
int_ram (rwx) : ORIGIN = 0x1000000, LENGTH = 0x6000
|
||||
/* External SDRAM. */
|
||||
sdram (rwx) : ORIGIN = 0x2000000, LENGTH = 0x800000
|
||||
/* External SRAM. */
|
||||
sram (rwx) : ORIGIN = ${SRAM_ORIGIN}, LENGTH = ${SRAM_LENGTH}
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
/* The interrupt vector is placed at the beginning of ${TEXT},
|
||||
as required at reset. */
|
||||
.vector_table : {
|
||||
*(.vector_table)
|
||||
} > ${TEXT}
|
||||
|
||||
/* Text section. */
|
||||
.text :
|
||||
{
|
||||
*(.text .gnu.linkonce.t.*)
|
||||
. = ALIGN(0x4);
|
||||
__CTOR_LIST__ = .;
|
||||
___CTOR_LIST__ = .;
|
||||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
|
||||
*(.ctors)
|
||||
LONG(0)
|
||||
__CTOR_END__ = .;
|
||||
__DTOR_LIST__ = .;
|
||||
___DTOR_LIST__ = .;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
*(.dtors)
|
||||
LONG(0)
|
||||
__DTOR_END__ = .;
|
||||
*(.rodata* .gnu.linkonce.r.*)
|
||||
*(.gcc_except_table)
|
||||
*(.eh_frame)
|
||||
|
||||
. = ALIGN(0x2);
|
||||
__INIT_SECTION__ = . ;
|
||||
LONG (0x4e560000) /* linkw %fp,#0 */
|
||||
*(.init)
|
||||
SHORT (0x4e5e) /* unlk %fp */
|
||||
SHORT (0x4e75) /* rts */
|
||||
|
||||
__FINI_SECTION__ = . ;
|
||||
LONG (0x4e560000) /* linkw %fp,#0 */
|
||||
*(.fini)
|
||||
SHORT (0x4e5e) /* unlk %fp */
|
||||
SHORT (0x4e75) /* rts */
|
||||
. = ALIGN(0x800); /* align to a 2K dcache boundary */
|
||||
_dcache_start = .;
|
||||
*(DCACHE_CODE)
|
||||
_dcache_end = .;
|
||||
_etext = .;
|
||||
*(.lit)
|
||||
. = ALIGN(0x4);
|
||||
__start_romdata = .;
|
||||
} > ${TEXT}
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
_data = .;
|
||||
KEEP (*(.jcr));
|
||||
*(.shdata);
|
||||
*(.data .gnu.linkonce.d.*);
|
||||
_edata_cksum = .;
|
||||
*(checksum);
|
||||
_edata = .;
|
||||
} > ${DATA} ${DATALOAD:+AT>} ${DATALOAD}
|
||||
|
||||
/* Zero-initialized data. */
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
__bss_start = . ;
|
||||
*(.shbss)
|
||||
*(.bss .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_end = ALIGN (0x8);
|
||||
__end = _end;
|
||||
} > ${DATA}
|
||||
|
||||
/* Specially designated data is placed in the internal RAM. */
|
||||
fast_memory :
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
__fast_start = .;
|
||||
*(FAST_RAM)
|
||||
__fast_stop = .;
|
||||
} > int_ram
|
||||
}
|
||||
|
||||
PROVIDE (__stack = ${STACK});
|
||||
|
||||
PROVIDE (_heapend = ${HEAPEND});
|
||||
EOF
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* fido profiling support.
|
||||
*
|
||||
* Copyright (c) 2006 CodeSourcery Inc
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
#ifndef FIDO_PROFILING_H
|
||||
#define FIDO_PROFILING_H
|
||||
|
||||
extern int monconfig (unsigned char *buffer, unsigned buffer_size);
|
||||
extern int moncontrol (int);
|
||||
extern void _mcleanup (void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue