diff --git a/libgloss/ChangeLog b/libgloss/ChangeLog
index 794bd0628..567778991 100644
--- a/libgloss/ChangeLog
+++ b/libgloss/ChangeLog
@@ -1,3 +1,9 @@
+2006-11-24  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* mips/crt0.S (_start): Use all available float registers. Don't touch
+	SR_PE on post-mips2 CPUs, it means soft reset there.
+
 2006-11-22  Luca Barbato  <lu_zero@gentoo.org>
 
 	* spu/syscalls.c: Include spu_intrinsics.h to provide vector keyword.
diff --git a/libgloss/mips/crt0.S b/libgloss/mips/crt0.S
index 8810afa6c..651b2a782 100644
--- a/libgloss/mips/crt0.S
+++ b/libgloss/mips/crt0.S
@@ -65,11 +65,21 @@ _start:
 	nop
 	move	s0,$31
 #endif
-#if !defined(__mips64) || (__mips_fpr==32)
-#define STATUS_MASK (SR_CU1|SR_PE)
+#if __mips<3
+#  define STATUS_MASK (SR_CU1|SR_PE)
 #else
-# For mips3 or mips4, turn on 64-bit addressing and additional float regs
-#define STATUS_MASK (SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX)
+/* Post-mips2 has no SR_PE bit.  */
+#  ifdef __mips64
+/* Turn on 64-bit addressing and additional float regs.  */
+#    define STATUS_MASK (SR_CU1|SR_FR|SR_KX|SR_SX|SR_UX)
+#  else
+#    ifdef __mips_fpr=32
+#      define STATUS_MASK (SR_CU1)
+#    else
+/* Turn on additional float regs.  */
+#      define STATUS_MASK (SR_CU1|SR_FR)
+#    endif
+#  endif
 #endif
 	li	v0, STATUS_MASK
 	mtc0	v0, C0_SR