2013-10-14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* arm/cpu-init/rdimon-aem.S: Disable for M class cores. * arm/crt0.S: Don't call _rdimon_hw_init_hook for non-A class cores. * arm/cpu-init/Makefile.in (CPU_INIT_OBJS): Use CFLAGS.
This commit is contained in:
Richard Earnshaw
parent
40ec00004b
commit
639951dda7
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@ -1,3 +1,9 @@
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2013-10-14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* arm/cpu-init/rdimon-aem.S: Disable for M class cores.
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* arm/crt0.S: Don't call _rdimon_hw_init_hook for non-A class cores.
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* arm/cpu-init/Makefile.in (CPU_INIT_OBJS): Use CFLAGS.
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2013-09-30 Steve Ellcey <sellcey@mips.com>
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* mips/Makefile.in (install): Add mkdir, fix install command.
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@ -60,7 +60,7 @@ test:
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# Static pattern rule for assembling cpu init files to object files.
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${CPU_INIT_OBJS}: %.o: %.S
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$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) -DARM_RDI_MONITOR -o $@ -c $<
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$(CC) $(CFLAGS_FOR_TARGET) $(CFLAGS) $(INCLUDES) -DARM_RDI_MONITOR -o $@ -c $<
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clean mostlyclean:
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rm -f a.out core *.i *.o *-test *.srec *.dis *.x
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@ -37,18 +37,22 @@
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It does not change processor state from the startup privilege and security
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level.
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This has only been tested to work in ARM state.
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By default it assumes exception vectors are located from address 0.
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However, if this is not true they can be moved by defining the
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_rdimon_vector_base symbol. For example if you have HIVECS enabled you
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may pass --defsym _rdimon_vector_base=0xffff0000 on the linker command
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line. */
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/* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A
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has been defined since 4.2 onwards, which is when v7-a support was added
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and hence 'A' profile support was added in the compiler. Allow for this
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file to be built with older compilers. */
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#if defined(__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A')
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.syntax unified
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.arch armv7-a
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#if defined(__thumb__)
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.thumb
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#endif
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.arm
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@ CPU Initialisation
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.globl _rdimon_hw_init_hook
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@ -81,6 +85,7 @@ spin:
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@ For Cortex-A15 and Cortex-A7 only:
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@ Write zero into the ACTLR to turn everything on.
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itt eq
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moveq r4, #0
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mcreq 15, 0, r4, c1, c0, 1
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isb
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@ -88,6 +93,7 @@ spin:
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@ For Cortex-A15 and Cortex-A7 only:
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@ Set ACTLR:SMP bit before enabling the caches and MMU,
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@ or performing any cache and TLB maintenance operations.
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ittt eq
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mrceq 15, 0, r4, c1, c0, 1 @ Read ACTLR
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orreq r4, r4, #(1<<6) @ Enable ACTLR:SMP
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mcreq 15, 0, r4, c1, c0, 1 @ Write ACTLR
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@ -245,7 +251,7 @@ vector_common_adr:
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.word vector_common_2 @ Common handling code
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@ Vector stack
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.align 3 @ Align to 8 byte boundary boundary to
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.p2align 3 @ Align to 8 byte boundary boundary to
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@ keep ABI compatibility
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.fill 32, 4, 0 @ 32-entry stack is enough for vector
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@ handlers.
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@ -365,7 +371,8 @@ register_names:
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.asciz "r12 "
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.asciz "r14 "
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.align
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.p2align 3
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@ Enable the caches
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__enable_caches:
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@ -386,7 +393,7 @@ __enable_caches:
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cmp r0, #0
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it ne
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orrne r4, r4, #4
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mcr 15, 0, r4, cr1, cr0, 0 @ Eanble D-Cache
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mcr 15, 0, r4, cr1, cr0, 0 @ Enable D-Cache
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bx r5 @ Return
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__reset_caches:
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@ -414,7 +421,9 @@ __reset_caches:
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orrne r1, r1, #0x1000 @ Enable I-Cache now -
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@ We actually only do this if we have a
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@ Harvard style cache.
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it eq
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bleq init_cpu_client_enable_dcache
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itt eq
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cmpeq r0, #0
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beq Finished1
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@ -483,6 +492,7 @@ is_a15_a7:
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cmp r8, r9
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movw r9, #0xc070
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movt r9, #0x410f
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it ne
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cmpne r8, r9
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bx lr
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@ -516,3 +526,5 @@ is_a15_a7:
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.p2align 14
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page_tables:
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PT7(0x1c0e)
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#endif //#if defined(__ARM_ARCH_7A__) || __ARM_ARCH_PROFILE == 'A'
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@ -77,11 +77,18 @@
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.fnstart
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#endif
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/* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A
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has been defined since 4.2 onwards, which is when v7-a support was added
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and hence 'A' profile support was added in the compiler. Allow for this
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file to be built with older compilers. We only call this for A profile
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cores. */
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#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A')
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/* The init hook does not use the stack and is called before the stack has been set up. */
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#ifdef ARM_RDI_MONITOR
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bl _rdimon_hw_init_hook
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.weak FUNCTION (_rdimon_hw_init_hook)
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#endif
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#endif
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/* Start by setting up a stack */
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#ifdef ARM_RDP_MONITOR
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