From 753a03bf8e01cd738885a11922618ef6401a9f92 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Mon, 2 Mar 2009 10:33:07 +0000 Subject: [PATCH] Add support for Score7 architecture. --- include/elf/ChangeLog | 5 + include/elf/common.h | 3 + include/elf/score.h | 13 +- include/opcode/ChangeLog | 6 + include/opcode/score-datadep.h | 227 +----------------------- include/opcode/score-inst.h | 313 +++------------------------------ 6 files changed, 50 insertions(+), 517 deletions(-) diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index e882628b2..606a170f6 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,8 @@ +2009-03-02 Qinwei + + * score.h (RELOC_NUMBER): Add R_SCORE_IMM32. + * common.h (EM_SCORE_OLD): Define. + 2009-02-23 H.J. Lu * common.h (STB_LOPROC): Replace Application-specific with diff --git a/include/elf/common.h b/include/elf/common.h index 557c650ad..3ba44d946 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -334,6 +334,9 @@ #define EM_CYGNUS_MEP 0xF00D /* Toshiba MeP */ +/* Old Sunplus S+core7 backend magic number. Written in the absence of an ABI. */ +#define EM_SCORE_OLD 95 + /* See the above comment before you add a new EM_* value here. */ /* Values for e_version. */ diff --git a/include/elf/score.h b/include/elf/score.h index 72ada0548..8d9c026bb 100644 --- a/include/elf/score.h +++ b/include/elf/score.h @@ -1,6 +1,7 @@ /* Score ELF support for BFD. - Copyright 2006, 2008 Free Software Foundation, Inc. + Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. Contributed by + Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) Pei-Lin Tsai (pltsai@sunplus.com) @@ -8,7 +9,7 @@ This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or + the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, @@ -35,6 +36,10 @@ #define GP_DISP_LABEL "_gp_disp" /* Processor specific flags for the ELF header e_flags field: */ +#define EF_SCORE_MACH 0xffff0000 +#define EF_OMIT_PIC_FIXDD 0x0fff0000 +#define E_SCORE_MACH_SCORE3 0x00030000 +#define E_SCORE_MACH_SCORE7 0x00070000 /* File contains position independent code. */ #define EF_SCORE_PIC 0x80000000 @@ -101,7 +106,7 @@ START_RELOC_NUMBERS (elf_score_reloc_type) RELOC_NUMBER (R_SCORE_NONE, 0) RELOC_NUMBER (R_SCORE_HI16, 1) RELOC_NUMBER (R_SCORE_LO16, 2) - RELOC_NUMBER (R_SCORE_DUMMY1, 3) + RELOC_NUMBER (R_SCORE_BCMP, 3) RELOC_NUMBER (R_SCORE_24, 4) RELOC_NUMBER (R_SCORE_PC19, 5) RELOC_NUMBER (R_SCORE16_11, 6) @@ -118,6 +123,8 @@ START_RELOC_NUMBERS (elf_score_reloc_type) RELOC_NUMBER (R_SCORE_GPREL32, 17) RELOC_NUMBER (R_SCORE_REL32, 18) RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19) + RELOC_NUMBER (R_SCORE_IMM30, 20) + RELOC_NUMBER (R_SCORE_IMM32, 21) END_RELOC_NUMBERS (R_SCORE_max) #endif /* _ELF_SCORE_H */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index f7018b845..2a03208a9 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,9 @@ +2009-03-02 Qinwei + + * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 + and _IMM11 for mbitclr and mbitset. + * score-datadep.h: Update dependency information. + 2009-02-26 Peter Bergner * ppc.h (PPC_OPCODE_POWER7): New. diff --git a/include/opcode/score-datadep.h b/include/opcode/score-datadep.h index 8ef35adc8..33c05c060 100644 --- a/include/opcode/score-datadep.h +++ b/include/opcode/score-datadep.h @@ -1,6 +1,7 @@ /* score-datadep.h -- Score Instructions data dependency table - Copyright 2006 Free Software Foundation, Inc. + Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. Contributed by: + Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) Pei-Lin Tsai (pltsai@sunplus.com) @@ -8,7 +9,7 @@ GAS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) + the Free Software Foundation; either version 3, or (at your option) any later version. GAS is distributed in the hope that it will be useful, @@ -28,20 +29,7 @@ enum insn_type_for_dependency { - D_pce, - D_cond_br, - D_cond_mv, - D_cached, - D_cachei, - D_ldst, - D_ldcombine, D_mtcr, - D_mfcr, - D_mfsr, - D_mftlb, - D_mtptlb, - D_mtrtlb, - D_stlb, D_all_insn }; @@ -58,225 +46,20 @@ struct data_dependency enum insn_type_for_dependency cur_insn_type; char cur_reg[6]; int bubblenum_7; - int bubblenum_5; + int bubblenum_3; int warn_or_error; /* warning - 0; error - 1 */ }; static const struct insn_to_dependency insn_to_dependency_table[] = { - /* pce instruction. */ - {"pce", D_pce}, - /* conditional branch instruction. */ - {"bcs", D_cond_br}, - {"bcc", D_cond_br}, - {"bgtu", D_cond_br}, - {"bleu", D_cond_br}, - {"beq", D_cond_br}, - {"bne", D_cond_br}, - {"bgt", D_cond_br}, - {"ble", D_cond_br}, - {"bge", D_cond_br}, - {"blt", D_cond_br}, - {"bmi", D_cond_br}, - {"bpl", D_cond_br}, - {"bvs", D_cond_br}, - {"bvc", D_cond_br}, - {"bcsl", D_cond_br}, - {"bccl", D_cond_br}, - {"bgtul", D_cond_br}, - {"bleul", D_cond_br}, - {"beql", D_cond_br}, - {"bnel", D_cond_br}, - {"bgtl", D_cond_br}, - {"blel", D_cond_br}, - {"bgel", D_cond_br}, - {"bltl", D_cond_br}, - {"bmil", D_cond_br}, - {"bpll", D_cond_br}, - {"bvsl", D_cond_br}, - {"bvcl", D_cond_br}, - {"bcs!", D_cond_br}, - {"bcc!", D_cond_br}, - {"bgtu!", D_cond_br}, - {"bleu!", D_cond_br}, - {"beq!", D_cond_br}, - {"bne!", D_cond_br}, - {"bgt!", D_cond_br}, - {"ble!", D_cond_br}, - {"bge!", D_cond_br}, - {"blt!", D_cond_br}, - {"bmi!", D_cond_br}, - {"bpl!", D_cond_br}, - {"bvs!", D_cond_br}, - {"bvc!", D_cond_br}, - {"brcs", D_cond_br}, - {"brcc", D_cond_br}, - {"brgtu", D_cond_br}, - {"brleu", D_cond_br}, - {"breq", D_cond_br}, - {"brne", D_cond_br}, - {"brgt", D_cond_br}, - {"brle", D_cond_br}, - {"brge", D_cond_br}, - {"brlt", D_cond_br}, - {"brmi", D_cond_br}, - {"brpl", D_cond_br}, - {"brvs", D_cond_br}, - {"brvc", D_cond_br}, - {"brcsl", D_cond_br}, - {"brccl", D_cond_br}, - {"brgtul", D_cond_br}, - {"brleul", D_cond_br}, - {"breql", D_cond_br}, - {"brnel", D_cond_br}, - {"brgtl", D_cond_br}, - {"brlel", D_cond_br}, - {"brgel", D_cond_br}, - {"brltl", D_cond_br}, - {"brmil", D_cond_br}, - {"brpll", D_cond_br}, - {"brvsl", D_cond_br}, - {"brvcl", D_cond_br}, - {"brcs!", D_cond_br}, - {"brcc!", D_cond_br}, - {"brgtu!", D_cond_br}, - {"brleu!", D_cond_br}, - {"breq!", D_cond_br}, - {"brne!", D_cond_br}, - {"brgt!", D_cond_br}, - {"brle!", D_cond_br}, - {"brge!", D_cond_br}, - {"brlt!", D_cond_br}, - {"brmi!", D_cond_br}, - {"brpl!", D_cond_br}, - {"brvs!", D_cond_br}, - {"brvc!", D_cond_br}, - {"brcsl!", D_cond_br}, - {"brccl!", D_cond_br}, - {"brgtul!", D_cond_br}, - {"brleul!", D_cond_br}, - {"breql!", D_cond_br}, - {"brnel!", D_cond_br}, - {"brgtl!", D_cond_br}, - {"brlel!", D_cond_br}, - {"brgel!", D_cond_br}, - {"brltl!", D_cond_br}, - {"brmil!", D_cond_br}, - {"brpll!", D_cond_br}, - {"brvsl!", D_cond_br}, - {"brvcl!", D_cond_br}, - /* conditional move instruction. */ - {"mvcs", D_cond_mv}, - {"mvcc", D_cond_mv}, - {"mvgtu", D_cond_mv}, - {"mvleu", D_cond_mv}, - {"mveq", D_cond_mv}, - {"mvne", D_cond_mv}, - {"mvgt", D_cond_mv}, - {"mvle", D_cond_mv}, - {"mvge", D_cond_mv}, - {"mvlt", D_cond_mv}, - {"mvmi", D_cond_mv}, - {"mvpl", D_cond_mv}, - {"mvvs", D_cond_mv}, - {"mvvc", D_cond_mv}, /* move spectial instruction. */ {"mtcr", D_mtcr}, - {"mftlb", D_mftlb}, - {"mtptlb", D_mtptlb}, - {"mtrtlb", D_mtrtlb}, - {"stlb", D_stlb}, - {"mfcr", D_mfcr}, - {"mfsr", D_mfsr}, - /* cache instruction. */ - {"cache 8", D_cached}, - {"cache 9", D_cached}, - {"cache 10", D_cached}, - {"cache 11", D_cached}, - {"cache 12", D_cached}, - {"cache 13", D_cached}, - {"cache 14", D_cached}, - {"cache 24", D_cached}, - {"cache 26", D_cached}, - {"cache 27", D_cached}, - {"cache 29", D_cached}, - {"cache 30", D_cached}, - {"cache 31", D_cached}, - {"cache 0", D_cachei}, - {"cache 1", D_cachei}, - {"cache 2", D_cachei}, - {"cache 3", D_cachei}, - {"cache 4", D_cachei}, - {"cache 16", D_cachei}, - {"cache 17", D_cachei}, - /* load/store instruction. */ - {"lb", D_ldst}, - {"lbu", D_ldst}, - {"lbu!", D_ldst}, - {"lbup!", D_ldst}, - {"lh", D_ldst}, - {"lhu", D_ldst}, - {"lh!", D_ldst}, - {"lhp!", D_ldst}, - {"lw", D_ldst}, - {"lw!", D_ldst}, - {"lwp!", D_ldst}, - {"sb", D_ldst}, - {"sb!", D_ldst}, - {"sbp!", D_ldst}, - {"sh", D_ldst}, - {"sh!", D_ldst}, - {"shp!", D_ldst}, - {"sw", D_ldst}, - {"sw!", D_ldst}, - {"swp!", D_ldst}, - {"alw", D_ldst}, - {"asw", D_ldst}, - {"push!", D_ldst}, - {"pushhi!", D_ldst}, - {"pop!", D_ldst}, - {"pophi!", D_ldst}, - {"ldc1", D_ldst}, - {"ldc2", D_ldst}, - {"ldc3", D_ldst}, - {"stc1", D_ldst}, - {"stc2", D_ldst}, - {"stc3", D_ldst}, - {"scb", D_ldst}, - {"scw", D_ldst}, - {"sce", D_ldst}, - /* load combine instruction. */ - {"lcb", D_ldcombine}, - {"lcw", D_ldcombine}, - {"lce", D_ldcombine}, }; static const struct data_dependency data_dependency_table[] = { - /* Condition register. */ - {D_mtcr, "cr1", D_pce, "", 2, 1, 1}, - {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1}, - {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1}, /* Status regiser. */ - {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0}, - /* CCR regiser. */ - {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0}, - /* EntryHi/EntryLo register. */ - {D_mftlb, "", D_mtptlb, "", 1, 1, 1}, - {D_mftlb, "", D_mtrtlb, "", 1, 1, 1}, - {D_mftlb, "", D_stlb, "", 1, 1,1}, - {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1}, - {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1}, - /* Index register. */ - {D_stlb, "", D_mtptlb, "", 1, 1, 1}, - {D_stlb, "", D_mftlb, "", 1, 1, 1}, - {D_stlb, "", D_mfcr, "cr8", 2, 2, 1}, - /* Cache. */ - {D_cached, "", D_ldst, "", 1, 1, 0}, - {D_cached, "", D_ldcombine, "", 1, 1, 0}, - {D_cachei, "", D_all_insn, "", 5, 4, 0}, - /* Load combine. */ - {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1}, + {D_mtcr, "cr0", D_all_insn, "", 5, 1, 0}, }; #endif diff --git a/include/opcode/score-inst.h b/include/opcode/score-inst.h index e87794f77..0eac3824c 100644 --- a/include/opcode/score-inst.h +++ b/include/opcode/score-inst.h @@ -1,6 +1,7 @@ /* score-inst.h -- Score Instructions Table - Copyright 2006 Free Software Foundation, Inc. + Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. Contributed by: + Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) Pei-Lin Tsai (pltsai@sunplus.com) @@ -8,7 +9,7 @@ GAS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) + the Free Software Foundation; either version 3, or (at your option) any later version. GAS is distributed in the hope that it will be useful, @@ -96,6 +97,8 @@ enum score_insn_type Rd_Rs_I14, I15, Rd_I16, + Rd_I30, + Rd_I32, Rd_rvalueRs_SI10, Rd_lvalueRs_SI10, Rd_rvalueRs_preSI12, @@ -105,6 +108,8 @@ enum score_insn_type Rd_Rs_SI14, Rd_rvalueRs_SI15, Rd_lvalueRs_SI15, + Rd_SI5, + Rd_SI6, Rd_SI16, PC_DISP8div2, PC_DISP11div2, @@ -139,6 +144,8 @@ enum score_insn_type Insn_GP, Insn_PIC, Insn_internal, + Insn_BCMP, + Ra_I9_I5, }; enum score_data_type @@ -178,6 +185,13 @@ enum score_data_type _SIMM16_pic = 42, /* Index in score_df_range. */ _IMM16_LO16_pic = 43, _IMM16_pic = 44, + + _SIMM5 = 45, + _SIMM6 = 46, + _IMM32 = 47, + _SIMM32 = 48, + _IMM11 = 49, + _IMM5_MULTI_LOAD = 50, }; #define REG_TMP 1 @@ -206,302 +220,17 @@ enum score_data_type #define OP16_SH_DISP8 (OP_IMM_TYPE | 0) #define OP16_SH_DISP11 (OP_IMM_TYPE | 1) -struct datafield_range -{ - int data_type; - int bits; - int range[2]; -}; - -struct datafield_range score_df_range[] = -{ - {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */ - {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */ - {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */ - {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */ - {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ - {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ - {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */ - {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */ - {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */ - {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */ - {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */ - {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */ - {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_IMM20, 20, {0, (1 << 20) - 1}}, - {_IMM25, 25, {0, (1 << 25) - 1}}, - {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */ - {_DISP11div2, 11, {0, 0}}, - {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */ - {_DISP24div2, 24, {0, 0}}, - {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}}, - {_VALUE_HI16, 16, {0, (1 << 16) - 1}}, - {_VALUE_LO16, 16, {0, (1 << 16) - 1}}, - {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}}, - {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */ - {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */ - {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ - {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */ - {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */ - {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */ - {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */ - {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */ - {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */ - {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */ - {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */ - {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ - {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ - {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */ - {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */ - {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */ - {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */ - {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ - {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ -}; - -struct shift_bitmask -{ - int opd_type; - int opd_num; - struct datafield_range *df_range; - int sh[4]; - long fieldbits[4]; -}; - -struct shift_bitmask score_sh_bits_map[] = -{ - { - Rd_I4, 2, &score_df_range[_IMM4], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0xf, 0, 0}, - }, - { - Rd_I5, 2, &score_df_range[_IMM5], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0x1f, 0, 0}, - }, - { - Rd_rvalueBP_I5, 2, &score_df_range[_IMM5], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0x1f, 0, 0}, - }, - { - Rd_lvalueBP_I5, 2, &score_df_range[_IMM5], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0x1f, 0, 0}, - }, - { - Rd_Rs_I5, 3, &score_df_range[_IMM5], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0}, - {0x1f, 0x1f, 0x1f, 0}, - }, - { - x_Rs_I5, 2, &score_df_range[_IMM5], - {OP_SH_REGS1, OP_SH_I5, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - x_I5_x, 1, &score_df_range[_IMM5], - {OP_SH_TRAPI5, 0, 0, 0}, - {0x1f, 0, 0, 0}, - }, - { - Rd_I8, 2, &score_df_range[_IMM8], - {OP16_SH_REGD, OP16_SH_I8, 0, 0}, - {0xf, 0xff, 0, 0}, - }, - { - Rd_Rs_I14, 3, &score_df_range[_IMM14], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, - {0x1f, 0x1f, 0x3fff, 0}, - }, - { - I15, 1, &score_df_range[_IMM15], - {OP_SH_I15, 0, 0, 0}, - {0x7fff, 0, 0, 0}, - }, - { - Rd_I16, 2, &score_df_range[_IMM16], - {OP_SH_REGD, OP_SH_I, 0, 0}, - {0x1f, 0xffff, 0, 0}, - }, - { - Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, - {0x1f, 0x1f, 0x3ff, 0}, - }, - { - Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, - {0x1f, 0x1f, 0x3ff, 0}, - }, - { - Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_Rs_SI14, 3, &score_df_range[_SIMM14], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, - {0x1f, 0x1f, 0x3fff, 0}, - }, - { - Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, - {0x1f, 0x1f, 0x7fff, 0}, - }, - { - Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, - {0x1f, 0x1f, 0x7fff, 0}, - }, - { - Rd_SI16, 2, &score_df_range[_SIMM16], - {OP_SH_REGD, OP_SH_I, 0, 0}, - {0x1f, 0xffff, 0, 0}, - }, - { - PC_DISP8div2, 1, &score_df_range[_DISP8div2], - {OP16_SH_DISP8, 0, 0, 0}, - {0xff, 0, 0, 0}, - }, - { - PC_DISP11div2, 1, &score_df_range[_DISP11div2], - {OP16_SH_DISP11, 0, 0, 0}, - {0x7ff, 0, 0, 0}, - }, - { - PC_DISP19div2, 2, &score_df_range[_DISP19div2], - {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0}, - {0x3ff, 0x1ff, 0, 0}, - }, - { - PC_DISP24div2, 1, &score_df_range[_DISP24div2], - {OP_SH_DISP24, 0, 0, 0}, - {0xffffff, 0, 0, 0}, - }, - { - Rd_Rs_Rs, 3, NULL, - {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0}, - {0x1f, 0x1f, 0x1f, 0} - }, - { - Rd_Rs_x, 2, NULL, - {OP_SH_REGD, OP_SH_REGS1, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - Rd_x_Rs, 2, NULL, - {OP_SH_REGD, OP_SH_REGS2, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - Rd_x_x, 1, NULL, - {OP_SH_REGD, 0, 0, 0}, - {0x1f, 0, 0, 0}, - }, - { - x_Rs_Rs, 2, NULL, - {OP_SH_REGS1, OP_SH_REGS2, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - x_Rs_x, 1, NULL, - {OP_SH_REGS1, 0, 0, 0}, - {0x1f, 0, 0, 0}, - }, - { - Rd_Rs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0, 0}, - }, - { - Rd_HighRs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0x1f, 0}, - }, - { - Rd_rvalueRs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0, 0}, - }, - { - Rd_lvalueRs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0, 0} - }, - { - Rd_lvalue32Rs, 2, NULL, - {OP_SH_REGD, OP_SH_REGS1, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - Rd_rvalue32Rs, 2, NULL, - {OP_SH_REGD, OP_SH_REGS1, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - x_Rs, 1, NULL, - {OP16_SH_REGS1, 0, 0, 0}, - {0xf, 0, 0, 0}, - }, - { - NO_OPD, 0, NULL, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - }, - { - NO16_OPD, 0, NULL, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - }, -}; - -struct asm_opcode -{ - /* Instruction name. */ - const char *template; - - /* Instruction Opcode. */ - unsigned long value; - - /* Instruction bit mask. */ - unsigned long bitmask; - - /* Relax instruction opcode. 0x8000 imply no relaxation. */ - unsigned long relax_value; - - /* Instruction type. */ - enum score_insn_type type; - - /* Function to call to parse args. */ - void (*parms) (char *); -}; - enum insn_class { INSN_CLASS_16, INSN_CLASS_32, + INSN_CLASS_48, INSN_CLASS_PCE, INSN_CLASS_SYN }; +/* s3_s7: Globals for both tc-score.c and elf32-score.c. */ +extern int score3; +extern int score7; + #endif