include/
* xtensa-config.h (XCHAL_HAVE_MUL16, XCHAL_HAVE_MUL32, XCHAL_HAVE_DIV32) (XCHAL_HAVE_MINMAX, XCHAL_HAVE_SEXT, XCHAL_HAVE_THREADPTR) (XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): Change to 1. (XCHAL_NUM_AREGS): Change to 32. (XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE): Change to 16K. (XCHAL_ICACHE_LINESIZE, XCHAL_DCACHE_LINESIZE): Change to 32. (XCHAL_ICACHE_LINEWIDTH, XCHAL_DCACHE_LINEWIDTH): Change to 5. (XCHAL_DCACHE_IS_WRITEBACK): Change to 1. (XCHAL_DEBUGLEVEL): Change to 6. bfd/ * xtensa-modules.c (sysregs): Add MMID, VECBASE, EPC5, EPC6, EPC7, EXCSAVE5, EXCSAVE6, EXCSAVE7, EPS5, EPS6, EPS7, CPENABLE, SCOMPARE1, and THREADPTR registers. (NUM_SYSREGS, MAX_USER_REG): Update. (states): Change width of INTERRUPT, WindowBase, WindowStart, and INTENABLE. Add VECBASE, EPC5, EPC6, EPC7, EXCSAVE5, EXCSAVE6, EXCSAVE7, EPS6, EPS6, EPS7, THREADPTR, CPENABLE, and SCOMPARE1 states. (NUM_STATES): Update. (enum xtensa_state_id): Add entries for new states. (enum xtensa_field_id): Add entries for xt_wbr15_imm and xt_wbr18_imm fields, along with functions to extract and set them. (regfiles): Change number of AR registers to 32. (Operand_ar0_encode, Operand_ar4_encode, Operand_ar8_encode, Operand_ar12_encode, Operand_ars_entry_encode): Update register mask. (operands): Add entries for tp7, xt_wbr15_label, xt_wbr18_label, xt_wbr15_imm, and xt_wbr18_imm operands, along with functions to encode and decode them. (enum xtensa_operand_id): Add entries for new operands. (Iclass_xt_iclass_rfi_stateArgs): Add EPC5, EPC6, EPC7, EPS5, EPS6, and EPC7 states. (Iclass_xt_iclass_rfdo_stateArgs): Replace EPC4 and EPS4 by EPC6 and EPS6, respectively. (iclasses): Add entries for rur_threadptr, wur_threadptr, xt_iclass_wsr_176, xt_iclass_rsr_epc5, xt_iclass_wsr_epc5, xt_iclass_xsr_epc5, xt_iclass_rsr_excsave5, xt_iclass_wsr_excsave5, xt_iclass_xsr_excsave5, xt_iclass_rsr_epc6, xt_iclass_wsr_epc6, xt_iclass_xsr_epc6, xt_iclass_rsr_excsave6, xt_iclass_wsr_excsave6, xt_iclass_xsr_excsave6, xt_iclass_rsr_epc7, xt_iclass_wsr_epc7, xt_iclass_xsr_epc7, xt_iclass_rsr_excsave7, xt_iclass_wsr_excsave7, xt_iclass_xsr_excsave7, xt_iclass_rsr_eps5, xt_iclass_wsr_eps5, xt_iclass_xsr_eps5, xt_iclass_rsr_eps6, xt_iclass_wsr_eps6, xt_iclass_xsr_eps6, xt_iclass_rsr_eps7, xt_iclass_wsr_eps7, xt_iclass_xsr_eps7, xt_iclass_rsr_vecbase, xt_iclass_wsr_vecbase, xt_iclass_xsr_vecbase, xt_iclass_mul16, xt_iclass_wsr_mmid, xt_iclass_icache_lock, xt_iclass_dcache_lock, xt_iclass_rsr_cpenable, xt_iclass_wsr_cpenable, xt_iclass_xsr_cpenable, xt_iclass_clamp, xt_iclass_minmax, xt_iclass_sx, xt_iclass_l32ai, xt_iclass_s32ri, xt_iclass_s32c1i, xt_iclass_rsr_scompare1, xt_iclass_wsr_scompare1, xt_iclass_xsr_scompare1, xt_iclass_div, and xt_iclass_mul32, along with corresponding argument and state argument arrays. Change number of state arguments for xt_iclass_rfi. Add arguments for xt_iclass_rfdo. (enum xtensa_iclass_id): Add entries for new iclasses. (opcodes): Add entries for RUR_THREADPTR, WUR_THREADPTR, WSR_176, RSR_EPC5, WSR_EPC5, XSR_EPC5, RSR_EXCSAVE5, WSR_EXCSAVE5, XSR_EXCSAVE5, RSR_EPC6, WSR_EPC6, XSR_EPC6, RSR_EXCSAVE6, WSR_EXCSAVE6, XSR_EXCSAVE6, RSR_EPC7, WSR_EPC7, XSR_EPC7, RSR_EXCSAVE7, WSR_EXCSAVE7, XSR_EXCSAVE7, RSR_EPS5, WSR_EPS5, XSR_EPS5, RSR_EPS6, WSR_EPS6, XSR_EPS6, RSR_EPS7, WSR_EPS7, XSR_EPS7, RSR_VECBASE, WSR_VECBASE, XSR_VECBASE, MUL16U, MUL16S, WSR_MMID, IPFL, IHU, IIU, DPFL, DHU, DIU, RSR_CPENABLE, WSR_CPENABLE, XSR_CPENABLE, CLAMPS, MIN, MAX, MINU, MAXU, SEXT, L32AI, S32RI, S32C1I, RSR_SCOMPARE1, WSR_SCOMPARE1, XSR_SCOMPARE1, QUOU, QUOS, REMU, REMS, and MULL opcodes, along with the corresponding functions to encode them. (enum xtensa_opcode_id): Add entries for new opcodes. (Slot_inst_decode): Handle new opcodes. (Slot_inst_get_field_fns, Slot_inst_set_field_fns): Add entries for xt_wbr15_imm and xt_wbr18_imm fields. (Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns): Likewise. (Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns): Likewise. (xtensa_modules): Update number of fields, operands, iclasses and opcodes.
This commit is contained in:
Bob Wilson
parent
c58cf6af0f
commit
7562a08bb4
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@ -1,3 +1,15 @@
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2008-11-19 Bob Wilson <bob.wilson@acm.org>
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* xtensa-config.h (XCHAL_HAVE_MUL16, XCHAL_HAVE_MUL32, XCHAL_HAVE_DIV32)
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(XCHAL_HAVE_MINMAX, XCHAL_HAVE_SEXT, XCHAL_HAVE_THREADPTR)
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(XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): Change to 1.
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(XCHAL_NUM_AREGS): Change to 32.
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(XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE): Change to 16K.
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(XCHAL_ICACHE_LINESIZE, XCHAL_DCACHE_LINESIZE): Change to 32.
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(XCHAL_ICACHE_LINEWIDTH, XCHAL_DCACHE_LINEWIDTH): Change to 5.
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(XCHAL_DCACHE_IS_WRITEBACK): Change to 1.
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(XCHAL_DEBUGLEVEL): Change to 6.
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2008-11-14 Tristan Gingold <gingold@adacore.com>
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* fopen-vms.h (FOPEN_RB): Use a single string to match the
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@ -1,5 +1,5 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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@ -50,37 +50,37 @@
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#define XCHAL_HAVE_MAC16 0
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 0
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 0
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 0
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 0
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 0
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 0
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 0
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 0
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 0
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 0
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@ -104,7 +104,7 @@
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 64
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#define XCHAL_NUM_AREGS 32
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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@ -114,25 +114,25 @@
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 8192
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#define XCHAL_ICACHE_SIZE 16384
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 8192
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#define XCHAL_DCACHE_SIZE 16384
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 16
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#define XCHAL_ICACHE_LINESIZE 32
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 16
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#define XCHAL_DCACHE_LINESIZE 32
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 4
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#define XCHAL_ICACHE_LINEWIDTH 5
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 4
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#define XCHAL_DCACHE_LINEWIDTH 5
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 0
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#define XCHAL_DCACHE_IS_WRITEBACK 1
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#undef XCHAL_HAVE_MMU
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@ -152,7 +152,7 @@
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 4
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#define XCHAL_DEBUGLEVEL 6
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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