Add support for Score target.
This commit is contained in:
Nick Clifton
parent
3e231d9a38
commit
7aa8dc8eb0
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@ -1,3 +1,7 @@
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2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
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* dis-asm.h: Add prototypes for Score disassembler routines.
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2006-09-07 H.J. Lu <hongjiu.lu@intel.com>
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* bfdlink.h (bfd_elf_dynamic_list): New.
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@ -1,6 +1,6 @@
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/* Interface between the opcode library and its callers.
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Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
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Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
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Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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@ -37,7 +37,8 @@ extern "C" {
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typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
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enum dis_insn_type {
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enum dis_insn_type
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{
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dis_noninsn, /* Not a valid instruction */
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dis_nonbranch, /* Not a branch instruction */
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dis_branch, /* Unconditional branch */
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@ -58,7 +59,8 @@ enum dis_insn_type {
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It must be initialized before it is first passed; this can be done
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by hand, or using one of the initialization macros below. */
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typedef struct disassemble_info {
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typedef struct disassemble_info
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{
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fprintf_ftype fprintf_func;
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void *stream;
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void *application_data;
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@ -201,59 +203,63 @@ typedef struct disassemble_info {
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target address. Return number of octets processed. */
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typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
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extern int print_insn_big_mips (bfd_vma, disassemble_info *);
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extern int print_insn_little_mips (bfd_vma, disassemble_info *);
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extern int print_insn_i386 (bfd_vma, disassemble_info *);
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extern int print_insn_i386_att (bfd_vma, disassemble_info *);
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extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
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extern int print_insn_ia64 (bfd_vma, disassemble_info *);
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extern int print_insn_i370 (bfd_vma, disassemble_info *);
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extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
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extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
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extern int print_insn_m68k (bfd_vma, disassemble_info *);
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extern int print_insn_z80 (bfd_vma, disassemble_info *);
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extern int print_insn_z8001 (bfd_vma, disassemble_info *);
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extern int print_insn_z8002 (bfd_vma, disassemble_info *);
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extern int print_insn_h8300 (bfd_vma, disassemble_info *);
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extern int print_insn_h8300h (bfd_vma, disassemble_info *);
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extern int print_insn_h8300s (bfd_vma, disassemble_info *);
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extern int print_insn_h8500 (bfd_vma, disassemble_info *);
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extern int print_insn_alpha (bfd_vma, disassemble_info *);
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extern int print_insn_big_arm (bfd_vma, disassemble_info *);
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extern int print_insn_little_arm (bfd_vma, disassemble_info *);
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extern int print_insn_sparc (bfd_vma, disassemble_info *);
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extern int print_insn_avr (bfd_vma, disassemble_info *);
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extern int print_insn_bfin (bfd_vma, disassemble_info *);
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extern int print_insn_big_arm (bfd_vma, disassemble_info *);
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extern int print_insn_big_mips (bfd_vma, disassemble_info *);
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extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
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extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
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extern int print_insn_big_score (bfd_vma, disassemble_info *);
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extern int print_insn_crx (bfd_vma, disassemble_info *);
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extern int print_insn_d10v (bfd_vma, disassemble_info *);
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extern int print_insn_d30v (bfd_vma, disassemble_info *);
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extern int print_insn_dlx (bfd_vma, disassemble_info *);
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extern int print_insn_fr30 (bfd_vma, disassemble_info *);
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extern int print_insn_frv (bfd_vma, disassemble_info *);
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extern int print_insn_h8300 (bfd_vma, disassemble_info *);
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extern int print_insn_h8300h (bfd_vma, disassemble_info *);
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extern int print_insn_h8300s (bfd_vma, disassemble_info *);
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extern int print_insn_h8500 (bfd_vma, disassemble_info *);
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extern int print_insn_hppa (bfd_vma, disassemble_info *);
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extern int print_insn_i370 (bfd_vma, disassemble_info *);
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extern int print_insn_i386 (bfd_vma, disassemble_info *);
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extern int print_insn_i386_att (bfd_vma, disassemble_info *);
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extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
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extern int print_insn_i860 (bfd_vma, disassemble_info *);
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extern int print_insn_i960 (bfd_vma, disassemble_info *);
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extern int print_insn_ia64 (bfd_vma, disassemble_info *);
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extern int print_insn_ip2k (bfd_vma, disassemble_info *);
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extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
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extern int print_insn_little_arm (bfd_vma, disassemble_info *);
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extern int print_insn_little_mips (bfd_vma, disassemble_info *);
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extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
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extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
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extern int print_insn_little_score (bfd_vma, disassemble_info *);
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extern int print_insn_m32c (bfd_vma, disassemble_info *);
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extern int print_insn_m32r (bfd_vma, disassemble_info *);
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extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
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extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
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extern int print_insn_m68k (bfd_vma, disassemble_info *);
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extern int print_insn_m88k (bfd_vma, disassemble_info *);
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extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
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extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
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extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
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extern int print_insn_mcore (bfd_vma, disassemble_info *);
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extern int print_insn_mmix (bfd_vma, disassemble_info *);
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extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
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extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
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extern int print_insn_mt (bfd_vma, disassemble_info *);
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extern int print_insn_msp430 (bfd_vma, disassemble_info *);
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extern int print_insn_mt (bfd_vma, disassemble_info *);
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extern int print_insn_ns32k (bfd_vma, disassemble_info *);
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extern int print_insn_crx (bfd_vma, disassemble_info *);
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extern int print_insn_openrisc (bfd_vma, disassemble_info *);
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extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
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extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
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extern int print_insn_pdp11 (bfd_vma, disassemble_info *);
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extern int print_insn_pj (bfd_vma, disassemble_info *);
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extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
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extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
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extern int print_insn_rs6000 (bfd_vma, disassemble_info *);
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extern int print_insn_s390 (bfd_vma, disassemble_info *);
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extern int print_insn_sh (bfd_vma, disassemble_info *);
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extern int print_insn_sh64 (bfd_vma, disassemble_info *);
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extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
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extern int print_insn_sparc (bfd_vma, disassemble_info *);
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extern int print_insn_tic30 (bfd_vma, disassemble_info *);
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extern int print_insn_tic4x (bfd_vma, disassemble_info *);
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extern int print_insn_tic54x (bfd_vma, disassemble_info *);
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@ -261,14 +267,12 @@ extern int print_insn_tic80 (bfd_vma, disassemble_info *);
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extern int print_insn_v850 (bfd_vma, disassemble_info *);
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extern int print_insn_vax (bfd_vma, disassemble_info *);
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extern int print_insn_w65 (bfd_vma, disassemble_info *);
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extern int print_insn_xc16x (bfd_vma, disassemble_info *);
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extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
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extern int print_insn_xtensa (bfd_vma, disassemble_info *);
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extern int print_insn_sh64 (bfd_vma, disassemble_info *);
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extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
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extern int print_insn_frv (bfd_vma, disassemble_info *);
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extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
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extern int print_insn_xc16x (bfd_vma, disassemble_info *);
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extern int print_insn_m32c (bfd_vma, disassemble_info *);
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extern int print_insn_z80 (bfd_vma, disassemble_info *);
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extern int print_insn_z8001 (bfd_vma, disassemble_info *);
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extern int print_insn_z8002 (bfd_vma, disassemble_info *);
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extern disassembler_ftype arc_get_disassembler (void *);
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extern disassembler_ftype cris_get_disassembler (bfd *);
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@ -277,9 +281,9 @@ extern void print_mips_disassembler_options (FILE *);
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extern void print_ppc_disassembler_options (FILE *);
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extern void print_arm_disassembler_options (FILE *);
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extern void parse_arm_disassembler_option (char *);
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extern int get_arm_regname_num_options (void);
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extern int set_arm_regname_option (int);
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extern int get_arm_regnames (int, const char **, const char **, const char *const **);
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extern int get_arm_regname_num_options (void);
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extern int set_arm_regname_option (int);
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extern int get_arm_regnames (int, const char **, const char **, const char *const **);
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extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
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/* Fetch the disassembler for a given BFD, if that support is available. */
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@ -1,3 +1,8 @@
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2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
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* score.h: New file.
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* common.h: Add Score machine number.
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2006-07-10 Jakub Jelinek <jakub@redhat.com>
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* common.h (SHT_GNU_HASH, DT_GNU_HASH): Define.
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@ -185,6 +185,7 @@
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#define EM_BLACKFIN 106 /* ADI Blackfin */
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#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
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#define EM_CRX 114 /* National Semiconductor CRX */
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#define EM_SCORE 135 /* Sunplus Score */
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/* If it is necessary to assign new unofficial EM_* values, please pick large
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random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
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@ -0,0 +1,124 @@
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/* Score ELF support for BFD.
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Copyright 2006 Free Software Foundation, Inc.
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Contributed by
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Mei Ligang (ligang@sunnorth.com.cn)
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Pei-Lin Tsai (pltsai@sunplus.com)
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation,
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef _ELF_SCORE_H
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#define _ELF_SCORE_H
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#include "elf/reloc-macros.h"
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#define SCORE_SIMULATOR_ACTIVE 1
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#define OPC_PTMASK 0xc0000000 /* Parity-bit Mask */
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#define OPC16_PTMASK 0x00008000
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/* The parity-bit denotes. */
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#define OPC_32 0xc0000000 /* denotes 32b instruction, (default) */
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#define OPC_16 0x00000000 /* denotes 16b instruction */
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#define OPC_PE 0x8000 /* denotes parallel-execution instructions */
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#define EF_SCORE_HASENTRY 0x02
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#define GP_DISP_LABEL "_gp_disp"
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/* Processor specific flags for the ELF header e_flags field. */
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/* Fix data dependency. */
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#define EF_SCORE_FIXDEP 0x00000001
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/* File contains position independent code. */
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#define EF_SCORE_PIC 0x00000002
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/* Defined and allocated common symbol. Value is virtual address. If
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relocated, alignment must be preserved. */
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#define SHN_SCORE_TEXT 0xff01
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#define SHN_SCORE_DATA 0xff02
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/* Small common symbol. */
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#define SHN_SCORE_SCOMMON 0xff03
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/* Processor specific section flags. */
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/* This section must be in the global data area. */
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#define SHF_SCORE_GPREL 0x10000000
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/* This section should be merged. */
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#define SHF_SCORE_MERGE 0x20000000
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/* This section contains address data of size implied by section
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element size. */
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#define SHF_SCORE_ADDR 0x40000000
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/* This section contains string data. */
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#define SHF_SCORE_STRING 0x80000000
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/* This section may not be stripped. */
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#define SHF_SCORE_NOSTRIP 0x08000000
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/* This section is local to threads. */
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#define SHF_SCORE_LOCAL 0x04000000
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/* Linker should generate implicit weak names for this section. */
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#define SHF_SCORE_NAMES 0x02000000
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/* Section contais text/data which may be replicated in other sections.
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Linker should retain only one copy. */
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#define SHF_SCORE_NODUPES 0x01000000
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/* Processor specific dynamic array tags. */
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/* Base address of the segment. */
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#define DT_SCORE_BASE_ADDRESS 0x70000001
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/* Number of local global offset table entries. */
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#define DT_SCORE_LOCAL_GOTNO 0x70000002
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/* Number of entries in the .dynsym section. */
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#define DT_SCORE_SYMTABNO 0x70000003
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/* Index of first dynamic symbol in global offset table. */
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#define DT_SCORE_GOTSYM 0x70000004
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/* Index of first external dynamic symbol not referenced locally. */
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#define DT_SCORE_UNREFEXTNO 0x70000005
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/* Number of page table entries in global offset table. */
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#define DT_SCORE_HIPAGENO 0x70000006
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/* Processor specific section types. */
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/* Relocation types. */
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START_RELOC_NUMBERS (elf_score_reloc_type)
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RELOC_NUMBER (R_SCORE_NONE, 0)
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RELOC_NUMBER (R_SCORE_HI16, 1)
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RELOC_NUMBER (R_SCORE_LO16, 2)
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RELOC_NUMBER (R_SCORE_DUMMY1, 3)
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RELOC_NUMBER (R_SCORE_24, 4)
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RELOC_NUMBER (R_SCORE_PC19, 5)
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RELOC_NUMBER (R_SCORE16_11, 6)
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RELOC_NUMBER (R_SCORE16_PC8, 7)
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RELOC_NUMBER (R_SCORE_ABS32, 8)
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RELOC_NUMBER (R_SCORE_ABS16, 9)
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RELOC_NUMBER (R_SCORE_DUMMY2, 10)
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RELOC_NUMBER (R_SCORE_GP15, 11)
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RELOC_NUMBER (R_SCORE_GNU_VTINHERIT, 12)
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RELOC_NUMBER (R_SCORE_GNU_VTENTRY, 13)
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RELOC_NUMBER (R_SCORE_GOT15, 14)
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RELOC_NUMBER (R_SCORE_GOT_LO16, 15)
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RELOC_NUMBER (R_SCORE_CALL15, 16)
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RELOC_NUMBER (R_SCORE_GPREL32, 17)
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RELOC_NUMBER (R_SCORE_REL32, 18)
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RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19)
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END_RELOC_NUMBERS (R_SCORE_max)
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#endif /* _ELF_SCORE_H */
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@ -1,3 +1,8 @@
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2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
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* score-datadep.h: New file.
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* score-inst.h: New file.
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2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
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@ -0,0 +1,282 @@
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/* score-datadep.h -- Score Instructions data dependency table
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Copyright 2006 Free Software Foundation, Inc.
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Contributed by:
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Mei Ligang (ligang@sunnorth.com.cn)
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Pei-Lin Tsai (pltsai@sunplus.com)
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#ifndef SCORE_DATA_DEPENDENCY_H
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#define SCORE_DATA_DEPENDENCY_H
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#define INSN_NAME_LEN 16
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enum insn_type_for_dependency
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{
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D_pce,
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D_cond_br,
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D_cond_mv,
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D_cached,
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D_cachei,
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D_ldst,
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D_ldcombine,
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D_mtcr,
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D_mfcr,
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D_mfsr,
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D_mftlb,
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D_mtptlb,
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D_mtrtlb,
|
||||
D_stlb,
|
||||
D_all_insn
|
||||
};
|
||||
|
||||
struct insn_to_dependency
|
||||
{
|
||||
char *insn_name;
|
||||
enum insn_type_for_dependency type;
|
||||
};
|
||||
|
||||
struct data_dependency
|
||||
{
|
||||
enum insn_type_for_dependency pre_insn_type;
|
||||
char pre_reg[6];
|
||||
enum insn_type_for_dependency cur_insn_type;
|
||||
char cur_reg[6];
|
||||
int bubblenum_7;
|
||||
int bubblenum_5;
|
||||
int warn_or_error; /* warning - 0; error - 1 */
|
||||
};
|
||||
|
||||
static const struct insn_to_dependency insn_to_dependency_table[] =
|
||||
{
|
||||
/* pce instruction. */
|
||||
{"pce", D_pce},
|
||||
/* conditional branch instruction. */
|
||||
{"bcs", D_cond_br},
|
||||
{"bcc", D_cond_br},
|
||||
{"bgtu", D_cond_br},
|
||||
{"bleu", D_cond_br},
|
||||
{"beq", D_cond_br},
|
||||
{"bne", D_cond_br},
|
||||
{"bgt", D_cond_br},
|
||||
{"ble", D_cond_br},
|
||||
{"bge", D_cond_br},
|
||||
{"blt", D_cond_br},
|
||||
{"bmi", D_cond_br},
|
||||
{"bpl", D_cond_br},
|
||||
{"bvs", D_cond_br},
|
||||
{"bvc", D_cond_br},
|
||||
{"bcsl", D_cond_br},
|
||||
{"bccl", D_cond_br},
|
||||
{"bgtul", D_cond_br},
|
||||
{"bleul", D_cond_br},
|
||||
{"beql", D_cond_br},
|
||||
{"bnel", D_cond_br},
|
||||
{"bgtl", D_cond_br},
|
||||
{"blel", D_cond_br},
|
||||
{"bgel", D_cond_br},
|
||||
{"bltl", D_cond_br},
|
||||
{"bmil", D_cond_br},
|
||||
{"bpll", D_cond_br},
|
||||
{"bvsl", D_cond_br},
|
||||
{"bvcl", D_cond_br},
|
||||
{"bcs!", D_cond_br},
|
||||
{"bcc!", D_cond_br},
|
||||
{"bgtu!", D_cond_br},
|
||||
{"bleu!", D_cond_br},
|
||||
{"beq!", D_cond_br},
|
||||
{"bne!", D_cond_br},
|
||||
{"bgt!", D_cond_br},
|
||||
{"ble!", D_cond_br},
|
||||
{"bge!", D_cond_br},
|
||||
{"blt!", D_cond_br},
|
||||
{"bmi!", D_cond_br},
|
||||
{"bpl!", D_cond_br},
|
||||
{"bvs!", D_cond_br},
|
||||
{"bvc!", D_cond_br},
|
||||
{"brcs", D_cond_br},
|
||||
{"brcc", D_cond_br},
|
||||
{"brgtu", D_cond_br},
|
||||
{"brleu", D_cond_br},
|
||||
{"breq", D_cond_br},
|
||||
{"brne", D_cond_br},
|
||||
{"brgt", D_cond_br},
|
||||
{"brle", D_cond_br},
|
||||
{"brge", D_cond_br},
|
||||
{"brlt", D_cond_br},
|
||||
{"brmi", D_cond_br},
|
||||
{"brpl", D_cond_br},
|
||||
{"brvs", D_cond_br},
|
||||
{"brvc", D_cond_br},
|
||||
{"brcsl", D_cond_br},
|
||||
{"brccl", D_cond_br},
|
||||
{"brgtul", D_cond_br},
|
||||
{"brleul", D_cond_br},
|
||||
{"breql", D_cond_br},
|
||||
{"brnel", D_cond_br},
|
||||
{"brgtl", D_cond_br},
|
||||
{"brlel", D_cond_br},
|
||||
{"brgel", D_cond_br},
|
||||
{"brltl", D_cond_br},
|
||||
{"brmil", D_cond_br},
|
||||
{"brpll", D_cond_br},
|
||||
{"brvsl", D_cond_br},
|
||||
{"brvcl", D_cond_br},
|
||||
{"brcs!", D_cond_br},
|
||||
{"brcc!", D_cond_br},
|
||||
{"brgtu!", D_cond_br},
|
||||
{"brleu!", D_cond_br},
|
||||
{"breq!", D_cond_br},
|
||||
{"brne!", D_cond_br},
|
||||
{"brgt!", D_cond_br},
|
||||
{"brle!", D_cond_br},
|
||||
{"brge!", D_cond_br},
|
||||
{"brlt!", D_cond_br},
|
||||
{"brmi!", D_cond_br},
|
||||
{"brpl!", D_cond_br},
|
||||
{"brvs!", D_cond_br},
|
||||
{"brvc!", D_cond_br},
|
||||
{"brcsl!", D_cond_br},
|
||||
{"brccl!", D_cond_br},
|
||||
{"brgtul!", D_cond_br},
|
||||
{"brleul!", D_cond_br},
|
||||
{"breql!", D_cond_br},
|
||||
{"brnel!", D_cond_br},
|
||||
{"brgtl!", D_cond_br},
|
||||
{"brlel!", D_cond_br},
|
||||
{"brgel!", D_cond_br},
|
||||
{"brltl!", D_cond_br},
|
||||
{"brmil!", D_cond_br},
|
||||
{"brpll!", D_cond_br},
|
||||
{"brvsl!", D_cond_br},
|
||||
{"brvcl!", D_cond_br},
|
||||
/* conditional move instruction. */
|
||||
{"mvcs", D_cond_mv},
|
||||
{"mvcc", D_cond_mv},
|
||||
{"mvgtu", D_cond_mv},
|
||||
{"mvleu", D_cond_mv},
|
||||
{"mveq", D_cond_mv},
|
||||
{"mvne", D_cond_mv},
|
||||
{"mvgt", D_cond_mv},
|
||||
{"mvle", D_cond_mv},
|
||||
{"mvge", D_cond_mv},
|
||||
{"mvlt", D_cond_mv},
|
||||
{"mvmi", D_cond_mv},
|
||||
{"mvpl", D_cond_mv},
|
||||
{"mvvs", D_cond_mv},
|
||||
{"mvvc", D_cond_mv},
|
||||
/* move spectial instruction. */
|
||||
{"mtcr", D_mtcr},
|
||||
{"mftlb", D_mftlb},
|
||||
{"mtptlb", D_mtptlb},
|
||||
{"mtrtlb", D_mtrtlb},
|
||||
{"stlb", D_stlb},
|
||||
{"mfcr", D_mfcr},
|
||||
{"mfsr", D_mfsr},
|
||||
/* cache instruction. */
|
||||
{"cache 8", D_cached},
|
||||
{"cache 9", D_cached},
|
||||
{"cache 10", D_cached},
|
||||
{"cache 11", D_cached},
|
||||
{"cache 12", D_cached},
|
||||
{"cache 13", D_cached},
|
||||
{"cache 14", D_cached},
|
||||
{"cache 24", D_cached},
|
||||
{"cache 26", D_cached},
|
||||
{"cache 27", D_cached},
|
||||
{"cache 29", D_cached},
|
||||
{"cache 30", D_cached},
|
||||
{"cache 31", D_cached},
|
||||
{"cache 0", D_cachei},
|
||||
{"cache 1", D_cachei},
|
||||
{"cache 2", D_cachei},
|
||||
{"cache 3", D_cachei},
|
||||
{"cache 4", D_cachei},
|
||||
{"cache 16", D_cachei},
|
||||
{"cache 17", D_cachei},
|
||||
/* load/store instruction. */
|
||||
{"lb", D_ldst},
|
||||
{"lbu", D_ldst},
|
||||
{"lbu!", D_ldst},
|
||||
{"lbup!", D_ldst},
|
||||
{"lh", D_ldst},
|
||||
{"lhu", D_ldst},
|
||||
{"lh!", D_ldst},
|
||||
{"lhp!", D_ldst},
|
||||
{"lw", D_ldst},
|
||||
{"lw!", D_ldst},
|
||||
{"lwp!", D_ldst},
|
||||
{"sb", D_ldst},
|
||||
{"sb!", D_ldst},
|
||||
{"sbp!", D_ldst},
|
||||
{"sh", D_ldst},
|
||||
{"sh!", D_ldst},
|
||||
{"shp!", D_ldst},
|
||||
{"sw", D_ldst},
|
||||
{"sw!", D_ldst},
|
||||
{"swp!", D_ldst},
|
||||
{"alw", D_ldst},
|
||||
{"asw", D_ldst},
|
||||
{"push!", D_ldst},
|
||||
{"pushhi!", D_ldst},
|
||||
{"pop!", D_ldst},
|
||||
{"pophi!", D_ldst},
|
||||
{"ldc1", D_ldst},
|
||||
{"ldc2", D_ldst},
|
||||
{"ldc3", D_ldst},
|
||||
{"stc1", D_ldst},
|
||||
{"stc2", D_ldst},
|
||||
{"stc3", D_ldst},
|
||||
{"scb", D_ldst},
|
||||
{"scw", D_ldst},
|
||||
{"sce", D_ldst},
|
||||
/* load combine instruction. */
|
||||
{"lcb", D_ldcombine},
|
||||
{"lcw", D_ldcombine},
|
||||
{"lce", D_ldcombine},
|
||||
};
|
||||
|
||||
static const struct data_dependency data_dependency_table[] =
|
||||
{
|
||||
/* Condition register. */
|
||||
{D_mtcr, "cr1", D_pce, "", 2, 1, 1},
|
||||
{D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
|
||||
{D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
|
||||
/* Status regiser. */
|
||||
{D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
|
||||
/* CCR regiser. */
|
||||
{D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
|
||||
/* EntryHi/EntryLo register. */
|
||||
{D_mftlb, "", D_mtptlb, "", 1, 1, 1},
|
||||
{D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
|
||||
{D_mftlb, "", D_stlb, "", 1, 1,1},
|
||||
{D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
|
||||
{D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
|
||||
/* Index register. */
|
||||
{D_stlb, "", D_mtptlb, "", 1, 1, 1},
|
||||
{D_stlb, "", D_mftlb, "", 1, 1, 1},
|
||||
{D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
|
||||
/* Cache. */
|
||||
{D_cached, "", D_ldst, "", 1, 1, 0},
|
||||
{D_cached, "", D_ldcombine, "", 1, 1, 0},
|
||||
{D_cachei, "", D_all_insn, "", 5, 4, 0},
|
||||
/* Load combine. */
|
||||
{D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,506 @@
|
|||
/* score-inst.h -- Score Instructions Table
|
||||
Copyright 2006 Free Software Foundation, Inc.
|
||||
Contributed by:
|
||||
Mei Ligang (ligang@sunnorth.com.cn)
|
||||
Pei-Lin Tsai (pltsai@sunplus.com)
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#ifndef SCORE_INST_H
|
||||
#define SCORE_INST_H
|
||||
|
||||
#define LDST_UNALIGN_MASK 0x0000007f
|
||||
#define UA_LCB 0x00000060
|
||||
#define UA_LCW 0x00000062
|
||||
#define UA_LCE 0x00000066
|
||||
#define UA_SCB 0x00000068
|
||||
#define UA_SCW 0x0000006a
|
||||
#define UA_SCE 0x0000006e
|
||||
#define UA_LL 0x0000000c
|
||||
#define UA_SC 0x0000000e
|
||||
#define LDST16_RR_MASK 0x0000000f
|
||||
#define N16_LW 8
|
||||
#define N16_LH 9
|
||||
#define N16_POP 10
|
||||
#define N16_LBU 11
|
||||
#define N16_SW 12
|
||||
#define N16_SH 13
|
||||
#define N16_PUSH 14
|
||||
#define N16_SB 15
|
||||
#define LDST16_RI_MASK 0x7007
|
||||
#define N16_LWP 0x7000
|
||||
#define N16_LHP 0x7001
|
||||
#define N16_LBUP 0x7003
|
||||
#define N16_SWP 0x7004
|
||||
#define N16_SHP 0x7005
|
||||
#define N16_SBP 0x7007
|
||||
#define N16_LIU 0x5000
|
||||
|
||||
#define OPC_PSEUDOLDST_MASK 0x00000007
|
||||
|
||||
enum
|
||||
{
|
||||
INSN_LW = 0,
|
||||
INSN_LH = 1,
|
||||
INSN_LHU = 2,
|
||||
INSN_LB = 3,
|
||||
INSN_SW = 4,
|
||||
INSN_SH = 5,
|
||||
INSN_LBU = 6,
|
||||
INSN_SB = 7,
|
||||
};
|
||||
|
||||
/* Sub opcdoe opcode. */
|
||||
enum
|
||||
{
|
||||
INSN16_LBU = 11,
|
||||
INSN16_LH = 9,
|
||||
INSN16_LW = 8,
|
||||
INSN16_SB = 15,
|
||||
INSN16_SH = 13,
|
||||
INSN16_SW = 12,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
LDST_NOUPDATE = 0,
|
||||
LDST_PRE = 1,
|
||||
LDST_POST = 2,
|
||||
};
|
||||
|
||||
enum score_insn_type
|
||||
{
|
||||
Rd_I4,
|
||||
Rd_I5,
|
||||
Rd_rvalueBP_I5,
|
||||
Rd_lvalueBP_I5,
|
||||
Rd_Rs_I5,
|
||||
x_Rs_I5,
|
||||
x_I5_x,
|
||||
Rd_I8,
|
||||
Rd_Rs_I14,
|
||||
I15,
|
||||
Rd_I16,
|
||||
Rd_rvalueRs_SI10,
|
||||
Rd_lvalueRs_SI10,
|
||||
Rd_rvalueRs_preSI12,
|
||||
Rd_rvalueRs_postSI12,
|
||||
Rd_lvalueRs_preSI12,
|
||||
Rd_lvalueRs_postSI12,
|
||||
Rd_Rs_SI14,
|
||||
Rd_rvalueRs_SI15,
|
||||
Rd_lvalueRs_SI15,
|
||||
Rd_SI16,
|
||||
PC_DISP8div2,
|
||||
PC_DISP11div2,
|
||||
PC_DISP19div2,
|
||||
PC_DISP24div2,
|
||||
Rd_Rs_Rs,
|
||||
x_Rs_x,
|
||||
x_Rs_Rs,
|
||||
Rd_Rs_x,
|
||||
Rd_x_Rs,
|
||||
Rd_x_x,
|
||||
Rd_Rs,
|
||||
Rd_HighRs,
|
||||
Rd_lvalueRs,
|
||||
Rd_rvalueRs,
|
||||
Rd_lvalue32Rs,
|
||||
Rd_rvalue32Rs,
|
||||
x_Rs,
|
||||
NO_OPD,
|
||||
NO16_OPD,
|
||||
OP5_rvalueRs_SI15,
|
||||
I5_Rs_Rs_I5_OP5,
|
||||
x_rvalueRs_post4,
|
||||
Rd_rvalueRs_post4,
|
||||
Rd_x_I5,
|
||||
Rd_lvalueRs_post4,
|
||||
x_lvalueRs_post4,
|
||||
Rd_LowRs,
|
||||
Rd_Rs_Rs_imm,
|
||||
Insn_Type_PCE,
|
||||
Insn_Type_SYN,
|
||||
Insn_GP,
|
||||
Insn_PIC,
|
||||
};
|
||||
|
||||
enum score_data_type
|
||||
{
|
||||
_IMM4 = 0,
|
||||
_IMM5,
|
||||
_IMM8,
|
||||
_IMM14,
|
||||
_IMM15,
|
||||
_IMM16,
|
||||
_SIMM10 = 6,
|
||||
_SIMM12,
|
||||
_SIMM14,
|
||||
_SIMM15,
|
||||
_SIMM16,
|
||||
_SIMM14_NEG = 11,
|
||||
_IMM16_NEG,
|
||||
_SIMM16_NEG,
|
||||
_IMM20,
|
||||
_IMM25,
|
||||
_DISP8div2 = 16,
|
||||
_DISP11div2,
|
||||
_DISP19div2,
|
||||
_DISP24div2,
|
||||
_VALUE,
|
||||
_VALUE_HI16,
|
||||
_VALUE_LO16,
|
||||
_VALUE_LDST_LO16 = 23,
|
||||
_SIMM16_LA,
|
||||
_IMM5_RSHIFT_1,
|
||||
_IMM5_RSHIFT_2,
|
||||
_SIMM16_LA_POS,
|
||||
_IMM5_RANGE_8_31,
|
||||
_IMM10_RSHIFT_2,
|
||||
_GP_IMM15 = 30,
|
||||
_GP_IMM14 = 31,
|
||||
_SIMM16_pic = 42, /* Index in score_df_range. */
|
||||
_IMM16_LO16_pic = 43,
|
||||
_IMM16_pic = 44,
|
||||
};
|
||||
|
||||
#define REG_TMP 1
|
||||
|
||||
#define OP_REG_TYPE (1 << 6)
|
||||
#define OP_IMM_TYPE (1 << 7)
|
||||
#define OP_SH_REGD (OP_REG_TYPE |20)
|
||||
#define OP_SH_REGS1 (OP_REG_TYPE |15)
|
||||
#define OP_SH_REGS2 (OP_REG_TYPE |10)
|
||||
#define OP_SH_I (OP_IMM_TYPE | 1)
|
||||
#define OP_SH_RI15 (OP_IMM_TYPE | 0)
|
||||
#define OP_SH_I12 (OP_IMM_TYPE | 3)
|
||||
#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
|
||||
#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
|
||||
#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
|
||||
#define OP_SH_I5 (OP_IMM_TYPE |10)
|
||||
#define OP_SH_I10 (OP_IMM_TYPE | 5)
|
||||
#define OP_SH_COPID (OP_IMM_TYPE | 5)
|
||||
#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
|
||||
#define OP_SH_I15 (OP_IMM_TYPE |10)
|
||||
|
||||
#define OP16_SH_REGD (OP_REG_TYPE | 8)
|
||||
#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
|
||||
#define OP16_SH_I45 (OP_IMM_TYPE | 3)
|
||||
#define OP16_SH_I8 (OP_IMM_TYPE | 0)
|
||||
#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
|
||||
#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
|
||||
|
||||
struct datafield_range
|
||||
{
|
||||
int data_type;
|
||||
int bits;
|
||||
int range[2];
|
||||
};
|
||||
|
||||
struct datafield_range score_df_range[] =
|
||||
{
|
||||
{_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
|
||||
{_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
|
||||
{_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
|
||||
{_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
|
||||
{_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
|
||||
{_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
|
||||
{_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
|
||||
{_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
|
||||
{_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
|
||||
{_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
|
||||
{_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
|
||||
{_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
|
||||
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
|
||||
{_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
|
||||
{_IMM20, 20, {0, (1 << 20) - 1}},
|
||||
{_IMM25, 25, {0, (1 << 25) - 1}},
|
||||
{_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
|
||||
{_DISP11div2, 11, {0, 0}},
|
||||
{_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
|
||||
{_DISP24div2, 24, {0, 0}},
|
||||
{_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
|
||||
{_VALUE_HI16, 16, {0, (1 << 16) - 1}},
|
||||
{_VALUE_LO16, 16, {0, (1 << 16) - 1}},
|
||||
{_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
|
||||
{_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
|
||||
{_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
|
||||
{_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
|
||||
{_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
|
||||
{_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
|
||||
{_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
|
||||
{_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
|
||||
{_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
|
||||
{_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
|
||||
{_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
|
||||
{_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
|
||||
{_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
|
||||
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
|
||||
{_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
|
||||
{_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
|
||||
{_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
|
||||
{_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
|
||||
{_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
|
||||
{_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
|
||||
{_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
|
||||
{_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
|
||||
};
|
||||
|
||||
struct shift_bitmask
|
||||
{
|
||||
int opd_type;
|
||||
int opd_num;
|
||||
struct datafield_range *df_range;
|
||||
int sh[4];
|
||||
long fieldbits[4];
|
||||
};
|
||||
|
||||
struct shift_bitmask score_sh_bits_map[] =
|
||||
{
|
||||
{
|
||||
Rd_I4, 2, &score_df_range[_IMM4],
|
||||
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
|
||||
{0xf, 0xf, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_I5, 2, &score_df_range[_IMM5],
|
||||
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
|
||||
{0xf, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
|
||||
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
|
||||
{0xf, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
|
||||
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
|
||||
{0xf, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_Rs_I5, 3, &score_df_range[_IMM5],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
|
||||
{0x1f, 0x1f, 0x1f, 0},
|
||||
},
|
||||
{
|
||||
x_Rs_I5, 2, &score_df_range[_IMM5],
|
||||
{OP_SH_REGS1, OP_SH_I5, 0, 0},
|
||||
{0x1f, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
x_I5_x, 1, &score_df_range[_IMM5],
|
||||
{OP_SH_TRAPI5, 0, 0, 0},
|
||||
{0x1f, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_I8, 2, &score_df_range[_IMM8],
|
||||
{OP16_SH_REGD, OP16_SH_I8, 0, 0},
|
||||
{0xf, 0xff, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_Rs_I14, 3, &score_df_range[_IMM14],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
|
||||
{0x1f, 0x1f, 0x3fff, 0},
|
||||
},
|
||||
{
|
||||
I15, 1, &score_df_range[_IMM15],
|
||||
{OP_SH_I15, 0, 0, 0},
|
||||
{0x7fff, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_I16, 2, &score_df_range[_IMM16],
|
||||
{OP_SH_REGD, OP_SH_I, 0, 0},
|
||||
{0x1f, 0xffff, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
|
||||
{0x1f, 0x1f, 0x3ff, 0},
|
||||
},
|
||||
{
|
||||
Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
|
||||
{0x1f, 0x1f, 0x3ff, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
|
||||
{0xf, 0xf, 0xfff, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
|
||||
{0xf, 0xf, 0xfff, 0},
|
||||
},
|
||||
{
|
||||
Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
|
||||
{0xf, 0xf, 0xfff, 0},
|
||||
},
|
||||
{
|
||||
Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
|
||||
{0xf, 0xf, 0xfff, 0},
|
||||
},
|
||||
{
|
||||
Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
|
||||
{0x1f, 0x1f, 0x3fff, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
|
||||
{0x1f, 0x1f, 0x7fff, 0},
|
||||
},
|
||||
{
|
||||
Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
|
||||
{0x1f, 0x1f, 0x7fff, 0},
|
||||
},
|
||||
{
|
||||
Rd_SI16, 2, &score_df_range[_SIMM16],
|
||||
{OP_SH_REGD, OP_SH_I, 0, 0},
|
||||
{0x1f, 0xffff, 0, 0},
|
||||
},
|
||||
{
|
||||
PC_DISP8div2, 1, &score_df_range[_DISP8div2],
|
||||
{OP16_SH_DISP8, 0, 0, 0},
|
||||
{0xff, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
PC_DISP11div2, 1, &score_df_range[_DISP11div2],
|
||||
{OP16_SH_DISP11, 0, 0, 0},
|
||||
{0x7ff, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
PC_DISP19div2, 2, &score_df_range[_DISP19div2],
|
||||
{OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
|
||||
{0x3ff, 0x1ff, 0, 0},
|
||||
},
|
||||
{
|
||||
PC_DISP24div2, 1, &score_df_range[_DISP24div2],
|
||||
{OP_SH_DISP24, 0, 0, 0},
|
||||
{0xffffff, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_Rs_Rs, 3, NULL,
|
||||
{OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
|
||||
{0x1f, 0x1f, 0x1f, 0}
|
||||
},
|
||||
{
|
||||
Rd_Rs_x, 2, NULL,
|
||||
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
|
||||
{0x1f, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_x_Rs, 2, NULL,
|
||||
{OP_SH_REGD, OP_SH_REGS2, 0, 0},
|
||||
{0x1f, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_x_x, 1, NULL,
|
||||
{OP_SH_REGD, 0, 0, 0},
|
||||
{0x1f, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
x_Rs_Rs, 2, NULL,
|
||||
{OP_SH_REGS1, OP_SH_REGS2, 0, 0},
|
||||
{0x1f, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
x_Rs_x, 1, NULL,
|
||||
{OP_SH_REGS1, 0, 0, 0},
|
||||
{0x1f, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_Rs, 2, NULL,
|
||||
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
|
||||
{0xf, 0xf, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_HighRs, 2, NULL,
|
||||
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
|
||||
{0xf, 0xf, 0x1f, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalueRs, 2, NULL,
|
||||
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
|
||||
{0xf, 0xf, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_lvalueRs, 2, NULL,
|
||||
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
|
||||
{0xf, 0xf, 0, 0}
|
||||
},
|
||||
{
|
||||
Rd_lvalue32Rs, 2, NULL,
|
||||
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
|
||||
{0x1f, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
Rd_rvalue32Rs, 2, NULL,
|
||||
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
|
||||
{0x1f, 0x1f, 0, 0},
|
||||
},
|
||||
{
|
||||
x_Rs, 1, NULL,
|
||||
{OP16_SH_REGS1, 0, 0, 0},
|
||||
{0xf, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
NO_OPD, 0, NULL,
|
||||
{0, 0, 0, 0},
|
||||
{0, 0, 0, 0},
|
||||
},
|
||||
{
|
||||
NO16_OPD, 0, NULL,
|
||||
{0, 0, 0, 0},
|
||||
{0, 0, 0, 0},
|
||||
},
|
||||
};
|
||||
|
||||
struct asm_opcode
|
||||
{
|
||||
/* Instruction name. */
|
||||
const char *template;
|
||||
|
||||
/* Instruction Opcode. */
|
||||
unsigned long value;
|
||||
|
||||
/* Instruction bit mask. */
|
||||
unsigned long bitmask;
|
||||
|
||||
/* Relax instruction opcode. 0x8000 imply no relaxation. */
|
||||
unsigned long relax_value;
|
||||
|
||||
/* Instruction type. */
|
||||
enum score_insn_type type;
|
||||
|
||||
/* Function to call to parse args. */
|
||||
void (*parms) (char *);
|
||||
};
|
||||
|
||||
enum insn_class
|
||||
{
|
||||
INSN_CLASS_16,
|
||||
INSN_CLASS_32,
|
||||
INSN_CLASS_PCE,
|
||||
INSN_CLASS_SYN
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue