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2002-08-19 Elena Zannoni <ezannoni@redhat.com> 

From matthew green  <mrg@redhat.com>

        * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
        instructions.
        (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
        PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
        e500x2 Integer select, branch locking, performance monitor,
        cache locking and machine check APUs, respectively.
        (PPC_OPCODE_EFS): New opcode type for efs* instructions.
        (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
This commit is contained in:
Elena Zannoni 2002-08-19 20:55:48 +00:00
parent 3bacc423cf
commit 8d16a989fb
2 changed files with 37 additions and 0 deletions
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13
include/opcode/ChangeLog
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@ -1,3 +1,16 @@
2002-08-19 Elena Zannoni <ezannoni@redhat.com>
From matthew green <mrg@redhat.com>
* ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
instructions.
(PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
e500x2 Integer select, branch locking, performance monitor,
cache locking and machine check APUs, respectively.
(PPC_OPCODE_EFS): New opcode type for efs* instructions.
(PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
2002-08-13 Stephane Carrez <stcarrez@nerim.fr>
* m68hc11.h (M6812_OP_PAGE): Define to identify call operand.

24
include/opcode/ppc.h
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@ -107,6 +107,30 @@ extern const int powerpc_num_opcodes;
/* Opcode isn't supported by Power4 architecture. */
#define PPC_OPCODE_NOPOWER4 (040000)
/* Opcode is only supported by POWERPC Classic architecture. */
#define PPC_OPCODE_CLASSIC (0100000)
/* Opcode is only supported by e500x2 Core. */
#define PPC_OPCODE_SPE (0200000)
/* Opcode is supported by e500x2 Integer select APU. */
#define PPC_OPCODE_ISEL (0400000)
/* Opcode is an e500 SPE floating point instruction. */
#define PPC_OPCODE_EFS (01000000)
/* Opcode is supported by branch locking APU. */
#define PPC_OPCODE_BRLOCK (02000000)
/* Opcode is supported by performance monitor APU. */
#define PPC_OPCODE_PMR (04000000)
/* Opcode is supported by cache locking APU. */
#define PPC_OPCODE_CACHELCK (010000000)
/* Opcode is supported by machine check APU. */
#define PPC_OPCODE_RFMCI (020000000)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)