include/opcode/
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
This commit is contained in:
Richard Sandiford
parent
4e9c217b55
commit
b1b497cb2e
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@ -1,3 +1,22 @@
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
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(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
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(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
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(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
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(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
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(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
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(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
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(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
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(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
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(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
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(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
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(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
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(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
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Rename to...
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(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
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(M_USD_AB): ...these.
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h: Remove documentation of "[" and "]". Update documentation
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@ -947,8 +947,8 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
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/* This is a list of macro expanded instructions.
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_I appended means immediate
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_A appended means address
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_AB appended means address with base register
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_A appended means target address of a jump
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_AB appended means address with (possibly zero) base register
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_D appended means 64 bit floating point constant
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_S appended means 32 bit floating point constant. */
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@ -956,12 +956,10 @@ enum
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{
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M_ABS,
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M_ACLR_AB,
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M_ACLR_OB,
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M_ADD_I,
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M_ADDU_I,
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M_AND_I,
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M_ASET_AB,
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M_ASET_OB,
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M_BALIGN,
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M_BC1FL,
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M_BC1TL,
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@ -1018,9 +1016,7 @@ enum
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M_BNE_I,
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M_BNEL_I,
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M_CACHE_AB,
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M_CACHE_OB,
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M_CACHEE_AB,
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M_CACHEE_OB,
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M_DABS,
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M_DADD_I,
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M_DADDU_I,
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@ -1059,41 +1055,25 @@ enum
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M_JALS_A,
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M_JRADDIUSP,
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M_JRC,
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M_L_DOB,
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M_L_DAB,
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M_LA_AB,
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M_LB_A,
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M_LB_AB,
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M_LBE_OB,
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M_LBE_AB,
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M_LBU_A,
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M_LBU_AB,
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M_LBUE_OB,
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M_LBUE_AB,
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M_LCA_AB,
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M_LD_A,
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M_LD_OB,
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M_LD_AB,
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M_LDC1_AB,
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M_LDC2_AB,
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M_LDC2_OB,
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M_LQC2_AB,
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M_LDC3_AB,
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M_LDL_AB,
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M_LDL_OB,
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M_LDM_AB,
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M_LDM_OB,
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M_LDP_AB,
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M_LDP_OB,
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M_LDR_AB,
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M_LDR_OB,
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M_LH_A,
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M_LH_AB,
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M_LHE_OB,
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M_LHE_AB,
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M_LHU_A,
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M_LHU_AB,
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M_LHUE_OB,
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M_LHUE_AB,
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M_LI,
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M_LI_D,
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@ -1101,42 +1081,22 @@ enum
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M_LI_S,
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M_LI_SS,
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M_LL_AB,
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M_LL_OB,
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M_LLD_AB,
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M_LLD_OB,
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M_LLE_AB,
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M_LLE_OB,
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M_LQ_AB,
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M_LS_A,
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M_LW_A,
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M_LW_AB,
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M_LWE_OB,
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M_LWE_AB,
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M_LWC0_A,
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M_LWC0_AB,
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M_LWC1_A,
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M_LWC1_AB,
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M_LWC2_A,
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M_LWC2_AB,
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M_LWC2_OB,
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M_LWC3_A,
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M_LWC3_AB,
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M_LWL_A,
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M_LWL_AB,
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M_LWL_OB,
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M_LWLE_AB,
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M_LWLE_OB,
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M_LWM_AB,
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M_LWM_OB,
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M_LWP_AB,
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M_LWP_OB,
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M_LWR_A,
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M_LWR_AB,
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M_LWR_OB,
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M_LWRE_AB,
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M_LWRE_OB,
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M_LWU_AB,
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M_LWU_OB,
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M_MSGSND,
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M_MSGLD,
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M_MSGLD_T,
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@ -1153,9 +1113,7 @@ enum
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M_NOR_I,
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M_OR_I,
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M_PREF_AB,
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M_PREF_OB,
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M_PREFE_AB,
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M_PREFE_OB,
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M_REM_3,
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M_REM_3I,
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M_REMU_3,
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@ -1169,35 +1127,22 @@ enum
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M_DROR_I,
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M_ROR_I,
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M_S_DA,
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M_S_DOB,
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M_S_DAB,
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M_S_S,
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M_SAA_AB,
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M_SAA_OB,
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M_SAAD_AB,
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M_SAAD_OB,
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M_SC_AB,
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M_SC_OB,
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M_SCD_AB,
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M_SCD_OB,
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M_SCE_AB,
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M_SCE_OB,
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M_SD_A,
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M_SD_OB,
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M_SD_AB,
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M_SDC1_AB,
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M_SDC2_AB,
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M_SDC2_OB,
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M_SQC2_AB,
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M_SDC3_AB,
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M_SDL_AB,
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M_SDL_OB,
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M_SDM_AB,
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M_SDM_OB,
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M_SDP_AB,
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M_SDP_OB,
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M_SDR_AB,
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M_SDR_OB,
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M_SEQ,
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M_SEQ_I,
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M_SGE,
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@ -1216,42 +1161,23 @@ enum
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M_SLTU_I,
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M_SNE,
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M_SNE_I,
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M_SB_A,
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M_SB_AB,
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M_SBE_OB,
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M_SBE_AB,
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M_SH_A,
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M_SH_AB,
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M_SHE_OB,
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M_SHE_AB,
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M_SQ_AB,
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M_SW_A,
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M_SW_AB,
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M_SWE_OB,
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M_SWE_AB,
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M_SWC0_A,
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M_SWC0_AB,
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M_SWC1_A,
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M_SWC1_AB,
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M_SWC2_A,
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M_SWC2_AB,
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M_SWC2_OB,
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M_SWC3_A,
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M_SWC3_AB,
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M_SWL_A,
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M_SWL_AB,
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M_SWL_OB,
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M_SWLE_AB,
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M_SWLE_OB,
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M_SWM_AB,
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M_SWM_OB,
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M_SWP_AB,
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M_SWP_OB,
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M_SWR_A,
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M_SWR_AB,
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M_SWR_OB,
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M_SWRE_AB,
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M_SWRE_OB,
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M_SUB_I,
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M_SUBU_I,
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M_SUBU_I_2,
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@ -1263,20 +1189,13 @@ enum
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M_TNE_I,
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M_TRUNCWD,
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M_TRUNCWS,
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M_ULD,
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M_ULD_A,
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M_ULH,
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M_ULH_A,
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M_ULHU,
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M_ULHU_A,
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M_ULW,
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M_ULW_A,
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M_USH,
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M_USH_A,
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M_USW,
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M_USW_A,
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M_USD,
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M_USD_A,
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M_ULD_AB,
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M_ULH_AB,
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M_ULHU_AB,
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M_ULW_AB,
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M_USH_AB,
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M_USW_AB,
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M_USD_AB,
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M_XOR_I,
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M_COP0,
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M_COP1,
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