From b29ef5d944eb77715a1b1b1768a9a0109fe7a600 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Tue, 4 Sep 2012 13:52:04 +0000 Subject: [PATCH] Add Intel Itanium Series 9500 support bfd/ 2012-09-04 Sergey A. Guriev * cpu-ia64-opc.c (ins_cnt6a): New function. (ext_cnt6a): Ditto. (ins_strd5b): Ditto. (ext_strd5b): Ditto. (elf64_ia64_operands): Add new operand types. gas/ 2012-09-04 Sergey A. Guriev * config/tc-ia64.c (reg_symbol): Add a new register. (indirect_reg): Ditto. (pseudo_func): Add new symbolic constants. (operand_match): Add new operand types recognition. (operand_insn): Add new register recognition. (md_begin): Add new register definition. (specify_resource): Add new register recognition. gas/testsuite/ 2012-09-04 Sergey A. Guriev * gas/testsuite/gas/ia64/psn.d: New file. * gas/testsuite/gas/ia64/psn.s: New file. * gas/testsuite/gas/ia64/ia64.exp: Add new testcase. * gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests. * gas/testsuite/gas/ia64/opc-m.d: Ditto. include/opcode/ 2012-09-04 Sergey A. Guriev * ia64.h (ia64_opnd): Add new operand types. opcodes/ 2012-09-04 Sergey A. Guriev * ia64-asmtab.h (completer_index): Extend bitfield to full uint. * ia64-gen.c: Promote completer index type to longlong. (irf_operand): Add new register recognition. (in_iclass_mov_x): Add an entry for the new mov_* instruction type. (lookup_specifier): Add new resource recognition. (insert_bit_table_ent): Relax abort condition according to the changed completer index type. (print_dis_table): Fix printf format for completer index. * ia64-ic.tbl: Add a new instruction class. * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions. * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions. * ia64-opc.h: Define short names for new operand types. * ia64-raw.tbl: Add new RAW resource for DAHR register. * ia64-waw.tbl: Add new WAW resource for DAHR register. * ia64-asmtab.c: Regenerate. --- include/opcode/ChangeLog | 48 ++++++++++++++++++++++------------------ include/opcode/ia64.h | 9 ++++++++ 2 files changed, 35 insertions(+), 22 deletions(-) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index e0b0673be..ce5c71de0 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,22 +1,26 @@ +2012-09-04 Sergey A. Guriev + + * ia64.h (ia64_opnd): Add new operand types. + 2012-08-21 David S. Miller * sparc.h (F3F4): New macro. 2012-08-13 Ian Bolton - Laurent Desnogues - Jim MacArthur - Marcus Shawcroft - Nigel Stephens - Ramana Radhakrishnan - Richard Earnshaw - Sofiane Naci - Tejas Belagod - Yufeng Zhang + Laurent Desnogues + Jim MacArthur + Marcus Shawcroft + Nigel Stephens + Ramana Radhakrishnan + Richard Earnshaw + Sofiane Naci + Tejas Belagod + Yufeng Zhang * aarch64.h: New file. 2012-08-13 Richard Sandiford - Maciej W. Rozycki + Maciej W. Rozycki * mips.h (mips_opcode): Add the exclusions field. (OPCODE_IS_MEMBER): Remove macro. @@ -24,8 +28,8 @@ (opcode_is_member): Likewise. 2012-07-31 Chao-Ying Fu - Catherine Moore - Maciej W. Rozycki + Catherine Moore + Maciej W. Rozycki * mips.h: Document microMIPS DSP ASE usage. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for @@ -110,7 +114,7 @@ (XRELEASE_PREFIX_OPCODE): Likewise. 2011-12-08 Andrew Pinski - Adam Nemet + Adam Nemet * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. @@ -141,7 +145,7 @@ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. 2011-08-09 Chao-ying Fu - Maciej W. Rozycki + Maciej W. Rozycki * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. @@ -187,7 +191,7 @@ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. 2011-07-24 Chao-ying Fu - Maciej W. Rozycki + Maciej W. Rozycki * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. @@ -750,7 +754,7 @@ 2008-11-28 Joshua Kinard * mips.h: Define CPU_R14000, CPU_R16000. - (OPCODE_IS_MEMBER): Include R14000, R16000 in test. + (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 2008-11-18 Catherine Moore @@ -989,9 +993,9 @@ * i386.h: Replace CpuMNI with CpuSSSE3. 2006-09-26 Mark Shinwell - Joseph Myers - Ian Lance Taylor - Ben Elliston + Joseph Myers + Ian Lance Taylor + Ben Elliston * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. @@ -1034,18 +1038,18 @@ * m68k.h (mcf_mask): Define. 2006-05-05 Thiemo Seufer - David Ung + David Ung * mips.h (enum): Add macro M_CACHE_AB. 2006-05-04 Thiemo Seufer - Nigel Stephens + Nigel Stephens David Ung * mips.h: Add INSN_SMARTMIPS define. 2006-04-30 Thiemo Seufer - David Ung + David Ung * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h index 4285377f7..433c5058a 100644 --- a/include/opcode/ia64.h +++ b/include/opcode/ia64.h @@ -91,6 +91,7 @@ enum ia64_opnd IA64_OPND_R2, /* second register # */ IA64_OPND_R3, /* third register # */ IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ /* memory operands: */ IA64_OPND_MR3, /* memory at addr of third register # */ @@ -105,6 +106,7 @@ enum ia64_opnd IA64_OPND_PKR_R3, /* pkr[reg] */ IA64_OPND_PMC_R3, /* pmc[reg] */ IA64_OPND_PMD_R3, /* pmd[reg] */ + IA64_OPND_DAHR_R3, /* dahr[reg] */ IA64_OPND_RR_R3, /* rr[reg] */ /* immediate operands: */ @@ -134,7 +136,9 @@ enum ia64_opnd IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ + IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ + IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ @@ -155,6 +159,9 @@ enum ia64_opnd IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ + IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ + IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ + IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ }; @@ -191,6 +198,7 @@ enum ia64_resource_specifier IA64_RS_CR_IRR, IA64_RS_CR_LRR, IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ + IA64_RS_DAHR, IA64_RS_DBR, IA64_RS_FR, IA64_RS_FRb, @@ -212,6 +220,7 @@ enum ia64_resource_specifier IA64_RS_PSR, /* PSR bits */ IA64_RS_RSE, /* implementation-specific RSE resources */ IA64_RS_AR_FPSR, + }; enum ia64_rse_resource