628 lines
15 KiB
ArmAsm
628 lines
15 KiB
ArmAsm
/*
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* Basic startup code for Blackfin processor
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*
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* Copyright (C) 2008 Analog Devices, Inc.
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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// basic startup code which
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// - turns the cycle counter on
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// - loads up FP & SP (both supervisor and user)
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// - initialises the device drivers (FIOCRT)
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// - calls monstartup to set up the profiling routines (PROFCRT)
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// - calls the C++ startup (CPLUSCRT)
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// - initialises argc/argv (FIOCRT/normal)
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// - calls _main
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// - calls _exit (which calls monexit to dump accumulated prof data (PROFCRT))
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// - defines dummy IO routines (!FIOCRT)
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#include <sys/platform.h>
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#include <cplb.h>
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#include <sys/anomaly_macros_rtl.h>
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#define IVBh (EVT0 >> 16)
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#define IVBl (EVT0 & 0xFFFF)
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#define UNASSIGNED_VAL 0
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#define UNASSIGNED_FILL 0
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// just IVG15
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#define INTERRUPT_BITS 0x400
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#if defined(_ADI_THREADS) || \
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!defined(__ADSPLPBLACKFIN__) || defined(__ADSPBF561__) || defined(__ADSPBF566__)
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#define SET_CLOCK_SPEED 0
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#else
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#define SET_CLOCK_SPEED 1
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#endif
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#if SET_CLOCK_SPEED == 1
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#include <sys/pll.h>
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#define SET_CLK_MSEL 0x16
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#define SET_CLK_DF 0
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#define SET_CLK_LOCK_COUNT 0x300
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#define SET_CLK_CSEL 0
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#define SET_CLK_SSEL 5
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/*
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** CLKIN == 27MHz on the EZ-Kits.
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** D==0 means CLKIN is passed to PLL without dividing.
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** MSEL==0x16 means VCO==27*0x16 == 594MHz
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** CSEL==0 means CCLK==VCO == 594MHz
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** SSEL==5 means SCLK==VCO/5 == 118MHz
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*/
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#endif
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#ifdef __ADSPBF561_COREB__
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.section .b.text,"ax",@progbits
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.align 2;
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.global __coreb_start;
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.type __coreb_start, STT_FUNC;
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__coreb_start:
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#elif defined(__ADSPBF60x_CORE1__)
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.section .1.text,"ax",@progbits
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.align 2;
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.global __core1_start;
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.type __core1_start, STT_FUNC;
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__core1_start:
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#else
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.text;
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.align 2;
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.global __start;
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.type __start, STT_FUNC;
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__start:
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#endif
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#if WA_05000109
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// Avoid Anomaly ID 05000109.
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# define SYSCFG_VALUE 0x30
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R1 = SYSCFG_VALUE;
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SYSCFG = R1;
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#endif
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#if WA_05000229
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// Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset.
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R1 = 0x400;
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#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
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P0.L = SPI0_CTL & 0xFFFF;
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P0.H = SPI0_CTL >> 16;
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W[P0] = R1.L;
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#else
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P0.L = SPI_CTL & 0xFFFF;
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P0.H = SPI_CTL >> 16;
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W[P0] = R1.L;
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#endif
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P0.L = DMA5_CONFIG & 0xFFFF;
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P0.H = DMA5_CONFIG >> 16;
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R1 = 0;
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W[P0] = R1.L;
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#endif
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// Zap loop counters to zero, to make sure that
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// hw loops are disabled - it could be really baffling
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// if the counters and bottom regs are set, and we happen
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// to run into them.
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R7 = 0;
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LC0 = R7;
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LC1 = R7;
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// Clear the DAG Length regs too, so that it's safe to
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// use I-regs without them wrapping around.
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L0 = R7;
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L1 = R7;
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L2 = R7;
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L3 = R7;
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// Zero ITEST_COMMAND and DTEST_COMMAND
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// (in case they have crud in them and
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// does a write somewhere when we enable cache)
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I0.L = (ITEST_COMMAND & 0xFFFF);
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I0.H = (ITEST_COMMAND >> 16);
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I1.L = (DTEST_COMMAND & 0xFFFF);
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I1.H = (DTEST_COMMAND >> 16);
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R7 = 0;
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[I0] = R7;
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[I1] = R7;
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// It seems writing ITEST_COMMAND from SDRAM with icache enabled
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// needs SSYNC.
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#ifdef __BFIN_SDRAM
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SSYNC;
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#else
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CSYNC;
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#endif
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// Initialise the Event Vector table.
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P0.H = IVBh;
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P0.L = IVBl;
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// Install __unknown_exception_occurred in EVT so that
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// there is defined behaviour.
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P0 += 2*4; // Skip Emulation and Reset
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P1 = 13;
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R1.L = __unknown_exception_occurred;
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R1.H = __unknown_exception_occurred;
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LSETUP (L$ivt,L$ivt) LC0 = P1;
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L$ivt: [P0++] = R1;
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// Set IVG15's handler to be the start of the mode-change
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// code. Then, before we return from the Reset back to user
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// mode, we'll raise IVG15. This will mean we stay in supervisor
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// mode, and continue from the mode-change point., but at a
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// much lower priority.
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P1.H = L$supervisor_mode;
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P1.L = L$supervisor_mode;
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[P0] = P1;
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// Initialise the stack.
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// Note: this points just past the end of the section.
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// First write should be with [--SP].
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#ifdef __BFIN_SDRAM
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SP.L = __end + 0x400000 - 12;
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SP.H = __end + 0x400000 - 12;
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#else
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#ifdef __ADSPBF561_COREB__
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SP.L=__coreb_stack_end - 12;
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SP.H=__coreb_stack_end - 12;
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#elif defined(__ADSPBF60x_CORE1__)
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SP.L=__core1_stack_end - 12;
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SP.H=__core1_stack_end - 12;
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#else
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SP.L=__stack_end - 12;
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SP.H=__stack_end - 12;
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#endif
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#endif
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usp = sp;
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// We're still in supervisor mode at the moment, so the FP
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// needs to point to the supervisor stack.
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FP = SP;
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// And make space for incoming "parameters" for functions
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// we call from here:
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SP += -12;
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// Zero out bss section
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#ifdef __BFIN_SDRAM
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R0.L = ___bss_start;
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R0.H = ___bss_start;
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R1.L = __end;
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R1.H = __end;
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#else
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#ifdef __ADSPBF561_COREB__
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R0.L = __coreb_bss_start;
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R0.H = __coreb_bss_start;
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R1.L = __coreb_bss_end;
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R1.H = __coreb_bss_end;
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#elif defined(__ADSPBF60x_CORE1__)
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R0.L = __core1_bss_start;
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R0.H = __core1_bss_start;
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R1.L = __core1_bss_end;
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R1.H = __core1_bss_end;
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#else
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R0.L = __bss_start;
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R0.H = __bss_start;
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R1.L = __bss_end;
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R1.H = __bss_end;
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#endif
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#endif
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R2 = R1 - R0;
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R1 = 0;
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#ifdef __ADSPBF561_COREB__
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CALL.X __coreb_memset;
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#elif defined(__ADSPBF60x_CORE1__)
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CALL.X __core1_memset;
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#else
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CALL.X _memset;
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#endif
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R0 = INTERRUPT_BITS;
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R0 <<= 5; // Bits 0-4 not settable.
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// CALL.X __install_default_handlers;
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R4 = R0; // Save modified list
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R0 = SYSCFG; // Enable the Cycle counter
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BITSET(R0,1);
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SYSCFG = R0;
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#if WA_05000137
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// Avoid anomaly #05000137
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// Set the port preferences of DAG0 and DAG1 to be
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// different; this gives better performance when
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// performing dual-dag operations on SDRAM.
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P0.L = DMEM_CONTROL & 0xFFFF;
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P0.H = DMEM_CONTROL >> 16;
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R0 = [P0];
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BITSET(R0, 12);
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BITCLR(R0, 13);
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[P0] = R0;
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CSYNC;
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#endif
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// Reinitialise data areas in RAM from ROM, if MemInit's
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// been used.
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// CALL.X _mi_initialize;
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#if defined(__ADSPLPBLACKFIN__)
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#if SET_CLOCK_SPEED == 1
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#if 0
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// Check if this feature is enabled, i.e. ___clk_ctrl is defined to non-zero
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P0.L = ___clk_ctrl;
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P0.H = ___clk_ctrl;
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R0 = MAX_IN_STARTUP;
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R1 = [P0];
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R0 = R0 - R1;
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CC = R0;
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IF CC JUMP L$clock_is_set;
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#endif
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// Investigate whether we are a suitable revision
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// for boosting the system clocks.
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// speed.
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P0.L = DSPID & 0xFFFF;
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P0.H = DSPID >> 16;
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R0 = [P0];
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R0 = R0.L (Z);
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CC = R0 < 2;
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IF CC JUMP L$clock_is_set;
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// Set the internal Voltage-Controlled Oscillator (VCO)
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R0 = SET_CLK_MSEL (Z);
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R1 = SET_CLK_DF (Z);
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R2 = SET_CLK_LOCK_COUNT (Z);
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CALL.X __pll_set_system_vco;
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// Set the Core and System clocks
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R0 = SET_CLK_CSEL (Z);
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R1 = SET_CLK_SSEL (Z);
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CALL.X __pll_set_system_clocks;
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L$clock_is_set:
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#endif
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#endif /* ADSPLPBLACKFIN */
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#if defined(__ADSPBF561__) || defined(__ADSPBF566__) || defined(__ADSPBF606__) || defined(__ADSPBF607__) || defined(__ADSPBF608__) || defined(__ADSPBF609__)
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// Initialise the multi-core data tables.
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// A dummy function will be called if we are not linking with
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// -multicore
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// CALL.X __mc_data_initialise;
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#endif
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#if 0
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// Write the cplb exception handler to the EVT if approprate and
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// initialise the CPLBs if they're needed. couldn't do
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// this before we set up the stacks.
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P2.H = ___cplb_ctrl;
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P2.L = ___cplb_ctrl;
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R0 = CPLB_ENABLE_ANY_CPLBS;
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R6 = [P2];
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R0 = R0 & R6;
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CC = R0;
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IF !CC JUMP L$no_cplbs;
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#if !defined(_ADI_THREADS)
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P1.H = __cplb_hdr;
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P1.L = __cplb_hdr;
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P0.H = IVBh;
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P0.L = IVBl;
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[P0+12] = P1; // write exception handler
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#endif /* _ADI_THREADS */
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R0 = R6;
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CALL.X __cplb_init;
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#endif
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L$no_cplbs:
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// Enable interrupts
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STI R4; // Using the mask from default handlers
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RAISE 15;
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// Move the processor into user mode.
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P0.L=L$still_interrupt_in_ipend;
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P0.H=L$still_interrupt_in_ipend;
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RETI=P0;
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L$still_interrupt_in_ipend:
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rti; // keep doing 'rti' until we've 'finished' servicing all
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// interrupts of priority higher than IVG15. Normally one
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// would expect to only have the reset interrupt in IPEND
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// being serviced, but occasionally when debugging this may
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// not be the case - if restart is hit when servicing an
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// interrupt.
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//
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// When we clear all bits from IPEND, we'll enter user mode,
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// then we'll automatically jump to supervisor_mode to start
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// servicing IVG15 (which we will 'service' for the whole
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// program, so that the program is in supervisor mode.
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//
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// Need to do this to 'finish' servicing the reset interupt.
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L$supervisor_mode:
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[--SP] = RETI; // re-enables the interrupt system
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R0.L = UNASSIGNED_VAL;
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R0.H = UNASSIGNED_VAL;
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#if UNASSIGNED_FILL
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R2=R0;
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R3=R0;
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R4=R0;
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R5=R0;
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R6=R0;
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R7=R0;
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P0=R0;
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P1=R0;
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P2=R0;
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P3=R0;
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P4=R0;
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P5=R0;
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#endif
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// Push a RETS and Old FP onto the stack, for sanity.
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[--SP]=R0;
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[--SP]=R0;
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// Make sure the FP is sensible.
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FP = SP;
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// And leave space for incoming "parameters"
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SP += -12;
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#ifdef PROFCRT
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CALL.X monstartup; // initialise profiling routines
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#endif /* PROFCRT */
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#if !defined(__ADSPBF561_COREB__) && !defined(__ADSPBF60x_CORE1__)
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CALL.X __init;
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R0.L = __fini;
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R0.H = __fini;
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CALL.X _atexit;
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#endif
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#if !defined(_ADI_THREADS)
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#ifdef FIOCRT
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// FILE IO provides access to real command-line arguments.
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CALL.X __getargv;
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r1.l=__Argv;
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r1.h=__Argv;
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#else
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// Default to having no arguments and a null list.
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R0=0;
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#ifdef __ADSPBF561_COREB__
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R1.L=L$argv_coreb;
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R1.H=L$argv_coreb;
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#elif defined(__ADSPBF60x_CORE1__)
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R1.L=L$argv_core1;
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R1.H=L$argv_core1;
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#else
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R1.L=L$argv;
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R1.H=L$argv;
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#endif
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#endif /* FIOCRT */
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#endif /* _ADI_THREADS */
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// At long last, call the application program.
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#ifdef __ADSPBF561_COREB__
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CALL.X _coreb_main;
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#elif defined(__ADSPBF60x_CORE1__)
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CALL.X _core1_main;
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#else
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CALL.X _main;
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#endif
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#if !defined(_ADI_THREADS)
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#if !defined(__ADSPBF561_COREB__) && !defined(__ADSPBF60x_CORE1__)
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CALL.X _exit; // passing in main's return value
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#endif
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#endif
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#ifdef __ADSPBF561_COREB__
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.size __coreb_start, .-__coreb_start
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#elif defined(__ADSPBF60x_CORE1__)
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.size __core1_start, .-__core1_start
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#else
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.size __start, .-__start
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#endif
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.align 2
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.type __unknown_exception_occurred, STT_FUNC;
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__unknown_exception_occurred:
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// This function is invoked by the default exception
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// handler, if it does not recognise the kind of
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// exception that has occurred. In other words, the
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// default handler only handles some of the system's
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// exception types, and it does not expect any others
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// to occur. If your application is going to be using
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// other kinds of exceptions, you must replace the
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// default handler with your own, that handles all the
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// exceptions you will use.
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//
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// Since there's nothing we can do, we just loop here
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// at what we hope is a suitably informative label.
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IDLE;
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CSYNC;
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JUMP __unknown_exception_occurred;
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RTS;
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.size __unknown_exception_occurred, .-__unknown_exception_occurred
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#if defined(__ADSPLPBLACKFIN__)
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#if SET_CLOCK_SPEED == 1
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/*
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** CLKIN == 27MHz on the EZ-Kits.
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** D==0 means CLKIN is passed to PLL without dividing.
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** MSEL==0x16 means VCO==27*0x16 == 594MHz
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** CSEL==0 means CCLK==VCO == 594MHz
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** SSEL==5 means SCLK==VCO/5 == 118MHz
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*/
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// int pll_set_system_clocks(int csel, int ssel)
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// returns 0 for success, -1 for error.
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.align 2
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.type __pll_set_system_clocks, STT_FUNC;
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__pll_set_system_clocks:
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P0.H = PLL_DIV >> 16;
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P0.L = PLL_DIV & 0xFFFF;
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R2 = W[P0] (Z);
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// Plant CSEL and SSEL
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R0 <<= 16;
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R0.L = (4 << 8) | 2; // 2 bits, at posn 4
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R1 <<= 16;
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R1.L = 4; // 4 bits, at posn 0
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R2 = DEPOSIT(R2, R0);
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#if defined(__WORKAROUND_DREG_COMP_LATENCY)
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// Work around anomaly 05-00-0209 which affects the DEPOSIT
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// instruction (and the EXTRACT, SIGNBITS, and EXPADJ instructions)
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// if the previous instruction created any of its operands
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NOP;
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#endif
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R2 = DEPOSIT(R2, R1);
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W[P0] = R2;
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SSYNC;
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RTS;
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.size __pll_set_system_clocks, .-__pll_set_system_clocks
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// int pll_set_system_vco(int msel, int df, lockcnt)
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.align 2
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.type __pll_set_system_vco, STT_FUNC;
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__pll_set_system_vco:
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P0.H = PLL_CTL >> 16;
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P0.L = PLL_CTL & 0xFFFF;
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R3 = W[P0] (Z);
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P2 = R3; // Save copy
|
|
R3 >>= 1; // Drop old DF
|
|
R1 = ROT R1 BY -1; // Move DF into CC
|
|
R3 = ROT R3 BY 1; // and into ctl space.
|
|
R0 <<= 16; // Set up pattern reg
|
|
R0.L = (9<<8) | 6; // (6 bits at posn 9)
|
|
R1 = P2; // Get the old version
|
|
R3 = DEPOSIT(R3, R0);
|
|
CC = R1 == R3; // and if we haven't changed
|
|
IF CC JUMP L$done; // Anything, return
|
|
|
|
CC = R2 == 0; // Use default lockcount if
|
|
IF CC JUMP L$wakeup; // user one is zero.
|
|
P2.H = PLL_LOCKCNT >> 16;
|
|
P2.L = PLL_LOCKCNT & 0xFFFF;
|
|
W[P2] = R2; // Set the lock counter
|
|
L$wakeup:
|
|
P2.H = SIC_IWR >> 16;
|
|
P2.L = SIC_IWR & 0xFFFF;
|
|
R2 = [P2];
|
|
BITSET(R2, 0); // enable PLL Wakeup
|
|
[P2] = R2;
|
|
|
|
W[P0] = R3; // Update PLL_CTL
|
|
SSYNC;
|
|
|
|
CLI R2; // Avoid unnecessary interrupts
|
|
IDLE; // Wait until PLL has locked
|
|
STI R2; // Restore interrupts.
|
|
|
|
L$done:
|
|
RTS;
|
|
.size __pll_set_system_vco, .-__pll_set_system_vco
|
|
#endif
|
|
#endif /* ADSPLPBLACKFIN */
|
|
|
|
#if defined(__ADSPBF561_COREB__) || defined(__ADSPBF60x_CORE1__)
|
|
#ifdef __ADSPBF561_COREB__
|
|
.section .b.text,"ax",@progbits
|
|
.type __coreb_memset, STT_FUNC
|
|
__coreb_memset:
|
|
#else
|
|
.section .1.text,"ax",@progbits
|
|
.type __core1_memset, STT_FUNC
|
|
__core1_memset:
|
|
#endif
|
|
P0 = R0 ; /* P0 = address */
|
|
P2 = R2 ; /* P2 = count */
|
|
R3 = R0 + R2; /* end */
|
|
CC = R2 <= 7(IU);
|
|
IF CC JUMP .Ltoo_small;
|
|
R1 = R1.B (Z); /* R1 = fill char */
|
|
R2 = 3;
|
|
R2 = R0 & R2; /* addr bottom two bits */
|
|
CC = R2 == 0; /* AZ set if zero. */
|
|
IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
|
|
|
|
.Laligned:
|
|
P1 = P2 >> 2; /* count = n/4 */
|
|
R2 = R1 << 8; /* create quad filler */
|
|
R2.L = R2.L + R1.L(NS);
|
|
R2.H = R2.L + R1.H(NS);
|
|
P2 = R3;
|
|
|
|
LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
|
|
.Lquad_loop:
|
|
[P0++] = R2;
|
|
|
|
CC = P0 == P2;
|
|
IF !CC JUMP .Lbytes_left;
|
|
RTS;
|
|
|
|
.Lbytes_left:
|
|
R2 = R3; /* end point */
|
|
R3 = P0; /* current position */
|
|
R2 = R2 - R3; /* bytes left */
|
|
P2 = R2;
|
|
|
|
.Ltoo_small:
|
|
CC = P2 == 0; /* Check zero count */
|
|
IF CC JUMP .Lfinished; /* Unusual */
|
|
|
|
.Lbytes:
|
|
LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
|
|
.Lbyte_loop:
|
|
B[P0++] = R1;
|
|
|
|
.Lfinished:
|
|
RTS;
|
|
|
|
.Lforce_align:
|
|
CC = BITTST (R0, 0); /* odd byte */
|
|
R0 = 4;
|
|
R0 = R0 - R2;
|
|
P1 = R0;
|
|
R0 = P0; /* Recover return address */
|
|
IF !CC JUMP .Lskip1;
|
|
B[P0++] = R1;
|
|
.Lskip1:
|
|
CC = R2 <= 2; /* 2 bytes */
|
|
P2 -= P1; /* reduce count */
|
|
IF !CC JUMP .Laligned;
|
|
B[P0++] = R1;
|
|
B[P0++] = R1;
|
|
JUMP .Laligned;
|
|
#ifdef __ADSPBF561_COREB__
|
|
.size __coreb_memset,.-__coreb_memset
|
|
#else
|
|
.size __core1_memset,.-__core1_memset
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef __ADSPBF561_COREB__
|
|
.section .b.bss,"aw",@progbits
|
|
.align 4
|
|
.type L$argv_coreb, @object
|
|
.size L$argv_coreb, 4
|
|
L$argv_coreb:
|
|
.zero 4
|
|
#elif defined(__ADSPBF60x_CORE1__)
|
|
.section .1.bss,"aw",@progbits
|
|
.align 4
|
|
.type L$argv_core1, @object
|
|
.size L$argv_core1, 4
|
|
L$argv_core1:
|
|
.zero 4
|
|
#else
|
|
.local L$argv
|
|
.comm L$argv,4,4
|
|
#endif
|
|
|