78 lines
2.7 KiB
C
78 lines
2.7 KiB
C
/* Copyright (c) 2017 SiFive Inc. All rights reserved.
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This copyrighted material is made available to anyone wishing to use,
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modify, copy, or redistribute it subject to the terms and conditions
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of the BSD License. This program is distributed in the hope that
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it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
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including the implied warranties of MERCHANTABILITY or FITNESS FOR
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A PARTICULAR PURPOSE. A copy of this license is available at
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http://www.opensource.org/licenses.
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*/
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#ifndef _FENV_H_
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#define _FENV_H_
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#include <stddef.h>
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/* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA:
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* Version 2.1", Section 8.2, "Floating-Point Control and Status
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* Register":
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*
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* Flag Mnemonic Flag Meaning
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* ------------- -----------------
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* NV Invalid Operation
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* DZ Divide by Zero
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* OF Overflow
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* UF Underflow
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* NX Inexact
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*/
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#define FE_INVALID 0x00000010
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#define FE_DIVBYZERO 0x00000008
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#define FE_OVERFLOW 0x00000004
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#define FE_UNDERFLOW 0x00000002
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#define FE_INEXACT 0x00000001
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#define FE_ALL_EXCEPT (FE_INVALID|FE_DIVBYZERO|FE_OVERFLOW|FE_UNDERFLOW|FE_INEXACT)
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/* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA:
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* Version 2.1", Section 8.2, "Floating-Point Control and Status
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* Register":
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*
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* Rounding Mode Mnemonic Meaning Meaning
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* ------------- ---------------- -------
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* 000 RNE Round to Nearest, ties to Even
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* 001 RTZ Round towards Zero
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* 010 RDN Round Down (towards −∞)
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* 011 RUP Round Up (towards +∞)
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* 100 RMM Round to Nearest, ties to Max Magnitude
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* 101 Invalid. Reserved for future use.
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* 110 Invalid. Reserved for future use.
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* 111 In instruction’s rm field, selects dynamic rounding mode;
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* In Rounding Mode register, Invalid
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*/
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#define FE_TONEAREST_MM 0x00000004
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#define FE_UPWARD 0x00000003
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#define FE_DOWNWARD 0x00000002
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#define FE_TOWARDZERO 0x00000001
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#define FE_TONEAREST 0x00000000
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#define FE_RMODE_MASK 0x7
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/* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA:
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* Version 2.1":
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*
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* "The F extension adds 32 floating-point registers, f0–f31, each 32
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* bits wide, and a floating-point control and status register fcsr,
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* which contains the operating mode and exception status of the
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* floating-point unit."
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*/
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typedef size_t fenv_t;
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typedef size_t fexcept_t;
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extern const fenv_t fe_dfl_env;
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#define FE_DFL_ENV fe_dfl_env_p
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#endif /* _FENV_H_ */
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