121 lines
3.4 KiB
ArmAsm
121 lines
3.4 KiB
ArmAsm
/*
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Copyright (c) 2015, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This implementation is optimized for performance. For code size a generic
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implementation of this function from newlib/libc/string/strcpy.c will be
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used. */
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#if !defined (__OPTIMIZE_SIZE__) && !defined (PREFER_SIZE_OVER_SPEED)
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#include "asm.h"
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#if defined (__ARC600__) && defined (__Xbarrel_shifter)
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/* If dst and src are 4 byte aligned, copy 8 bytes at a time.
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If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
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it 8 byte aligned. Thus, we can do a little read-ahead, without
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dereferencing a cache line that we should not touch.
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Note that short and long instructions have been scheduled to avoid
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branch stalls.
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This version is optimized for the ARC600 pipeline. */
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ENTRY (strcpy)
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or r2,r0,r1
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bmsk.f 0,r2,1
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mov r8,0x01010101
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bne.d .Lcharloop
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mov_s r10,r0
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ld_l r3,[r1,0]
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bbit0.d r1,2,.Loop_setup
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ror r12,r8
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sub r2,r3,r8
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bic_s r2,r2,r3
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and_s r2,r2,r12
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brne_s r2,0,.Lr3z
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st.ab r3,[r10,4]
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ld.a r3,[r1,4]
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.Loop_setup:
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ld.a r4,[r1,4]
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sub r2,r3,r8
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and.f r2,r2,r12
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sub r5,r4,r8
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and.eq.f r5,r5,r12
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b.d .Loop_start
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mov_s r6,r3
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.balign 4
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.Loop:
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ld.a r3,[r1,4]
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st r4,[r10,4]
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ld.a r4,[r1,4]
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sub r2,r3,r8
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and.f r2,r2,r12
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sub r5,r4,r8
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and.eq.f r5,r5,r12
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st.ab r6,[r10,8]
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mov r6,r3
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.Loop_start:
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beq.d .Loop
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bic_s r2,r2,r3
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brne.d r2,0,.Lr3z
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and r5,r5,r12
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bic r5,r5,r4
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breq.d r5,0,.Loop
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mov_s r3,r4
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st.ab r6,[r10,4]
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#ifdef __LITTLE_ENDIAN__
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.Lr3z: bmsk.f r1,r3,7
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.Lr3z_loop:
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lsr_s r3,r3,8
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stb.ab r1,[r10,1]
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bne.d .Lr3z_loop
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bmsk.f r1,r3,7
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j_s [blink]
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#else
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.Lr3z: lsr.f r1,r3,24
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.Lr3z_loop:
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asl_s r3,r3,8
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stb.ab r1,[r10,1]
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bne.d .Lr3z_loop
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lsr.f r1,r3,24
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j_s [blink]
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#endif
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.balign 4
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.Lcharloop:
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ldb.ab r3,[r1,1]
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brne.d r3,0,.Lcharloop
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stb.ab r3,[r10,1]
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j [blink]
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ENDFUNC (strcpy)
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#endif /* __ARC600__ && __Xbarrel_shifter */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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