forked from Lephenixnoir/gint
391 lines
9.3 KiB
C
391 lines
9.3 KiB
C
//---
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// gint:core:intc - Interrupt Controller
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//
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// The interrupt controller is unwieldy because SH7705 and SH7305 have a
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// completely different interface. Everything here is split up and you'll
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// have to explicitly handle both to be able to use the device.
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//
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// gint's API provides higher-level and platform-agnostic interrupt
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// management. This is probably what you are looking for.
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//---
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#ifndef GINT_CORE_INTC
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#define GINT_CORE_INTC
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#include <defs/types.h>
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//---
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// SH7705 Interrupt Controller. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 6: "Interrupt Controller (INTC)"
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//---
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/* sh7705_intc_ipc_t - Interrupt Priority Controller
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A set of 16-bit register that control the interrupt priorities. The SH7705's
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IPC has its registers scattered everywhere in the memory, so there is a
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pointer for each register. The SH7305 needs only one pointer for the whole
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IPC because the registers are in a contiguous area. */
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typedef struct
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{
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volatile word_union(*IPRA,
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uint TMU0 :4; /* Timer 0 */
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uint TMU1 :4; /* Timer 1 */
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uint TMU2 :4; /* Timer 2 */
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uint RTC :4; /* Real-Time Clock */
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);
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volatile word_union(*IPRB,
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uint WDT :4; /* Watchdog Timer */
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uint REF :4; /* BSC Refresh Request, SDRAM (?) */
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uint :4;
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uint :4;
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);
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volatile word_union(*IPRC,
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uint IRQ3 :4; /* Interrupt request 3 */
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uint IRQ2 :4; /* Interrupt request 2 */
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uint IRQ1 :4; /* Interrupt request 1 */
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uint IRQ0 :4; /* Interrupt request 0 */
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);
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volatile word_union(*IPRD,
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uint PINT0_7 :4; /* External interrupt pins 0 to 7 */
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uint PINT8_15 :4; /* External interrupt pins 8 to 15 */
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uint IRQ5 :4; /* Interrupt request 5 */
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uint IRQ4 :4; /* Interrupt request 4 */
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);
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volatile word_union(*IPRE,
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uint DMAC :4; /* Direct Memory Access Controller */
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uint SCIF0 :4; /* Serial Communication Interface 0 */
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uint SCIF2 :4; /* Serial Communication Interface 2 */
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uint ADC :4; /* Analog/Decimal Converter */
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);
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volatile word_union(*IPRF,
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uint :4;
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uint :4;
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uint USB :4; /* USB Controller */
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uint :4;
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);
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volatile word_union(*IPRG,
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uint TPU0 :4; /* Timer Pulse Unit 0 */
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uint TPU1 :4; /* Timer Pulse Unit 1 */
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uint :4;
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uint :4;
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);
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volatile word_union(*IPRH,
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uint TPU2 :4; /* Timer Pulse Unit 2 */
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uint TPU3 :4; /* Timer Pulse Unit 3 */
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uint :4;
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uint :4;
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);
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} PACKED(4) sh7705_intc_ipc_t;
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/* sh7705_intc_icr1_t - Interrupt Control Register 1 (general) */
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typedef word_union(sh7705_intc_icr1_t,
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uint MAI :1; /* Mask All Interrupts */
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uint IRQLVL :1; /* Interrupt Request Level Detect */
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uint BLMSK :1; /* Enable NMI when BL is set */
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uint :1;
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uint IRQ5E :2; /* IRQ 5 Edge Detection */
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uint IRQ4E :2; /* etc. */
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uint IRQ3E :2;
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uint IRQ2E :2;
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uint IRQ1E :2;
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uint IRQ0E :2;
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);
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/* sh7705_intc_t - the SH7705 interrupt controller */
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typedef struct
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{
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/* All interrupt priority registers */
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union {
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sh7705_intc_ipc_t _;
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volatile uint16_t *IPRS[8];
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} PACKED(4);
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/* Control registers */
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volatile sh7705_intc_icr1_t *ICR1;
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} PACKED(4) sh7705_intc_t;
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//---
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// SH7305 Interrupt Controller. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 13: "Interrupt Controller (INTC)"
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//---
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/* sh7305_intc_ipc_t - Interrupt Priority Controller
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Some of the fields have been left unnamed because they correspond to SH7724
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peripheral modules that are *very* unlikely to even exist in the SH7305, let
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alone by of any use to us */
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typedef struct
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{
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word_union(IPRA,
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uint TMU0_0 :4; /* TMU0 Channel 0 */
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uint TMU0_1 :4; /* TMU0 Channel 1 */
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uint TMU0_2 :4; /* TMU0 Channel 2 */
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uint IrDA :4; /* Infrared Communication */
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);
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pad(2);
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word_union(IPRB,
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uint :4; /* JPEG Processing Unit */
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uint LCDC :4; /* LCD Controller */
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uint DMAC1A :4; /* Direct Memory Access Controller 1 */
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uint :4; /* Blending Engine Unit */
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);
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pad(2);
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word_union(IPRC,
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uint TMU1_0 :4; /* TMU1 Channel 0 */
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uint TMU1_1 :4; /* TMU1 Channel 1 */
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uint TMU1_2 :4; /* TMU1 Channel 2 */
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uint :4; /* Sound Processing Unit */
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);
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pad(2);
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word_union(IPRD,
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uint :4;
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uint MMCIF :4; /* MultiMedia Card Interface */
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uint :4;
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uint :4; /* ATAPI Interface */
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);
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pad(2);
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word_union(IPRE,
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uint DMAC0A :4; /* Direct Memory Access Controller 0 */
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uint :4; /* Various graphical engines */
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uint SCIFA3 :4; /* SCIFA channel 3 interrupt */
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uint :4; /* Video Processing Unit */
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);
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pad(2);
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word_union(IPRF,
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uint KEYSC :4; /* Key Scan Interface */
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uint DMACOB :4; /* DMAC0 transfer/error info */
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uint USB0_1 :4; /* USB controller */
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uint CMT :4; /* Compare Match Timer */
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);
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pad(2);
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word_union(IPRG,
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uint SCIF0 :4; /* SCIF0 transfer/error info */
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uint SCIF1 :4; /* SCIF1 transfer/error info */
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uint SCIF2 :4; /* SCIF2 transfer/error info */
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uint :4; /* Video Engine Unit */
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);
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pad(2);
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word_union(IPRH,
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uint MSIOF0 :4; /* Clock-synchronized SCIF channel 0 */
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uint MSIOF1 :4; /* Clock-synchronized SCIF channel 1 */
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uint :4; /* I2C Interface channel 0 */
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uint :4; /* I2C Interface channel 1 */
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);
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pad(2);
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word_union(IPRI,
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uint SCIFA4 :4; /* SCIFA channel 4 interrupt */
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uint :4; /* MediaRAM InterConnected Buffers */
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uint :4; /* Transport Stream Interface */
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uint :4; /* 2D Graphics Accelerator & ICB */
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);
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pad(2);
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word_union(IPRJ,
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uint :4; /* Capture Engine Unit */
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uint :4; /* Ethernet Memory Access Controller */
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uint FSI :4; /* FIFO-Buffered Serial Interface */
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uint SDHI1 :4; /* SD Card Host Interface channel 1 */
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);
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pad(2);
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word_union(IPRK,
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uint RTC :4; /* Real-Time Clock */
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uint DMAC1B :4; /* DMAC1 transfer/error info */
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uint :4; /* MediaRAM InterConnected Buffers */
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uint SDHI0 :4; /* SD Card Host Interface channel 0 */
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);
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pad(2);
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word_union(IPRL,
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uint SCIFA5 :4; /* SCIFA channel 5 interrupt */
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uint :4;
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uint TPU :4; /* Timer-Pulse Unit */
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uint :4; /* Image Extraction DMAC */
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);
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pad(2);
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} PACKED(4) sh7305_intc_ipc_t;
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/* sh7305_intc_masks_t - Interrupt mask management
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Writing 1 to IMR masks interrupts; writing 1 to IMCRs clears the masks.
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Writing 0 is ignored; reading from IMCRs yields undefined values */
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typedef struct
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{
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byte_union(IMR0,
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uint :1;
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uint TUNI1_2 :1; /* TMU1 overflow interrupts */
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uint TUNI1_1 :1;
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uint TUNI1_0 :1;
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uint SDHII3 :1; /* SD Card Host 1 interrupts */
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uint SDHII2 :1;
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uint SDHII1 :1;
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uint SDHII0 :1;
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);
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pad(3);
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byte_union(IMR1,
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uint :4;
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uint DEI3 :1; /* DMAC0A interrupts */
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uint DEI2 :1;
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uint DEI1 :1;
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uint DEI0 :1;
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);
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pad(3);
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byte_union(IMR2,
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uint :7;
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uint SCIFA0 :1; /* Asynchronous Serial interrupts */
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);
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pad(3);
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byte_union(IMR3,
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uint DEI3 :1; /* DMAC1A interrupts */
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uint DEI2 :1;
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uint DEI1 :1;
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uint DEI0 :1;
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uint :4;
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);
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pad(3);
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byte_union(IMR4,
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uint :1;
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uint TUNI0_2 :1; /* TMU0 overflow interrupts */
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uint TUNI0_1 :1;
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uint TUNI0_0 :1;
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uint :3;
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uint LCDCI :1; /* LCD Controller Interrupt */
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);
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pad(3);
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byte_union(IMR5,
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uint KEYI :1; /* Key Interface */
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uint DADERR :1; /* DMAC0B interrupts */
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uint DEI5 :1;
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uint DEI4 :1;
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uint :1;
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uint SCIF2 :1; /* Serial Communication Interface */
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uint SCIF1 :1;
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uint SCIF0 :1;
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);
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pad(3);
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byte_union(IMR6,
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uint :2;
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uint :1;
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uint SCIFA4 :1; /* SCIFA4 interrupt */
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uint :1;
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uint :1;
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uint MSIOFI0 :1; /* Clock-synchronized SCIF channel 0 */
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uint MSIOFI1 :1; /* Clock-synchronized SCIF channel 1 */
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);
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pad(3);
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uint8_t IMR7;
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pad(3);
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byte_union(IMR8,
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uint SDHII3 :1; /* SD Card Host 0 interrupts */
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uint SDHII2 :1;
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uint SDHII1 :1;
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uint SDHII0 :1;
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uint :2;
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uint SCFIA5 :1; /* SCIFA5 interrupt */
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uint FSI :1; /* FIFO-Buffered Serial Interface */
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);
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pad(3);
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byte_union(IMR9,
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uint :3;
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uint CMTI :1; /* Compare Match Timer Interrupt */
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uint :1;
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uint USI1 :1; /* USB1 */
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uint USI0 :1; /* USB0 */
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uint :1;
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);
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pad(3);
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byte_union(IMR10,
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uint :1;
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uint DADERR :1; /* DMAC1B interrupts */
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uint DEI5 :1;
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uint DEI4 :1;
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uint :1;
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uint ATI :1; /* RTC Alarm interrupt */
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uint PRI :1; /* RTC Periodic interrupt */
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uint CUI :1; /* RTC Carry interrupt */
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);
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pad(3);
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byte_union(IMR11,
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uint :5;
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uint TPUI :1; /* Timer-Pulse Unit */
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uint :2;
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);
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pad(3);
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uint8_t IMR12;
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} PACKED(4) sh7305_intc_masks_t;
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/* sh7305_intc_userimask_t - User Interrupt Mask
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Sets the minimum required level for interrupts to be accepted.
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WARNING: Writing to this register is only allowed when the upper bits of the
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operand (ie. the new value of USERIMASK) are 0xa5; otherwise, the write is
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ignored. To modify the value of this register, do not access the bit field
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directly, backup the variable and modify it:
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void set_user_imask(int new_level)
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{
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sh7305_intc_userimask_t mask = *(INTC._7305.USERIMASK);
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mask._0xa5 = 0xa5;
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mask.UIMASK = new_level & 0x0f;
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*(INTC._7305.USERIMASK) = mask;
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}
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*/
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typedef lword_union(sh7305_intc_userimask_t,
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uint _0xa5 :8; /* Always set to 0xa5 before writing */
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uint :16;
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uint UIMASK :4; /* User Interrupt Mask Level */
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uint :4;
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);
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/* sh7305_intc_t - the SH7305 interrupt controller */
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typedef struct
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{
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/* Interrupt priority registers */
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union {
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volatile sh7305_intc_ipc_t *_;
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volatile uint16_t *IPRS;
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};
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/* Interrupt mask & mask clear registers */
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volatile sh7305_intc_masks_t *MSK;
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volatile sh7305_intc_masks_t *MSKCLR;
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/* Other registers */
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volatile sh7305_intc_userimask_t *USERIMASK;
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} PACKED(4) sh7305_intc_t;
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#endif /* GINT_CORE_INTC */
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