diff --git a/CMakeLists.txt b/CMakeLists.txt
index 3309375..71a21e3 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -11,6 +11,7 @@ find_package(Gint 2.1 REQUIRED)
set(SOURCES
src/main.c
+ src/clock.c
# ...
)
# Shared assets, fx-9860G-only assets and fx-CG-50-only assets
diff --git a/Demo.cbp b/Demo.cbp
index 16ba8c0..620c1fe 100644
--- a/Demo.cbp
+++ b/Demo.cbp
@@ -11,10 +11,17 @@
+
+
+
+
+
+
+
diff --git a/Demo.layout b/Demo.layout
index eea4e49..a70778b 100644
--- a/Demo.layout
+++ b/Demo.layout
@@ -2,19 +2,19 @@
-
+
-
+
+
+
+
+
+
-
-
-
-
-
-
+
diff --git a/src/clock.c b/src/clock.c
new file mode 100644
index 0000000..caa7f93
--- /dev/null
+++ b/src/clock.c
@@ -0,0 +1,304 @@
+#include "clock.h"
+#include
+#include
+
+#define FLLFRQ_default 0x00004384
+#define FRQCR_default 0x0F011112
+
+#define CS0BCR_default 0x36DA0400 // CG50
+#define CS2BCR_default 0x36DA3400 // CG50
+#define CS3BCR_default 0x36DB4400 // CG50
+#define CS4BCR_default 0x36DB0400
+#define CS5aBCR_default 0x17DF0400
+#define CS5bBCR_default 0x17DF0400
+#define CS6aBCR_default 0x34D30200
+#define CS6bBCR_default 0x34D30200
+
+#define CS0WCR_default 0x000003C0 // CG50
+#define CS2WCR_default 0x000003C0 // CG50
+#define CS3WCR_default 0x000024D1 // CG50
+#define CS4WCR_default 0x00000540
+#define CS5aWCR_default 0x000203C1
+#define CS5bWCR_default 0x000203C1
+#define CS6aWCR_default 0x000302C0
+#define CS6bWCR_default 0x000302C0
+#define SDCR_default 0x00000A08
+
+#define PLL_32x 0b011111 //
+#define PLL_26x 0b011001 //
+#define PLL_16x 0b001111 // default
+
+#define DIV_2 0b0000 // 1/2
+#define DIV_4 0b0001 // 1/4
+#define DIV_8 0b0010 // 1/8
+#define DIV16 0b0011 // 1/16
+
+#define SLYDEBUG 0
+
+#if (SLYDEBUG==1)
+ #include
+ #include
+#endif
+
+
+struct st_cpg {
+ union { // struct FRQCRA similar to SH7724
+ unsigned long LONG; // long Word Access
+ struct { // Bit Access
+ unsigned long KICK :1; // KICK
+ unsigned long :1; //
+ unsigned long STC :6; // STC
+ unsigned long IFC :4; // IFC
+ unsigned long :4; //
+ unsigned long SFC :4; // SFC
+ unsigned long BFC :4; // BFC
+ unsigned long :4; //
+ unsigned long PFC :4; // PFC
+ } BIT;
+ } FRQCRA;
+
+ unsigned long FRQCRB; // 0xA41500004
+ unsigned long FCLKACR; // 0xA41500008
+ unsigned long FCLKBCR; // 0xA4150000C
+ unsigned long unknownA41500010;
+ unsigned long unknownA41500014;
+ unsigned long IRDACLKCR; // 0xA41500018
+ unsigned long unknownA4150001C;
+ unsigned long unknownA41500020;
+ unsigned long PLLCR; // 0xA41500024
+ unsigned long unknownA41500028;
+ unsigned long unknownA4150002C;
+ unsigned long unknownA41500030;
+ unsigned long unknownA41500034;
+ unsigned long unknownA41500038;
+ unsigned long SPUCLKCR; // 0xA4150003C
+ unsigned long unknownA41500040;
+ unsigned long unknownA41500044;
+ unsigned long VCLKCR; // 0xA41500048
+ unsigned long unknownA4150004C;
+
+ union { // struct FLLFRQ similar to SH7724
+ unsigned long LONG; // long Word Access
+ struct { // Bit Access
+ unsigned long :16; //
+ unsigned long SELXM:2; // SELXM
+ unsigned long :3; //
+ unsigned long FLF :11; // FLF
+ } BIT;
+ } FLLFRQ;
+
+ unsigned long unknownA41500054;
+ unsigned long unknownA41500058;
+ unsigned long unknownA4150005C;
+ unsigned long LSTATS;
+};
+
+#define CPG (*(volatile struct st_cpg *)0xA4150000)
+
+
+uint32_t *FRQCR = (uint32_t*)0xA4150000;
+//uint32_t *FSICLKCR = (uint32_t*)0xA4150008;
+//uint32_t *DDCLRCR = (uint32_t*)0xA4150010;
+//uint32_t *USBCLKCR = (uint32_t*)0xA4150014;
+//uint32_t *PLL1CR = (uint32_t*)0xA4150024;
+//uint32_t *PLL2CR = (uint32_t*)0xA4150028;
+//uint32_t *SPUCLKCR = (uint32_t*)0xA415003C;
+//uint32_t *SSCGCR = (uint32_t*)0xA4150044;
+uint32_t *FLLFRQ = (uint32_t*)0xA4150050;
+//uint32_t *LSTATS = (uint32_t*)0xA4150060;
+
+//uint32_t *CMNCR = (uint32_t*)0xFEC10000;
+uint32_t *CS0BCR = (uint32_t*)0xFEC10004;
+uint32_t *CS2BCR = (uint32_t*)0xFEC10008;
+uint32_t *CS3BCR = (uint32_t*)0xFEC1000C;
+uint32_t *CS4BCR = (uint32_t*)0xFEC10010;
+uint32_t *CS5ABCR = (uint32_t*)0xFEC10014;
+uint32_t *CS5BBCR = (uint32_t*)0xFEC10018;
+uint32_t *CS6ABCR = (uint32_t*)0xFEC1001C;
+uint32_t *CS6BBCR = (uint32_t*)0xFEC10020;
+uint32_t *CS0WCR = (uint32_t*)0xFEC10024;
+uint32_t *CS2WCR = (uint32_t*)0xFEC10028;
+uint32_t *CS3WCR = (uint32_t*)0xFEC1002C;
+uint32_t *CS4WCR = (uint32_t*)0xFEC10030;
+uint32_t *CS5AWCR = (uint32_t*)0xFEC10034;
+uint32_t *CS5BWCR = (uint32_t*)0xFEC10038;
+uint32_t *CS6AWCR = (uint32_t*)0xFEC1003C;
+uint32_t *CS6BWCR = (uint32_t*)0xFEC10040;
+uint32_t *SDCR = (uint32_t*)0xFEC10044;
+uint32_t *RTCSR = (uint32_t*)0xFEC10048;
+uint32_t *RTCNT = (uint32_t*)0xFEC1004C;
+uint32_t *RTCOR = (uint32_t*)0xFEC10050;
+
+uint8_t *SDMR2 = (uint8_t*)0xFEC14000;
+uint8_t *SDMR3 = (uint8_t*)0xFEC15000;
+
+
+uint32_t SaveDataF0_FLLFRQ=FLLFRQ_default; // FLL:900 default
+uint32_t SaveDataF0_FRQCR =FRQCR_default; // PLL:x16 IFC:1/2 SFC:1/4 BFC:1/4 PFC:1/8
+uint32_t SaveDataF0_CS0BCR=CS0BCR_default; // IWW:4 IWRRS:4
+uint32_t SaveDataF0_CS2BCR=CS2BCR_default; // IWW:4 IWRRS:4
+uint32_t SaveDataF0_CS0WCR=CS0WCR_default; // wait:8
+uint32_t SaveDataF0_CS2WCR=CS2WCR_default; //
+uint32_t SaveDataF0_CS3BCR=CS3BCR_default; // IWW:4 IWRRS:4
+uint32_t SaveDataF0_CS3WCR=CS3WCR_default; // CL:2
+uint32_t SaveDataF0_CS5aBCR=CS5aBCR_default; //
+uint32_t SaveDataF0_CS5aWCR=CS5aWCR_default; //
+
+uint32_t SaveDataF2_FLLFRQ=0x00004000+900; // FLL:900 59MHz like CG10/20
+uint32_t SaveDataF2_FRQCR =(PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
+uint32_t SaveDataF2_CS0BCR=0x24920400; // IWW:2 IWRRS:2
+uint32_t SaveDataF2_CS2BCR=0x24923400; // IWW:2 IWRRS:2
+uint32_t SaveDataF2_CS0WCR=0x00000340; // wait:6
+uint32_t SaveDataF2_CS2WCR=CS2WCR_default; //
+uint32_t SaveDataF2_CS3BCR=0x24924400; // IWW:2 IWRRS:2
+uint32_t SaveDataF2_CS3WCR=CS3WCR_default; // CL:2
+uint32_t SaveDataF2_CS5aBCR=CS5aBCR_default; //
+uint32_t SaveDataF2_CS5aWCR=CS5aWCR_default; //
+
+uint32_t SaveDataF3_FLLFRQ=0x00004000+900; // FLL:900 95.8MHz
+uint32_t SaveDataF3_FRQCR =(PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
+uint32_t SaveDataF3_CS0BCR=0x24920400; // IWW:2 IWRRS:2
+uint32_t SaveDataF3_CS2BCR=0x24923400; // IWW:2 IWRRS:2
+uint32_t SaveDataF3_CS0WCR=0x00000240; // wait:4
+uint32_t SaveDataF3_CS2WCR=CS2WCR_default; //
+uint32_t SaveDataF3_CS3BCR=0x24924400; // IWW:2 IWRRS:2
+uint32_t SaveDataF3_CS3WCR=CS3WCR_default; // CL:2
+uint32_t SaveDataF3_CS5aBCR=CS5aBCR_default; //
+uint32_t SaveDataF3_CS5aWCR=CS5aWCR_default; //
+
+uint32_t SaveDataF4_FLLFRQ=0x00004000+900; // FLL:900 236MHz
+uint32_t SaveDataF4_FRQCR =(PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16;
+uint32_t SaveDataF4_CS0BCR=0x24920400; // IWW:2 IWRRS:2
+uint32_t SaveDataF4_CS2BCR=0x24923400; // IWW:2 IWRRS:2
+uint32_t SaveDataF4_CS0WCR=0x000002C0; // wait:5
+uint32_t SaveDataF4_CS2WCR=CS2WCR_default; //
+uint32_t SaveDataF4_CS3BCR=0x24924400; // IWW:2 IWRRS:2
+uint32_t SaveDataF4_CS3WCR=CS3WCR_default; // CL:2
+uint32_t SaveDataF4_CS5aBCR=CS5aBCR_default; //
+uint32_t SaveDataF4_CS5aWCR=CS5aWCR_default; //
+
+uint32_t SaveDataF5_FLLFRQ=0x00004000+900; // FLL:900 191MHz
+uint32_t SaveDataF5_FRQCR =(PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8;
+uint32_t SaveDataF5_CS0BCR=0x24920400; // IWW:2 IWRRS:2
+uint32_t SaveDataF5_CS2BCR=0x24923400; // IWW:2 IWRRS:2
+uint32_t SaveDataF5_CS0WCR=0x00000440; // wait:10
+uint32_t SaveDataF5_CS2WCR=CS2WCR_default; //
+uint32_t SaveDataF5_CS3BCR=0x24924400; // IWW:2 IWRRS:2
+uint32_t SaveDataF5_CS3WCR=CS3WCR_default; // CL:2
+uint32_t SaveDataF5_CS5aBCR=CS5aBCR_default; //
+uint32_t SaveDataF5_CS5aWCR=CS5aWCR_default; //
+
+
+void SetOCDefault( void )
+{
+ FLLFRQ[0] = SaveDataF0_FLLFRQ;
+ FRQCR[0] = SaveDataF0_FRQCR;
+ CS0BCR[0] = SaveDataF0_CS0BCR;
+ CS0WCR[0] = SaveDataF0_CS0WCR;
+ CS2BCR[0] = SaveDataF0_CS2BCR;
+ CS2WCR[0] = SaveDataF0_CS2WCR;
+ CS3BCR[0] = SaveDataF0_CS3BCR;
+ CS3WCR[0] = SaveDataF0_CS3WCR;
+ CS5ABCR[0] = SaveDataF0_CS5aBCR;
+ CS5AWCR[0] = SaveDataF0_CS5aWCR;
+
+ #if (SLYDEBUG==1)
+ if (usb_is_open()) usb_fxlink_text("MODE OC_Normal SET", 0);
+ #endif // SLYDEBUG
+}
+
+void SetOCPtuneF2( void )
+{
+ FLLFRQ[0] = SaveDataF2_FLLFRQ;
+ FRQCR[0] = SaveDataF2_FRQCR;
+ CS0BCR[0] = SaveDataF2_CS0BCR;
+ CS0WCR[0] = SaveDataF2_CS0WCR;
+ CS2BCR[0] = SaveDataF2_CS2BCR;
+ CS2WCR[0] = SaveDataF2_CS2WCR;
+ CS3BCR[0] = SaveDataF2_CS3BCR;
+ CS3WCR[0] = SaveDataF2_CS3WCR;
+ CS5ABCR[0] = SaveDataF2_CS5aBCR;
+ CS5AWCR[0] = SaveDataF2_CS5aWCR;
+
+ #if (SLYDEBUG==1)
+ if (usb_is_open()) usb_fxlink_text("MODE PTune_F2 SET", 0);
+ #endif // SLYDEBUG
+}
+
+void SetOCPtuneF3( void )
+{
+ FLLFRQ[0] = SaveDataF3_FLLFRQ;
+ FRQCR[0] = SaveDataF3_FRQCR;
+ CS0BCR[0] = SaveDataF3_CS0BCR;
+ CS0WCR[0] = SaveDataF3_CS0WCR;
+ CS2BCR[0] = SaveDataF3_CS2BCR;
+ CS2WCR[0] = SaveDataF3_CS2WCR;
+ CS3BCR[0] = SaveDataF3_CS3BCR;
+ CS3WCR[0] = SaveDataF3_CS3WCR;
+ CS5ABCR[0] = SaveDataF3_CS5aBCR;
+ CS5AWCR[0] = SaveDataF3_CS5aWCR;
+
+ #if (SLYDEBUG==1)
+ if (usb_is_open()) usb_fxlink_text("MODE PTune_F3 SET", 0);
+ #endif // SLYDEBUG
+}
+
+void SetOCPtuneF4( void )
+{
+ FLLFRQ[0] = SaveDataF4_FLLFRQ;
+ FRQCR[0] = SaveDataF4_FRQCR;
+ CS0BCR[0] = SaveDataF4_CS0BCR;
+ CS0WCR[0] = SaveDataF4_CS0WCR;
+ CS2BCR[0] = SaveDataF4_CS2BCR;
+ CS2WCR[0] = SaveDataF4_CS2WCR;
+ CS3BCR[0] = SaveDataF4_CS3BCR;
+ CS3WCR[0] = SaveDataF4_CS3WCR;
+ CS5ABCR[0] = SaveDataF4_CS5aBCR;
+ CS5AWCR[0] = SaveDataF4_CS5aWCR;
+
+ #if (SLYDEBUG==1)
+ if (usb_is_open()) usb_fxlink_text("MODE PTune_F4 SET", 0);
+ #endif // SLYDEBUG
+}
+
+void SetOCPtuneF5( void )
+{
+ FLLFRQ[0] = SaveDataF5_FLLFRQ;
+ FRQCR[0] = SaveDataF5_FRQCR;
+ CS0BCR[0] = SaveDataF5_CS0BCR;
+ CS0WCR[0] = SaveDataF5_CS0WCR;
+ CS2BCR[0] = SaveDataF5_CS2BCR;
+ CS2WCR[0] = SaveDataF5_CS2WCR;
+ CS3BCR[0] = SaveDataF5_CS3BCR;
+ CS3WCR[0] = SaveDataF5_CS3WCR;
+ CS5ABCR[0] = SaveDataF5_CS5aBCR;
+ CS5AWCR[0] = SaveDataF5_CS5aWCR;
+
+ #if (SLYDEBUG==1)
+ if (usb_is_open()) usb_fxlink_text("MODE PTune_F5 SET", 0);
+ #endif // SLYDEBUG
+}
+
+
+void clock_overclock( overclock_level level )
+{
+ if(gint[HWCALC] == HWCALC_FXCG50)
+ {
+ #if (SLYDEBUG==1)
+ if (usb_is_open()) usb_fxlink_text("HARDWARE OK", 0);
+ #endif // SLYDEBUG
+
+ if (level == OC_Default) SetOCDefault();
+ else if (level == OC_PtuneF2) SetOCPtuneF2();
+ else if (level == OC_PtuneF3) SetOCPtuneF3();
+ else if (level == OC_PtuneF4) SetOCPtuneF4();
+ else if (level == OC_PtuneF5) SetOCPtuneF5();
+ else SetOCDefault();
+
+
+
+ CPG.FRQCRA.BIT.KICK = 1 ;
+ while((CPG.LSTATS & 1)!=0);
+ }
+ else return;
+}
diff --git a/src/clock.h b/src/clock.h
new file mode 100644
index 0000000..38095db
--- /dev/null
+++ b/src/clock.h
@@ -0,0 +1,17 @@
+#ifndef CLOCK_H
+#define CLOCK_H
+
+typedef enum
+{
+ OC_Default = 0, // Default (118MHz)
+ OC_PtuneF2 = 1, // 59MHz
+ OC_PtuneF3 = 2, // 96MHz
+ OC_PtuneF4 = 3, // 236MHz
+ OC_PtuneF5 = 4 // 191MHz
+} overclock_level;
+
+
+void clock_overclock( overclock_level level );
+
+
+#endif // CLOCK_H
diff --git a/src/main.c b/src/main.c
index 1a3ce20..87ff692 100644
--- a/src/main.c
+++ b/src/main.c
@@ -14,6 +14,8 @@
#define MAXHEIGHT 200
+#include "clock.h"
+
bool stop = false;
bool skip_intro = false;
@@ -1184,16 +1186,26 @@ static void get_minimum_inputs( void )
if(keydown(KEY_7)) screenshot = true;
if(keydown(KEY_8)) record = !record;
+
+ /// TEST OC
+
+ if (keydown(KEY_1)) clock_overclock( OC_Default );
+ if (keydown(KEY_2)) clock_overclock( OC_PtuneF2 );
+ if (keydown(KEY_3)) clock_overclock( OC_PtuneF3 );
+ if (keydown(KEY_4)) clock_overclock( OC_PtuneF4 );
+ if (keydown(KEY_5)) clock_overclock( OC_PtuneF5 );
}
int main(void)
{
-
usb_interface_t const *interfaces[] = { &usb_ff_bulk, NULL };
usb_open(interfaces, GINT_CALL_NULL);
+ /// TEST OC
+ clock_overclock( OC_Default );
+
srand( rtc_ticks() );
size_t size = image_size_profile( 2, DWIDTH, MAXHEIGHT);
@@ -1265,6 +1277,9 @@ int main(void)
get_minimum_inputs();
}
+ /// TEST OC
+ clock_overclock( OC_Default );
+
//free( screen );
return 1;
}