diff --git a/src/clock.c b/src/clock.c
index 2792e2b..77cfeb9 100644
--- a/src/clock.c
+++ b/src/clock.c
@@ -37,9 +37,12 @@
 #define DIV_8 0b0010	// 1/8
 #define DIV16 0b0011	// 1/16
 
+#define WAIT18 0b1011
+
 #define CPG SH7305_CPG
 #define BSC SH7305_BSC
-
+#define SDMR3_CL2    *(volatile uint8_t *)0xFEC15040    // SDMR2    Address
+#define SDMR3_CL3    *(volatile uint8_t *)0xFEC15060    // SDMR2    Address
 
 static overclock_level current_clock_state = OC_Default;
 bool overclock_config_changed = false;
@@ -47,50 +50,84 @@ bool overclock_config_changed = false;
 
 void SetOCDefault( void )
 {
+    BSC.CS0WCR.WR = WAIT18;
+
     CPG.FLLFRQ.lword  = FLLFRQ_default;
     CPG.FRQCR.lword  = FRQCR_default;
+
+    CPG.FRQCR.KICK = 1 ;
+    while((CPG.LSTATS & 1)!=0)
+
     BSC.CS0BCR.lword  = CS0BCR_default;
     BSC.CS0WCR.lword  = CS0WCR_default;
     BSC.CS2BCR.lword  = CS2BCR_default;
     BSC.CS2WCR.lword  = CS2WCR_default;
     BSC.CS3BCR.lword  = CS3BCR_default;
     BSC.CS3WCR.lword  = CS3WCR_default;
+
+    if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
+
     BSC.CS5ABCR.lword = CS5aBCR_default;
     BSC.CS5AWCR.lword = CS5aWCR_default;
 }
 
 void SetOCPtuneF2( void )
 {
+    BSC.CS0WCR.WR = WAIT18;
+
     CPG.FLLFRQ.lword  = 0x00004000+900;
     CPG.FRQCR.lword  = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
+
+    CPG.FRQCR.KICK = 1 ;
+    while((CPG.LSTATS & 1)!=0)
+
     BSC.CS0BCR.lword  = 0x24920400;
     BSC.CS0WCR.lword  = 0x00000340;
     BSC.CS2BCR.lword  = 0x24923400;
     BSC.CS2WCR.lword  = CS2WCR_default;
     BSC.CS3BCR.lword  = 0x24924400;
     BSC.CS3WCR.lword  = CS3WCR_default;
+
+    if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
+
     BSC.CS5ABCR.lword = CS5aBCR_default;
     BSC.CS5AWCR.lword = CS5aWCR_default;
 }
 
 void SetOCPtuneF3( void )
 {
+    BSC.CS0WCR.WR = WAIT18;
+
     CPG.FLLFRQ.lword  = 0x00004000+900;
     CPG.FRQCR.lword  = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
+
+    CPG.FRQCR.KICK = 1 ;
+    while((CPG.LSTATS & 1)!=0)
+
     BSC.CS0BCR.lword  = 0x24920400;
     BSC.CS0WCR.lword  = 0x00000240;
     BSC.CS2BCR.lword  = 0x24923400;
     BSC.CS2WCR.lword  = CS2WCR_default;
     BSC.CS3BCR.lword  = 0x24924400;
     BSC.CS3WCR.lword  = CS3WCR_default;
+
+    if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
+
     BSC.CS5ABCR.lword = CS5aBCR_default;
     BSC.CS5AWCR.lword = CS5aWCR_default;
 }
 
 void SetOCPtuneF4( void )
 {
+    BSC.CS0WCR.WR = WAIT18;
+
     CPG.FLLFRQ.lword  = 0x00004000+900;
     CPG.FRQCR.lword  = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16;
+
+    CPG.FRQCR.KICK = 1 ;
+    while((CPG.LSTATS & 1)!=0)
+
+
     BSC.CS0BCR.lword  = 0x24920400;
     BSC.CS0WCR.lword  = 0x000002C0;
     BSC.CS2BCR.lword  = 0x24923400;
@@ -103,14 +140,23 @@ void SetOCPtuneF4( void )
 
 void SetOCPtuneF5( void )
 {
+    BSC.CS0WCR.WR = WAIT18;
+
     CPG.FLLFRQ.lword  = 0x00004000+900;
     CPG.FRQCR.lword  = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8;
+
+    CPG.FRQCR.KICK = 1 ;
+    while((CPG.LSTATS & 1)!=0)
+
     BSC.CS0BCR.lword  = 0x24920400;
     BSC.CS0WCR.lword  = 0x00000440;
     BSC.CS2BCR.lword  = 0x24923400;
     BSC.CS2WCR.lword  = CS2WCR_default;
     BSC.CS3BCR.lword  = 0x24924400;
     BSC.CS3WCR.lword  = CS3WCR_default;
+
+    if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
+
     BSC.CS5ABCR.lword = CS5aBCR_default;
     BSC.CS5AWCR.lword = CS5aWCR_default;
 }
@@ -133,18 +179,19 @@ int clock_overclock( overclock_level level )
         if (level == OC_PtuneF3 && current_clock_state!=OC_PtuneF3)    SetOCPtuneF3(), current_clock_state= OC_PtuneF3, overclock_config_changed=true;
         if (level == OC_PtuneF4 && current_clock_state!=OC_PtuneF4)    SetOCPtuneF4(), current_clock_state= OC_PtuneF4, overclock_config_changed=true;
         if (level == OC_PtuneF5 && current_clock_state!=OC_PtuneF5)    SetOCPtuneF5(), current_clock_state= OC_PtuneF5, overclock_config_changed=true;
-
+/*
         if (overclock_config_changed==true)
         {
             CPG.FRQCR.KICK = 1 ;
             while((CPG.LSTATS & 1)!=0 && count<=1000)
             { count++; }
         }
-
+*/
         cpu_atomic_end();
 
-        if (count >= 1000) return -1;
-        else return 1;
+//        if (count >= 1000) return -1;
+//        else return 1;
+        return 1;
     }
     else return 0;
 }