Added the overclock_detect() function
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cce51954c2
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37
Demo.layout
37
Demo.layout
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@ -2,6 +2,16 @@
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@ -12,19 +22,24 @@
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74
src/clock.c
74
src/clock.c
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@ -260,6 +260,9 @@ void SetOCPtuneF4_CG50( void )
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BSC.CS2WCR.lword = CS2WCR_default_CG50;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default_CG50;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG50;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG50;
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}
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@ -405,6 +408,75 @@ void SetOCPtuneF5_CG10_20( void )
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overclock_level overclock_detect( void )
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{
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if(gint[HWCALC] == HWCALC_FXCG50)
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{
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// OC_Default configuration
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if (CPG.FLLFRQ.lword == FLLFRQ_default_CG50 && CPG.FRQCR.lword == FRQCR_default_CG50 && BSC.CS0BCR.lword == CS0BCR_default_CG50 && BSC.CS0WCR.lword == CS0WCR_default_CG50 &&
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BSC.CS2BCR.lword == CS2BCR_default_CG50 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == CS3BCR_default_CG50 && BSC.CS3WCR.lword == CS3WCR_default_CG50 &&
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BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50 ) return OC_Default;
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// OC_PtuneF2 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 &&
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BSC.CS0WCR.lword == 0x00000340 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50 ) return OC_PtuneF2;
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// OC_PtuneF3 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 &&
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BSC.CS0WCR.lword == 0x00000240 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF3;
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// OC_PtuneF4 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16 && BSC.CS0BCR.lword == 0x24920400 &&
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BSC.CS0WCR.lword == 0x000002C0 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF4;
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// OC_PtuneF5 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 &&
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BSC.CS0WCR.lword == 0x00000440 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF5;
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// Not recognized
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else return OC_Undefined;
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}
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else if(gint[HWCALC] == HWCALC_PRIZM)
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{
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// OC_Default configuration
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if (CPG.FLLFRQ.lword == FLLFRQ_default_CG10_20 && CPG.FRQCR.lword == FRQCR_default_CG10_20 && BSC.CS0BCR.lword == CS0BCR_default_CG10_20 && BSC.CS0WCR.lword == CS0WCR_default_CG10_20 &&
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BSC.CS2BCR.lword == CS2BCR_default_CG10_20 && BSC.CS2WCR.lword == CS2WCR_default_CG10_20 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && BSC.CS3WCR.lword == CS3WCR_default_CG10_20 &&
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BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_Default;
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// OC_PtuneF2 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_8<<20)+(DIV16<<12)+(DIV16<<8)+DIV32 && BSC.CS0BCR.lword == 0x04900400 &&
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BSC.CS0WCR.lword == 0x00000140 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000100C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF2;
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// OC_PtuneF3 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV32 && BSC.CS0BCR.lword == 0x24900400 &&
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BSC.CS0WCR.lword == 0x000002C0 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000201C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF3;
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// OC_PtuneF4 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV32 && BSC.CS0BCR.lword == 0x44900400 &&
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BSC.CS0WCR.lword == 0x00000440 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x00040340 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF4;
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// OC_PtuneF5 configuration
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else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV16 && BSC.CS0BCR.lword == 0x34900400 &&
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BSC.CS0WCR.lword == 0x000003C0 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000402C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
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BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20) return OC_PtuneF5;
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// Not recognized
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else return OC_Undefined;
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}
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}
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// return 0 if no need to change
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// return 1 if successful change
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// return -1 on error
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@ -413,6 +485,8 @@ int clock_overclock( overclock_level level )
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{
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uint32_t count=0;
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if (level==OC_Undefined) return 0;
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if(gint[HWCALC] == HWCALC_FXCG50 && current_clock_state!=level)
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{
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cpu_atomic_start();
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@ -8,6 +8,7 @@ extern "C" {
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typedef enum
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{
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OC_Undefined = -1, // Mode not recognized as a PTune/FTune configuration (i.e. certainly a user-defined mode)
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OC_Default = 0, // Default (118MHz)
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OC_PtuneF2 = 1, // 59MHz
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OC_PtuneF3 = 2, // 96MHz
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@ -22,6 +23,7 @@ typedef enum
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int clock_overclock( overclock_level level );
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overclock_level overclock_detect( void );
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#ifdef __cplusplus
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}
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@ -1217,6 +1217,8 @@ int main(void)
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uint32_t time_render = 0;
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float dt = 1.0;
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overclock_level EntryLevel; // we Store the initial OC_Level when entering the Addin
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EntryLevel = overclock_detect();
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/// TEST OC
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clock_overclock( OC_Default );
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@ -1284,6 +1286,8 @@ int main(void)
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dprint(1,1, C_WHITE, "FPS %.0f", (float) (1000.0f/dt) );
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dprint(1,15, C_WHITE, "OC STAT %d", valueOC );
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dprint(1, 50, C_WHITE, "Addin OC Entry Level : %d", EntryLevel );
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dprint(1,75, C_WHITE, "Current OC Level : %d", overclock_detect() );
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dupdate();
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@ -1305,7 +1309,8 @@ int main(void)
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}
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/// TEST OC
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clock_overclock( OC_Default );
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if (EntryLevel!=OC_Undefined) clock_overclock(EntryLevel); // if we were able to recognised the initial level, we set it back
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else clock_overclock( OC_Default ); // if not, we return to Normal mode
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prof_quit();
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