diff --git a/Demo.layout b/Demo.layout index dc9b5bd..d54e8e9 100644 --- a/Demo.layout +++ b/Demo.layout @@ -2,6 +2,16 @@ + + + + + + + + + + @@ -12,19 +22,24 @@ - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/src/clock.c b/src/clock.c index 749f3d4..2bef86f 100644 --- a/src/clock.c +++ b/src/clock.c @@ -260,6 +260,9 @@ void SetOCPtuneF4_CG50( void ) BSC.CS2WCR.lword = CS2WCR_default_CG50; BSC.CS3BCR.lword = 0x24924400; BSC.CS3WCR.lword = CS3WCR_default_CG50; + + if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0; + BSC.CS5ABCR.lword = CS5aBCR_default_CG50; BSC.CS5AWCR.lword = CS5aWCR_default_CG50; } @@ -405,6 +408,75 @@ void SetOCPtuneF5_CG10_20( void ) +overclock_level overclock_detect( void ) +{ + if(gint[HWCALC] == HWCALC_FXCG50) + { + + // OC_Default configuration + if (CPG.FLLFRQ.lword == FLLFRQ_default_CG50 && CPG.FRQCR.lword == FRQCR_default_CG50 && BSC.CS0BCR.lword == CS0BCR_default_CG50 && BSC.CS0WCR.lword == CS0WCR_default_CG50 && + BSC.CS2BCR.lword == CS2BCR_default_CG50 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == CS3BCR_default_CG50 && BSC.CS3WCR.lword == CS3WCR_default_CG50 && + BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50 ) return OC_Default; + + // OC_PtuneF2 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 && + BSC.CS0WCR.lword == 0x00000340 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 && + BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50 ) return OC_PtuneF2; + + // OC_PtuneF3 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 && + BSC.CS0WCR.lword == 0x00000240 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 && + BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF3; + + // OC_PtuneF4 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16 && BSC.CS0BCR.lword == 0x24920400 && + BSC.CS0WCR.lword == 0x000002C0 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 && + BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF4; + + // OC_PtuneF5 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 && + BSC.CS0WCR.lword == 0x00000440 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 && + BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF5; + + // Not recognized + else return OC_Undefined; + + } + else if(gint[HWCALC] == HWCALC_PRIZM) + { + + // OC_Default configuration + if (CPG.FLLFRQ.lword == FLLFRQ_default_CG10_20 && CPG.FRQCR.lword == FRQCR_default_CG10_20 && BSC.CS0BCR.lword == CS0BCR_default_CG10_20 && BSC.CS0WCR.lword == CS0WCR_default_CG10_20 && + BSC.CS2BCR.lword == CS2BCR_default_CG10_20 && BSC.CS2WCR.lword == CS2WCR_default_CG10_20 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && + BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_Default; + + // OC_PtuneF2 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_8<<20)+(DIV16<<12)+(DIV16<<8)+DIV32 && BSC.CS0BCR.lword == 0x04900400 && + BSC.CS0WCR.lword == 0x00000140 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000100C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && + BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF2; + + // OC_PtuneF3 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV32 && BSC.CS0BCR.lword == 0x24900400 && + BSC.CS0WCR.lword == 0x000002C0 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000201C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && + BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF3; + + // OC_PtuneF4 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV32 && BSC.CS0BCR.lword == 0x44900400 && + BSC.CS0WCR.lword == 0x00000440 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x00040340 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && + BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF4; + + // OC_PtuneF5 configuration + else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV16 && BSC.CS0BCR.lword == 0x34900400 && + BSC.CS0WCR.lword == 0x000003C0 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000402C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && + BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20) return OC_PtuneF5; + + // Not recognized + else return OC_Undefined; + } +} + + + // return 0 if no need to change // return 1 if successful change // return -1 on error @@ -413,6 +485,8 @@ int clock_overclock( overclock_level level ) { uint32_t count=0; + if (level==OC_Undefined) return 0; + if(gint[HWCALC] == HWCALC_FXCG50 && current_clock_state!=level) { cpu_atomic_start(); diff --git a/src/clock.h b/src/clock.h index e0459b4..a40f597 100644 --- a/src/clock.h +++ b/src/clock.h @@ -8,6 +8,7 @@ extern "C" { typedef enum { + OC_Undefined = -1, // Mode not recognized as a PTune/FTune configuration (i.e. certainly a user-defined mode) OC_Default = 0, // Default (118MHz) OC_PtuneF2 = 1, // 59MHz OC_PtuneF3 = 2, // 96MHz @@ -22,6 +23,7 @@ typedef enum int clock_overclock( overclock_level level ); +overclock_level overclock_detect( void ); #ifdef __cplusplus } diff --git a/src/main.c b/src/main.c index 5e9f13d..1f69ac7 100644 --- a/src/main.c +++ b/src/main.c @@ -1217,6 +1217,8 @@ int main(void) uint32_t time_render = 0; float dt = 1.0; + overclock_level EntryLevel; // we Store the initial OC_Level when entering the Addin + EntryLevel = overclock_detect(); /// TEST OC clock_overclock( OC_Default ); @@ -1284,6 +1286,8 @@ int main(void) dprint(1,1, C_WHITE, "FPS %.0f", (float) (1000.0f/dt) ); dprint(1,15, C_WHITE, "OC STAT %d", valueOC ); + dprint(1, 50, C_WHITE, "Addin OC Entry Level : %d", EntryLevel ); + dprint(1,75, C_WHITE, "Current OC Level : %d", overclock_detect() ); dupdate(); @@ -1305,7 +1309,8 @@ int main(void) } /// TEST OC - clock_overclock( OC_Default ); + if (EntryLevel!=OC_Undefined) clock_overclock(EntryLevel); // if we were able to recognised the initial level, we set it back + else clock_overclock( OC_Default ); // if not, we return to Normal mode prof_quit();