attempt to adjust P_Phi_f to get correct timers
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18
Demo.layout
18
Demo.layout
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@ -2,19 +2,29 @@
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<CodeBlocks_layout_file>
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<FileVersion major="1" minor="0" />
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<ActiveTarget name="Release" />
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<File name="CMakeLists.txt" open="1" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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</File>
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<File name="assets-cg/fxconv-metadata.txt" open="1" top="1" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<File name="src/clock.h" open="1" top="1" tabpos="3" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<Cursor1 position="324" topLine="0" />
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</Cursor>
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</File>
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<File name="src/clock.c" open="1" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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<Cursor1 position="4196" topLine="130" />
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</Cursor>
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</File>
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<File name="src/main.c" open="1" top="0" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
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</CodeBlocks_layout_file>
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141
src/clock.c
141
src/clock.c
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@ -44,10 +44,132 @@
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#define SDMR3_CL2 *(volatile uint8_t *)0xFEC15040 // SDMR2 Address
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#define SDMR3_CL3 *(volatile uint8_t *)0xFEC15060 // SDMR2 Address
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#include <gint/mpu/tmu.h>
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/* Arrays of standard and extra timers */
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static tmu_t *TMU = SH7305_TMU.TMU;
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static etmu_t *ETMU = SH7305_ETMU;
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/* TSTR register for standard timers */
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static volatile uint8_t *TSTR = &SH7305_TMU.TSTR;
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bool runningTimers[9]; // 9 timers : 3 TMUs + 6 ETMUs
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uint32_t initTimersTCNT[9];
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uint32_t initTimersTCOR[9];
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uint32_t newTimersTCNT[9];
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uint32_t newTimersTCOR[9];
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int initPphi;
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int newPphi;
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static int getPphi_sh7305(void)
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{
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/* The meaning of the PLL setting on SH7305 differs from the
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documentation of SH7224; the value must not be doubled. */
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int pll = CPG.FRQCR.STC + 1;
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/* The FLL ratio is the value of the setting, halved if SELXM=1 */
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int fll = CPG.FLLFRQ.FLF;
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if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
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the SH7305 it is 1 / (2^setting + 1). */
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int divb = CPG.FRQCR.BFC;
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int divi = CPG.FRQCR.IFC;
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int divp = CPG.FRQCR.P1FC;
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/* Deduce the input frequency of divider 1 */
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int base = 32768;
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if(CPG.PLLCR.FLLE) base *= fll;
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if(CPG.PLLCR.PLLE) base *= pll;
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return (base >> (divp + 1));
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}
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//We list all running timers and store this in a table (true/false)
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void listTimerStatus( void )
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{
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for(int k=0;k<9; k++)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
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}
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else
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{
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etmu_t *T = &ETMU[k-3];
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runningTimers[k]= (!T->TCR.UNIE && !T->TSTR);
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}
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}
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}
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// We get all TCNT and TCOR of currently used timers
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// And store these value into the
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void getInitialTimersParameters( void )
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{
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for(int k=0;k<9; k++)
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{
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if (runningTimers[k]==true)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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initTimersTCNT[k]= T->TCNT;
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initTimersTCOR[k]= T->TCOR;
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}
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else
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{
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etmu_t *T = &ETMU[k-3];
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initTimersTCNT[k]= T->TCNT;
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initTimersTCOR[k]= T->TCOR;
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}
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}
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}
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}
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//We update the timers with the new TCNT and new TCOR
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void updateNewTimersParameters( void )
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{
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for(int k=0;k<9; k++)
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{
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if (runningTimers[k]==true)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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T->TCNT = newTimersTCNT[k];
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T->TCOR = newTimersTCOR[k];
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}
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else
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{
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etmu_t *T = &ETMU[k-3];
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T->TCNT = newTimersTCNT[k];
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T->TCOR = newTimersTCOR[k];
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}
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}
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}
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}
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//We compute the new TCNT and new TCOR
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void computeNewTimersParameters( int initPphi_f, int newPphi_f )
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{
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for(int k=0;k<9; k++)
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{
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if (runningTimers[k]==true)
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{
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newTimersTCNT[k] = initTimersTCNT[k] * newPphi_f / initPphi_f;
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newTimersTCOR[k] = initTimersTCOR[k] * newPphi_f / initPphi_f;
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}
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}
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}
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static overclock_level current_clock_state = OC_Default;
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bool overclock_config_changed = false;
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void SetOCDefault( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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@ -174,23 +296,22 @@ int clock_overclock( overclock_level level )
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{
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cpu_atomic_start();
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listTimerStatus(); // we list the running timers
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initPphi = getPphi_sh7305(); // we get the current P_Phi_f
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getInitialTimersParameters(); // we collect the current TCNT and TCOR
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if (level == OC_Default && current_clock_state!=OC_Default) SetOCDefault(), current_clock_state= OC_Default, overclock_config_changed=true;
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if (level == OC_PtuneF2 && current_clock_state!=OC_PtuneF2) SetOCPtuneF2(), current_clock_state= OC_PtuneF2, overclock_config_changed=true;
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if (level == OC_PtuneF3 && current_clock_state!=OC_PtuneF3) SetOCPtuneF3(), current_clock_state= OC_PtuneF3, overclock_config_changed=true;
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if (level == OC_PtuneF4 && current_clock_state!=OC_PtuneF4) SetOCPtuneF4(), current_clock_state= OC_PtuneF4, overclock_config_changed=true;
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if (level == OC_PtuneF5 && current_clock_state!=OC_PtuneF5) SetOCPtuneF5(), current_clock_state= OC_PtuneF5, overclock_config_changed=true;
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/*
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if (overclock_config_changed==true)
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{
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0 && count<=1000)
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{ count++; }
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}
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*/
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newPphi = getPphi_sh7305(); // we get the new P_Phi_f after OC
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computeNewTimersParameters( initPphi, newPphi ); // we compute the new TCNT and TCOR as per the new frequency
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updateNewTimersParameters(); // we adjust the timers accordingly
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cpu_atomic_end();
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// if (count >= 1000) return -1;
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// else return 1;
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return 1;
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}
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else return 0;
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16
src/clock.h
16
src/clock.h
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@ -1,5 +1,10 @@
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#ifndef CLOCK_H
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#define CLOCK_H
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#ifndef OVERCLOCK_H
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#define OVERCLOCK_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum
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{
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@ -18,4 +23,9 @@ typedef enum
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int clock_overclock( overclock_level level );
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#endif // CLOCK_H
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#ifdef __cplusplus
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}
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#endif
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#endif /* OVERCLOCK_H */
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