Overclock option set to P5 / corrected frequency calculation for correct FPS&speed
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901b5c16db
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128
CppOutRun.layout
128
CppOutRun.layout
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82
src/clock.cc
82
src/clock.cc
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@ -4,6 +4,7 @@
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#include <gint/cpu.h>
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#include <gint/mpu/bsc.h>
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#include <gint/mpu/cpg.h>
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#include <gint/clock.h>
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#define FLLFRQ_default 0x00004384
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uint32_t initTimersTCOR[3];
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uint32_t newTimersTCNT[3];
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uint32_t newTimersTCOR[3];
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int initPphi;
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int newPphi;
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uint32_t initPphi;
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uint32_t newPphi;
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static int getPphi_sh7305(void)
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// Return the value of Pphi_Freq as per the current overclocking configuration
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uint32_t getPphi_sh7305(void)
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{
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/* The meaning of the PLL setting on SH7305 differs from the
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documentation of SH7224; the value must not be doubled. */
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int pll = CPG.FRQCR.STC + 1;
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uint32_t fll_freq;
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uint32_t pll_freq;
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uint32_t per_freq;
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fll_freq = (SH7305_CPG.FLLFRQ.FLF * 32768) / (1 << SH7305_CPG.FLLFRQ.SELXM);
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pll_freq = fll_freq * (SH7305_CPG.FRQCR.STC + 1);
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per_freq = pll_freq / (1 << (SH7305_CPG.FRQCR.P1FC + 1));
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/* The FLL ratio is the value of the setting, halved if SELXM=1 */
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int fll = CPG.FLLFRQ.FLF;
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if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
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the SH7305 it is 1 / (2^setting + 1). */
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int divb = CPG.FRQCR.BFC;
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int divi = CPG.FRQCR.IFC;
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int divp = CPG.FRQCR.P1FC;
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/* Deduce the input frequency of divider 1 */
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int base = 32768;
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if(CPG.PLLCR.FLLE) base *= fll;
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if(CPG.PLLCR.PLLE) base *= pll;
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return (base >> (divp + 1));
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return per_freq;
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}
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//We list all running timers and store this in a table (true/false)
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{
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for(int k=0;k<3; k++)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
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}
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// else
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// {
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// etmu_t *T = &ETMU[k-3];
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// runningTimers[k]= (!T->TCR.UNIE && !T->TSTR);
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// }
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//runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
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runningTimers[k] = (T->TCNT!=0xffffffff || T->TCOR!=0xffffffff); // as per Lephe's proposal for Libprof compatibility
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}
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}
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{
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if (runningTimers[k]==true)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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initTimersTCNT[k]= T->TCNT;
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initTimersTCOR[k]= T->TCOR;
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}
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// else
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// {
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// etmu_t *T = &ETMU[k-3];
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// initTimersTCNT[k]= T->TCNT;
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// initTimersTCOR[k]= T->TCOR;
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// }
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}
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}
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}
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{
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if (runningTimers[k]==true)
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{
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timer_stop( k );
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if(k < 3)
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{
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timer_pause( k );
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tmu_t *T = &TMU[k];
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T->TCNT = newTimersTCNT[k];
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T->TCOR = newTimersTCOR[k];
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}
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// else
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// {
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// etmu_t *T = &ETMU[k-3];
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// T->TCNT = newTimersTCNT[k];
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// T->TCOR = newTimersTCOR[k];
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// }
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timer_start(k);
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}
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}
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}
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//We compute the new TCNT and new TCOR
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void computeNewTimersParameters( int initPphi_f, int newPphi_f )
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void computeNewTimersParameters( uint32_t initPphi_f, uint32_t newPphi_f )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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newTimersTCNT[k] = (uint32_t) ((uint64_t) initTimersTCNT[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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newTimersTCOR[k] = (uint32_t) ((uint64_t) initTimersTCOR[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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if(initTimersTCOR[k] == 0xffffffff)
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newTimersTCOR[k] = 0xffffffff;
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else
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newTimersTCOR[k] = (uint32_t) ((uint64_t) initTimersTCOR[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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}
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}
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}
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static overclock_level current_clock_state = OC_Default;
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static overclock_level current_clock_state = -1;
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bool overclock_config_changed = false;
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void SetOCDefault( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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cpu_atomic_end();
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cpg_compute_freq();
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return 1;
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}
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else return 0;
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#define DEBUGXXX 0
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#define OVERCLCK_ACTIVABLE 1
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char version[5] = {'V','1','.','0','5'};
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||||
char version[5] = {'V','1','.','0','6'};
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||||
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||||
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||||
extern bopti_image_t player;
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||||
|
|
@ -527,7 +527,7 @@ int main(void)
|
|||
|
||||
gint_world_switch( GINT_CALL( saveparameters ) );
|
||||
|
||||
if (gint[HWCALC] == HWCALC_FXCG50 && isOCActivated == true) clock_overclock( OC_PtuneF4 );
|
||||
if (gint[HWCALC] == HWCALC_FXCG50 && isOCActivated == true) clock_overclock( OC_PtuneF5 );
|
||||
else if (gint[HWCALC] == HWCALC_FXCG50 && isOCActivated == false) clock_overclock( OC_Default );
|
||||
}
|
||||
else if (mode==3)
|
||||
|
|
|
|||
Loading…
Reference in New Issue