diff --git a/CppOutRun.layout b/CppOutRun.layout
index 5b7ccbb..a0a968a 100644
--- a/CppOutRun.layout
+++ b/CppOutRun.layout
@@ -2,24 +2,9 @@
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@@ -27,9 +12,9 @@
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@@ -37,9 +22,14 @@
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@@ -55,24 +45,25 @@
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@@ -80,28 +71,24 @@
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@@ -109,32 +96,56 @@
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@@ -164,9 +175,4 @@
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diff --git a/capture b/capture
new file mode 100755
index 0000000..0332a60
--- /dev/null
+++ b/capture
@@ -0,0 +1 @@
+fxlink -iw
diff --git a/send b/send
new file mode 100755
index 0000000..273aa57
--- /dev/null
+++ b/send
@@ -0,0 +1 @@
+fxlink -sw *.g3a
diff --git a/src/clock.cc b/src/clock.cc
index 79224a1..87d2d27 100644
--- a/src/clock.cc
+++ b/src/clock.cc
@@ -4,6 +4,7 @@
#include
#include
#include
+#include
#define FLLFRQ_default 0x00004384
@@ -58,32 +59,22 @@ uint32_t initTimersTCNT[3];
uint32_t initTimersTCOR[3];
uint32_t newTimersTCNT[3];
uint32_t newTimersTCOR[3];
-int initPphi;
-int newPphi;
+uint32_t initPphi;
+uint32_t newPphi;
-static int getPphi_sh7305(void)
+
+// Return the value of Pphi_Freq as per the current overclocking configuration
+uint32_t getPphi_sh7305(void)
{
- /* The meaning of the PLL setting on SH7305 differs from the
- documentation of SH7224; the value must not be doubled. */
- int pll = CPG.FRQCR.STC + 1;
+ uint32_t fll_freq;
+ uint32_t pll_freq;
+ uint32_t per_freq;
+ fll_freq = (SH7305_CPG.FLLFRQ.FLF * 32768) / (1 << SH7305_CPG.FLLFRQ.SELXM);
+ pll_freq = fll_freq * (SH7305_CPG.FRQCR.STC + 1);
+ per_freq = pll_freq / (1 << (SH7305_CPG.FRQCR.P1FC + 1));
- /* The FLL ratio is the value of the setting, halved if SELXM=1 */
- int fll = CPG.FLLFRQ.FLF;
- if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
-
- /* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
- the SH7305 it is 1 / (2^setting + 1). */
-
- int divb = CPG.FRQCR.BFC;
- int divi = CPG.FRQCR.IFC;
- int divp = CPG.FRQCR.P1FC;
-
- /* Deduce the input frequency of divider 1 */
- int base = 32768;
- if(CPG.PLLCR.FLLE) base *= fll;
- if(CPG.PLLCR.PLLE) base *= pll;
- return (base >> (divp + 1));
+ return per_freq;
}
//We list all running timers and store this in a table (true/false)
@@ -91,16 +82,9 @@ void listTimerStatus( void )
{
for(int k=0;k<3; k++)
{
- if(k < 3)
- {
tmu_t *T = &TMU[k];
- runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
- }
-// else
-// {
-// etmu_t *T = &ETMU[k-3];
-// runningTimers[k]= (!T->TCR.UNIE && !T->TSTR);
-// }
+ //runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
+ runningTimers[k] = (T->TCNT!=0xffffffff || T->TCOR!=0xffffffff); // as per Lephe's proposal for Libprof compatibility
}
}
@@ -112,18 +96,9 @@ void getInitialTimersParameters( void )
{
if (runningTimers[k]==true)
{
- if(k < 3)
- {
tmu_t *T = &TMU[k];
initTimersTCNT[k]= T->TCNT;
initTimersTCOR[k]= T->TCOR;
- }
-// else
-// {
-// etmu_t *T = &ETMU[k-3];
-// initTimersTCNT[k]= T->TCNT;
-// initTimersTCOR[k]= T->TCOR;
-// }
}
}
}
@@ -141,44 +116,39 @@ void updateNewTimersParameters( void )
{
if (runningTimers[k]==true)
{
- timer_stop( k );
- if(k < 3)
- {
+ timer_pause( k );
+
tmu_t *T = &TMU[k];
T->TCNT = newTimersTCNT[k];
T->TCOR = newTimersTCOR[k];
- }
-// else
-// {
-// etmu_t *T = &ETMU[k-3];
-// T->TCNT = newTimersTCNT[k];
-// T->TCOR = newTimersTCOR[k];
-// }
+
timer_start(k);
}
}
}
//We compute the new TCNT and new TCOR
-void computeNewTimersParameters( int initPphi_f, int newPphi_f )
+void computeNewTimersParameters( uint32_t initPphi_f, uint32_t newPphi_f )
{
for(int k=0;k<3; k++)
{
if (runningTimers[k]==true)
{
newTimersTCNT[k] = (uint32_t) ((uint64_t) initTimersTCNT[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
- newTimersTCOR[k] = (uint32_t) ((uint64_t) initTimersTCOR[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
+
+ if(initTimersTCOR[k] == 0xffffffff)
+ newTimersTCOR[k] = 0xffffffff;
+ else
+ newTimersTCOR[k] = (uint32_t) ((uint64_t) initTimersTCOR[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
}
}
}
-static overclock_level current_clock_state = OC_Default;
+static overclock_level current_clock_state = -1;
bool overclock_config_changed = false;
-
-
void SetOCDefault( void )
{
BSC.CS0WCR.WR = WAIT18;
@@ -321,6 +291,8 @@ int clock_overclock( overclock_level level )
cpu_atomic_end();
+ cpg_compute_freq();
+
return 1;
}
else return 0;
diff --git a/src/main.cc b/src/main.cc
index b3262b1..e3b4183 100644
--- a/src/main.cc
+++ b/src/main.cc
@@ -36,7 +36,7 @@
#define DEBUGXXX 0
#define OVERCLCK_ACTIVABLE 1
-char version[5] = {'V','1','.','0','5'};
+char version[5] = {'V','1','.','0','6'};
extern bopti_image_t player;
@@ -527,7 +527,7 @@ int main(void)
gint_world_switch( GINT_CALL( saveparameters ) );
- if (gint[HWCALC] == HWCALC_FXCG50 && isOCActivated == true) clock_overclock( OC_PtuneF4 );
+ if (gint[HWCALC] == HWCALC_FXCG50 && isOCActivated == true) clock_overclock( OC_PtuneF5 );
else if (gint[HWCALC] == HWCALC_FXCG50 && isOCActivated == false) clock_overclock( OC_Default );
}
else if (mode==3)