543 lines
20 KiB
C++
543 lines
20 KiB
C++
#include "clock.h"
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#include <gint/hardware.h>
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#include <gint/defs/types.h>
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#include <gint/cpu.h>
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#include <gint/mpu/bsc.h>
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#include <gint/mpu/cpg.h>
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#include <gint/clock.h>
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#define FLLFRQ_default_CG50 0x00004384
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#define FRQCR_default_CG50 0x0F011112
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#define CS0BCR_default_CG50 0x36DA0400 // CG50
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#define CS2BCR_default_CG50 0x36DA3400 // CG50
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#define CS3BCR_default_CG50 0x36DB4400 // CG50
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#define CS4BCR_default_CG50 0x36DB0400
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#define CS5aBCR_default_CG50 0x17DF0400
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#define CS5bBCR_default_CG50 0x17DF0400
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#define CS6aBCR_default_CG50 0x34D30200
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#define CS6bBCR_default_CG50 0x34D30200
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#define CS0WCR_default_CG50 0x000003C0 // CG50
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#define CS2WCR_default_CG50 0x000003C0 // CG50
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#define CS3WCR_default_CG50 0x000024D1 // CG50
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#define CS4WCR_default_CG50 0x00000540
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#define CS5aWCR_default_CG50 0x000203C1
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#define CS5bWCR_default_CG50 0x000203C1
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#define CS6aWCR_default_CG50 0x000302C0
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#define CS6bWCR_default_CG50 0x000302C0
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//#define SDCR_default 0x00000A08
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#define FLLFRQ_default_CG10_20 0x00004384
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#define FRQCR_default_CG10_20 0x0F102203
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#define CS0BCR_default_CG10_20 0x24920400
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#define CS2BCR_default_CG10_20 0x24923400
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#define CS3BCR_default_CG10_20 0x24924400
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#define CS4BCR_default_CG10_20 0x36DB0400
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#define CS5aBCR_default_CG10_20 0x15140400
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#define CS5bBCR_default_CG10_20 0x15140400
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#define CS6aBCR_default_CG10_20 0x34D30200
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#define CS6bBCR_default_CG10_20 0x34D30200
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#define CS0WCR_default_CG10_20 0x000001C0
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#define CS2WCR_default_CG10_20 0x00000140
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#define CS3WCR_default_CG10_20 0x000024D0
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#define CS4WCR_default_CG10_20 0x00000540
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#define CS5aWCR_default_CG10_20 0x00010240
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#define CS5bWCR_default_CG10_20 0x00010240
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#define CS6aWCR_default_CG10_20 0x000302C0
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#define CS6bWCR_default_CG10_20 0x000302C0
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#define PLL_32x 0b011111 //
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#define PLL_26x 0b011001 //
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#define PLL_16x 0b001111 // default
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#define DIV_2 0b0000 // 1/2
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#define DIV_4 0b0001 // 1/4
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#define DIV_8 0b0010 // 1/8
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#define DIV16 0b0011 // 1/16
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#define DIV32 0b0100 // 1/32
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#define WAIT18 0b1011
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#define SDMR3_CL2 *(volatile uint8_t *)0xFEC15040 // SDMR2 Address
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#define SDMR3_CL3 *(volatile uint8_t *)0xFEC15060 // SDMR2 Address
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#include <gint/mpu/tmu.h>
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#include <gint/timer.h>
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/* Arrays of standard and extra timers */
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static tmu_t *TMU = SH7305_TMU.TMU;
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static etmu_t *ETMU = SH7305_ETMU;
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/* TSTR register for standard timers */
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static volatile uint8_t *TSTR = &SH7305_TMU.TSTR;
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bool runningTimers[3]; // 9 timers : 3 TMUs + 6 ETMUs
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uint32_t initTimersTCNT[3];
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uint32_t initTimersTCOR[3];
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uint32_t newTimersTCNT[3];
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uint32_t newTimersTCOR[3];
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uint32_t initPphi;
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uint32_t newPphi;
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// Return the value of Pphi_Freq as per the current overclocking configuration
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uint32_t getPphi_sh7305(void)
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{
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uint32_t fll_freq;
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uint32_t pll_freq;
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uint32_t per_freq;
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fll_freq = (SH7305_CPG.FLLFRQ.FLF * 32768) / (1 << SH7305_CPG.FLLFRQ.SELXM);
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pll_freq = fll_freq * (SH7305_CPG.FRQCR.STC + 1);
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per_freq = pll_freq / (1 << (SH7305_CPG.FRQCR.P1FC + 1));
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return per_freq;
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}
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//We list all running timers and store this in a table (true/false)
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void listTimerStatus( void )
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{
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for(int k=0;k<3; k++)
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{
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tmu_t *T = &TMU[k];
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//runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
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runningTimers[k] = (T->TCNT!=0xffffffff || T->TCOR!=0xffffffff); // as per Lephe's proposal for Libprof compatibility
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}
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}
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// We get all TCNT and TCOR of currently used timers
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// And store these value into the
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void getInitialTimersParameters( void )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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tmu_t *T = &TMU[k];
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initTimersTCNT[k]= T->TCNT;
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initTimersTCOR[k]= T->TCOR;
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}
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}
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}
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static int callback(void)
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{
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return TIMER_CONTINUE;
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}
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//We update the timers with the new TCNT and new TCOR
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void updateNewTimersParameters( void )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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timer_pause( k );
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tmu_t *T = &TMU[k];
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T->TCNT = newTimersTCNT[k];
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T->TCOR = newTimersTCOR[k];
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timer_start(k);
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}
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}
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}
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//We compute the new TCNT and new TCOR
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void computeNewTimersParameters( uint32_t initPphi_f, uint32_t newPphi_f )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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newTimersTCNT[k] = (uint32_t) ((uint64_t) initTimersTCNT[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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if(initTimersTCOR[k] == 0xffffffff)
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newTimersTCOR[k] = 0xffffffff;
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else
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newTimersTCOR[k] = (uint32_t) ((uint64_t) initTimersTCOR[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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}
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}
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}
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static overclock_level current_clock_state = -1;
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bool overclock_config_changed = false;
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void SetOCDefault_CG50( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = FLLFRQ_default_CG50;
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CPG.FRQCR.lword = FRQCR_default_CG50;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = CS0BCR_default_CG50;
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BSC.CS0WCR.lword = CS0WCR_default_CG50;
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BSC.CS2BCR.lword = CS2BCR_default_CG50;
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BSC.CS2WCR.lword = CS2WCR_default_CG50;
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BSC.CS3BCR.lword = CS3BCR_default_CG50;
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BSC.CS3WCR.lword = CS3WCR_default_CG50;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG50;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG50;
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}
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void SetOCPtuneF2_CG50( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x00000340;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default_CG50;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default_CG50;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG50;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG50;
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}
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void SetOCPtuneF3_CG50( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x00000240;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default_CG50;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default_CG50;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG50;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG50;
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}
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void SetOCPtuneF4_CG50( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x000002C0;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default_CG50;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default_CG50;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG50;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG50;
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}
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void SetOCPtuneF5_CG50( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x00000440;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default_CG50;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default_CG50;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG50;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG50;
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}
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void SetOCDefault_CG10_20( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = FLLFRQ_default_CG10_20;
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CPG.FRQCR.lword = FRQCR_default_CG10_20;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = CS0BCR_default_CG10_20;
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BSC.CS0WCR.lword = CS0WCR_default_CG10_20;
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BSC.CS2BCR.lword = CS2BCR_default_CG10_20;
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BSC.CS2WCR.lword = CS2WCR_default_CG10_20;
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BSC.CS3BCR.lword = CS3BCR_default_CG10_20;
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BSC.CS3WCR.lword = CS3WCR_default_CG10_20;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG10_20;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG10_20;
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}
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void SetOCPtuneF2_CG10_20( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_32x<<24)+(DIV_8<<20)+(DIV16<<12)+(DIV16<<8)+DIV32;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x04900400;
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BSC.CS0WCR.lword = 0x00000140;
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BSC.CS2BCR.lword = 0x04903400;
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BSC.CS2WCR.lword = 0x000100C0;
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BSC.CS3BCR.lword = CS3BCR_default_CG10_20;
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BSC.CS3WCR.lword = CS3WCR_default_CG10_20;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG10_20;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG10_20;
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}
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void SetOCPtuneF3_CG10_20( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV32;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24900400;
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BSC.CS0WCR.lword = 0x000002C0;
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BSC.CS2BCR.lword = 0x04903400;
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BSC.CS2WCR.lword = 0x000201C0;
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BSC.CS3BCR.lword = CS3BCR_default_CG10_20;
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BSC.CS3WCR.lword = CS3WCR_default_CG10_20;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG10_20;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG10_20;
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}
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void SetOCPtuneF4_CG10_20( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV32;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x44900400;
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BSC.CS0WCR.lword = 0x00000440;
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BSC.CS2BCR.lword = 0x04903400;
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BSC.CS2WCR.lword = 0x00040340;
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BSC.CS3BCR.lword = CS3BCR_default_CG10_20;
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BSC.CS3WCR.lword = CS3WCR_default_CG10_20;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG10_20;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG10_20;
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}
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void SetOCPtuneF5_CG10_20( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV16;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x34900400;
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BSC.CS0WCR.lword = 0x000003C0;
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BSC.CS2BCR.lword = 0x04903400;
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BSC.CS2WCR.lword = 0x000402C0;
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BSC.CS3BCR.lword = CS3BCR_default_CG10_20;
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BSC.CS3WCR.lword = CS3WCR_default_CG10_20;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default_CG10_20;
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BSC.CS5AWCR.lword = CS5aWCR_default_CG10_20;
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}
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overclock_level overclock_detect( void )
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{
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if(gint[HWCALC] == HWCALC_FXCG50)
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{
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// OC_Default configuration
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if (CPG.FLLFRQ.lword == FLLFRQ_default_CG50 && CPG.FRQCR.lword == FRQCR_default_CG50 && BSC.CS0BCR.lword == CS0BCR_default_CG50 && BSC.CS0WCR.lword == CS0WCR_default_CG50 &&
|
|
BSC.CS2BCR.lword == CS2BCR_default_CG50 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == CS3BCR_default_CG50 && BSC.CS3WCR.lword == CS3WCR_default_CG50 &&
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|
BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50 ) return OC_Default;
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|
|
|
// OC_PtuneF2 configuration
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|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 &&
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BSC.CS0WCR.lword == 0x00000340 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50 ) return OC_PtuneF2;
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|
|
|
// OC_PtuneF3 configuration
|
|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 &&
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|
BSC.CS0WCR.lword == 0x00000240 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
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|
BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF3;
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|
|
|
// OC_PtuneF4 configuration
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|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16 && BSC.CS0BCR.lword == 0x24920400 &&
|
|
BSC.CS0WCR.lword == 0x000002C0 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF4;
|
|
|
|
// OC_PtuneF5 configuration
|
|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8 && BSC.CS0BCR.lword == 0x24920400 &&
|
|
BSC.CS0WCR.lword == 0x00000440 && BSC.CS2BCR.lword == 0x24923400 && BSC.CS2WCR.lword == CS2WCR_default_CG50 && BSC.CS3BCR.lword == 0x24924400 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG50 && BSC.CS5ABCR.lword == CS5aBCR_default_CG50 && BSC.CS5AWCR.lword == CS5aWCR_default_CG50) return OC_PtuneF5;
|
|
|
|
// Not recognized
|
|
else return OC_Undefined;
|
|
|
|
}
|
|
else if(gint[HWCALC] == HWCALC_PRIZM)
|
|
{
|
|
|
|
// OC_Default configuration
|
|
if (CPG.FLLFRQ.lword == FLLFRQ_default_CG10_20 && CPG.FRQCR.lword == FRQCR_default_CG10_20 && BSC.CS0BCR.lword == CS0BCR_default_CG10_20 && BSC.CS0WCR.lword == CS0WCR_default_CG10_20 &&
|
|
BSC.CS2BCR.lword == CS2BCR_default_CG10_20 && BSC.CS2WCR.lword == CS2WCR_default_CG10_20 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 && BSC.CS3WCR.lword == CS3WCR_default_CG10_20 &&
|
|
BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_Default;
|
|
|
|
// OC_PtuneF2 configuration
|
|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_8<<20)+(DIV16<<12)+(DIV16<<8)+DIV32 && BSC.CS0BCR.lword == 0x04900400 &&
|
|
BSC.CS0WCR.lword == 0x00000140 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000100C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF2;
|
|
|
|
// OC_PtuneF3 configuration
|
|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV32 && BSC.CS0BCR.lword == 0x24900400 &&
|
|
BSC.CS0WCR.lword == 0x000002C0 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000201C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF3;
|
|
|
|
// OC_PtuneF4 configuration
|
|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV32 && BSC.CS0BCR.lword == 0x44900400 &&
|
|
BSC.CS0WCR.lword == 0x00000440 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x00040340 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20 ) return OC_PtuneF4;
|
|
|
|
// OC_PtuneF5 configuration
|
|
else if (CPG.FLLFRQ.lword == 0x00004000+900 && CPG.FRQCR.lword == (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV16 && BSC.CS0BCR.lword == 0x34900400 &&
|
|
BSC.CS0WCR.lword == 0x000003C0 && BSC.CS2BCR.lword == 0x04903400 && BSC.CS2WCR.lword == 0x000402C0 && BSC.CS3BCR.lword == CS3BCR_default_CG10_20 &&
|
|
BSC.CS3WCR.lword == CS3WCR_default_CG10_20 && BSC.CS5ABCR.lword == CS5aBCR_default_CG10_20 && BSC.CS5AWCR.lword == CS5aWCR_default_CG10_20) return OC_PtuneF5;
|
|
|
|
// Not recognized
|
|
else return OC_Undefined;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
// return 0 if no need to change
|
|
// return 1 if successful change
|
|
// return -1 on error
|
|
|
|
int clock_overclock( overclock_level level )
|
|
{
|
|
uint32_t count=0;
|
|
|
|
if (level==OC_Undefined) return 0;
|
|
|
|
if(gint[HWCALC] == HWCALC_FXCG50 && current_clock_state!=level)
|
|
{
|
|
cpu_atomic_start();
|
|
|
|
listTimerStatus(); // we list the running timers
|
|
initPphi = getPphi_sh7305(); // we get the current P_Phi_f
|
|
getInitialTimersParameters(); // we collect the current TCNT and TCOR
|
|
|
|
if (level == OC_Default && current_clock_state!=OC_Default) SetOCDefault_CG50(), current_clock_state= OC_Default, overclock_config_changed=true;
|
|
if (level == OC_PtuneF2 && current_clock_state!=OC_PtuneF2) SetOCPtuneF2_CG50(), current_clock_state= OC_PtuneF2, overclock_config_changed=true;
|
|
if (level == OC_PtuneF3 && current_clock_state!=OC_PtuneF3) SetOCPtuneF3_CG50(), current_clock_state= OC_PtuneF3, overclock_config_changed=true;
|
|
if (level == OC_PtuneF4 && current_clock_state!=OC_PtuneF4) SetOCPtuneF4_CG50(), current_clock_state= OC_PtuneF4, overclock_config_changed=true;
|
|
if (level == OC_PtuneF5 && current_clock_state!=OC_PtuneF5) SetOCPtuneF5_CG50(), current_clock_state= OC_PtuneF5, overclock_config_changed=true;
|
|
|
|
newPphi = getPphi_sh7305(); // we get the new P_Phi_f after OC
|
|
computeNewTimersParameters( initPphi, newPphi ); // we compute the new TCNT and TCOR as per the new frequency
|
|
updateNewTimersParameters(); // we adjust the timers accordingly
|
|
|
|
cpu_atomic_end();
|
|
|
|
cpg_compute_freq();
|
|
|
|
return 1;
|
|
}
|
|
else if(gint[HWCALC] == HWCALC_PRIZM && current_clock_state!=level)
|
|
{
|
|
cpu_atomic_start();
|
|
|
|
listTimerStatus(); // we list the running timers
|
|
initPphi = getPphi_sh7305(); // we get the current P_Phi_f
|
|
getInitialTimersParameters(); // we collect the current TCNT and TCOR
|
|
|
|
if (level == OC_Default && current_clock_state!=OC_Default) SetOCDefault_CG10_20(), current_clock_state= OC_Default, overclock_config_changed=true;
|
|
if (level == OC_PtuneF2 && current_clock_state!=OC_PtuneF2) SetOCPtuneF2_CG10_20(), current_clock_state= OC_PtuneF2, overclock_config_changed=true;
|
|
if (level == OC_PtuneF3 && current_clock_state!=OC_PtuneF3) SetOCPtuneF3_CG10_20(), current_clock_state= OC_PtuneF3, overclock_config_changed=true;
|
|
if (level == OC_PtuneF4 && current_clock_state!=OC_PtuneF4) SetOCPtuneF4_CG10_20(), current_clock_state= OC_PtuneF4, overclock_config_changed=true;
|
|
if (level == OC_PtuneF5 && current_clock_state!=OC_PtuneF5) SetOCPtuneF5_CG10_20(), current_clock_state= OC_PtuneF5, overclock_config_changed=true;
|
|
|
|
newPphi = getPphi_sh7305(); // we get the new P_Phi_f after OC
|
|
computeNewTimersParameters( initPphi, newPphi ); // we compute the new TCNT and TCOR as per the new frequency
|
|
updateNewTimersParameters(); // we adjust the timers accordingly
|
|
|
|
cpu_atomic_end();
|
|
|
|
cpg_compute_freq();
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
|
|
else return 0;
|
|
}
|