328 lines
9.0 KiB
C++
328 lines
9.0 KiB
C++
#include "clock.h"
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#include <gint/hardware.h>
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#include <gint/defs/types.h>
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#include <gint/cpu.h>
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#include <gint/mpu/bsc.h>
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#include <gint/mpu/cpg.h>
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#define FLLFRQ_default 0x00004384
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#define FRQCR_default 0x0F011112
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#define CS0BCR_default 0x36DA0400 // CG50
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#define CS2BCR_default 0x36DA3400 // CG50
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#define CS3BCR_default 0x36DB4400 // CG50
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#define CS4BCR_default 0x36DB0400
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#define CS5aBCR_default 0x17DF0400
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#define CS5bBCR_default 0x17DF0400
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#define CS6aBCR_default 0x34D30200
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#define CS6bBCR_default 0x34D30200
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#define CS0WCR_default 0x000003C0 // CG50
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#define CS2WCR_default 0x000003C0 // CG50
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#define CS3WCR_default 0x000024D1 // CG50
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#define CS4WCR_default 0x00000540
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#define CS5aWCR_default 0x000203C1
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#define CS5bWCR_default 0x000203C1
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#define CS6aWCR_default 0x000302C0
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#define CS6bWCR_default 0x000302C0
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#define SDCR_default 0x00000A08
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#define PLL_32x 0b011111 //
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#define PLL_26x 0b011001 //
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#define PLL_16x 0b001111 // default
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#define DIV_2 0b0000 // 1/2
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#define DIV_4 0b0001 // 1/4
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#define DIV_8 0b0010 // 1/8
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#define DIV16 0b0011 // 1/16
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#define WAIT18 0b1011
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#define SDMR3_CL2 *(volatile uint8_t *)0xFEC15040 // SDMR2 Address
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#define SDMR3_CL3 *(volatile uint8_t *)0xFEC15060 // SDMR2 Address
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#include <gint/mpu/tmu.h>
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#include <gint/timer.h>
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/* Arrays of standard and extra timers */
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static tmu_t *TMU = SH7305_TMU.TMU;
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static etmu_t *ETMU = SH7305_ETMU;
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/* TSTR register for standard timers */
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static volatile uint8_t *TSTR = &SH7305_TMU.TSTR;
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bool runningTimers[3]; // 9 timers : 3 TMUs + 6 ETMUs
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uint32_t initTimersTCNT[3];
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uint32_t initTimersTCOR[3];
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uint32_t newTimersTCNT[3];
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uint32_t newTimersTCOR[3];
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int initPphi;
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int newPphi;
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static int getPphi_sh7305(void)
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{
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/* The meaning of the PLL setting on SH7305 differs from the
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documentation of SH7224; the value must not be doubled. */
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int pll = CPG.FRQCR.STC + 1;
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/* The FLL ratio is the value of the setting, halved if SELXM=1 */
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int fll = CPG.FLLFRQ.FLF;
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if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
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the SH7305 it is 1 / (2^setting + 1). */
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int divb = CPG.FRQCR.BFC;
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int divi = CPG.FRQCR.IFC;
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int divp = CPG.FRQCR.P1FC;
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/* Deduce the input frequency of divider 1 */
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int base = 32768;
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if(CPG.PLLCR.FLLE) base *= fll;
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if(CPG.PLLCR.PLLE) base *= pll;
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return (base >> (divp + 1));
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}
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//We list all running timers and store this in a table (true/false)
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void listTimerStatus( void )
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{
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for(int k=0;k<3; k++)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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runningTimers[k]= (!T->TCR.UNIE && !(*TSTR & (1 << k)));
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}
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// else
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// {
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// etmu_t *T = &ETMU[k-3];
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// runningTimers[k]= (!T->TCR.UNIE && !T->TSTR);
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// }
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}
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}
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// We get all TCNT and TCOR of currently used timers
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// And store these value into the
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void getInitialTimersParameters( void )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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initTimersTCNT[k]= T->TCNT;
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initTimersTCOR[k]= T->TCOR;
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}
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// else
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// {
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// etmu_t *T = &ETMU[k-3];
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// initTimersTCNT[k]= T->TCNT;
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// initTimersTCOR[k]= T->TCOR;
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// }
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}
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}
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}
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static int callback(void)
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{
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return TIMER_CONTINUE;
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}
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//We update the timers with the new TCNT and new TCOR
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void updateNewTimersParameters( void )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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timer_stop( k );
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if(k < 3)
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{
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tmu_t *T = &TMU[k];
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T->TCNT = newTimersTCNT[k];
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T->TCOR = newTimersTCOR[k];
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}
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// else
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// {
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// etmu_t *T = &ETMU[k-3];
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// T->TCNT = newTimersTCNT[k];
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// T->TCOR = newTimersTCOR[k];
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// }
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timer_start(k);
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}
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}
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}
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//We compute the new TCNT and new TCOR
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void computeNewTimersParameters( int initPphi_f, int newPphi_f )
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{
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for(int k=0;k<3; k++)
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{
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if (runningTimers[k]==true)
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{
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newTimersTCNT[k] = (uint32_t) ((uint64_t) initTimersTCNT[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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newTimersTCOR[k] = (uint32_t) ((uint64_t) initTimersTCOR[k] * (uint64_t) newPphi_f / (uint64_t) initPphi_f);
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}
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}
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}
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static overclock_level current_clock_state = OC_Default;
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bool overclock_config_changed = false;
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void SetOCDefault( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = FLLFRQ_default;
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CPG.FRQCR.lword = FRQCR_default;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = CS0BCR_default;
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BSC.CS0WCR.lword = CS0WCR_default;
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BSC.CS2BCR.lword = CS2BCR_default;
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BSC.CS2WCR.lword = CS2WCR_default;
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BSC.CS3BCR.lword = CS3BCR_default;
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BSC.CS3WCR.lword = CS3WCR_default;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default;
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BSC.CS5AWCR.lword = CS5aWCR_default;
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}
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void SetOCPtuneF2( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x00000340;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default;
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BSC.CS5AWCR.lword = CS5aWCR_default;
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}
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void SetOCPtuneF3( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x00000240;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default;
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BSC.CS5AWCR.lword = CS5aWCR_default;
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}
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void SetOCPtuneF4( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x000002C0;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default;
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BSC.CS5ABCR.lword = CS5aBCR_default;
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BSC.CS5AWCR.lword = CS5aWCR_default;
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}
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void SetOCPtuneF5( void )
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{
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BSC.CS0WCR.WR = WAIT18;
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CPG.FLLFRQ.lword = 0x00004000+900;
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CPG.FRQCR.lword = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8;
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CPG.FRQCR.KICK = 1 ;
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while((CPG.LSTATS & 1)!=0)
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BSC.CS0BCR.lword = 0x24920400;
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BSC.CS0WCR.lword = 0x00000440;
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BSC.CS2BCR.lword = 0x24923400;
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BSC.CS2WCR.lword = CS2WCR_default;
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BSC.CS3BCR.lword = 0x24924400;
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BSC.CS3WCR.lword = CS3WCR_default;
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if ( BSC.CS3WCR.A3CL == 1 ) SDMR3_CL2 = 0; else SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = CS5aBCR_default;
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BSC.CS5AWCR.lword = CS5aWCR_default;
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}
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// return 0 if no need to change
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// return 1 if successful change
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// return -1 on error
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int clock_overclock( overclock_level level )
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{
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uint32_t count=0;
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if(gint[HWCALC] == HWCALC_FXCG50 && current_clock_state!=level)
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{
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cpu_atomic_start();
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listTimerStatus(); // we list the running timers
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initPphi = getPphi_sh7305(); // we get the current P_Phi_f
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getInitialTimersParameters(); // we collect the current TCNT and TCOR
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if (level == OC_Default && current_clock_state!=OC_Default) SetOCDefault(), current_clock_state= OC_Default, overclock_config_changed=true;
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if (level == OC_PtuneF2 && current_clock_state!=OC_PtuneF2) SetOCPtuneF2(), current_clock_state= OC_PtuneF2, overclock_config_changed=true;
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if (level == OC_PtuneF3 && current_clock_state!=OC_PtuneF3) SetOCPtuneF3(), current_clock_state= OC_PtuneF3, overclock_config_changed=true;
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if (level == OC_PtuneF4 && current_clock_state!=OC_PtuneF4) SetOCPtuneF4(), current_clock_state= OC_PtuneF4, overclock_config_changed=true;
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if (level == OC_PtuneF5 && current_clock_state!=OC_PtuneF5) SetOCPtuneF5(), current_clock_state= OC_PtuneF5, overclock_config_changed=true;
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newPphi = getPphi_sh7305(); // we get the new P_Phi_f after OC
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computeNewTimersParameters( initPphi, newPphi ); // we compute the new TCNT and TCOR as per the new frequency
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updateNewTimersParameters(); // we adjust the timers accordingly
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cpu_atomic_end();
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return 1;
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}
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else return 0;
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}
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