forked from Lephenixnoir/PythonExtra
464 lines
14 KiB
C
464 lines
14 KiB
C
/* Teensyduino Core Library
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* http://www.pjrc.com/teensy/
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* Copyright (c) 2013 PJRC.COM, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* 1. The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* 2. If the Software is incorporated into a build system that allows
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* selection among a list of target devices, then similar target
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* devices manufactured by PJRC.COM must be included in the list of
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* target devices and selectable in the same manner.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "core_pins.h"
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//#include "HardwareSerial.h"
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static uint8_t calibrating;
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static uint8_t analog_right_shift = 0;
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static uint8_t analog_config_bits = 10;
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static uint8_t analog_num_average = 4;
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static uint8_t analog_reference_internal = 0;
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// the alternate clock is connected to OSCERCLK (16 MHz).
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// datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode
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// datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode
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#if F_BUS == 60000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
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#elif F_BUS == 56000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
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#elif F_BUS == 48000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz
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#elif F_BUS == 40000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz
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#elif F_BUS == 36000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
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#elif F_BUS == 24000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz
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#elif F_BUS == 16000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz
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#elif F_BUS == 8000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
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#elif F_BUS == 4000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
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#elif F_BUS == 2000000
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#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
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#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
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#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
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#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
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#else
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#error "F_BUS must be 60, 56, 48, 40, 36, 24, 4 or 2 MHz"
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#endif
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void analog_init(void)
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{
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uint32_t num;
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VREF_TRM = 0x60;
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VREF_SC = 0xE1; // enable 1.2 volt ref
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if (analog_config_bits == 8) {
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ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
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ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
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#if defined(__MK20DX256__)
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ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
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ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
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#endif
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} else if (analog_config_bits == 10) {
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ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
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ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
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#if defined(__MK20DX256__)
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ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
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ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
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#endif
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} else if (analog_config_bits == 12) {
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ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
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ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
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#if defined(__MK20DX256__)
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ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
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ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
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#endif
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} else {
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ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
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ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
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#if defined(__MK20DX256__)
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ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
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ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
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#endif
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}
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if (analog_reference_internal) {
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ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
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#if defined(__MK20DX256__)
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ADC1_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
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#endif
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} else {
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ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
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#if defined(__MK20DX256__)
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ADC1_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
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#endif
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}
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num = analog_num_average;
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if (num <= 1) {
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ADC0_SC3 = ADC_SC3_CAL; // begin cal
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#if defined(__MK20DX256__)
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ADC1_SC3 = ADC_SC3_CAL; // begin cal
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#endif
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} else if (num <= 4) {
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ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
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#if defined(__MK20DX256__)
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ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
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#endif
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} else if (num <= 8) {
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ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
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#if defined(__MK20DX256__)
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ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
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#endif
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} else if (num <= 16) {
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ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
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#if defined(__MK20DX256__)
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ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
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#endif
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} else {
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ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
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#if defined(__MK20DX256__)
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ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
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#endif
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}
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calibrating = 1;
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}
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static void wait_for_cal(void)
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{
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uint16_t sum;
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//serial_print("wait_for_cal\n");
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#if defined(__MK20DX128__)
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while (ADC0_SC3 & ADC_SC3_CAL) {
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// wait
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}
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#elif defined(__MK20DX256__)
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while ((ADC0_SC3 & ADC_SC3_CAL) || (ADC1_SC3 & ADC_SC3_CAL)) {
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// wait
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}
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#endif
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__disable_irq();
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if (calibrating) {
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//serial_print("\n");
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sum = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
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sum = (sum / 2) | 0x8000;
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ADC0_PG = sum;
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//serial_print("ADC0_PG = ");
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//serial_phex16(sum);
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//serial_print("\n");
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sum = ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;
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sum = (sum / 2) | 0x8000;
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ADC0_MG = sum;
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//serial_print("ADC0_MG = ");
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//serial_phex16(sum);
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//serial_print("\n");
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#if defined(__MK20DX256__)
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sum = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
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sum = (sum / 2) | 0x8000;
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ADC1_PG = sum;
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sum = ADC1_CLMS + ADC1_CLM4 + ADC1_CLM3 + ADC1_CLM2 + ADC1_CLM1 + ADC1_CLM0;
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sum = (sum / 2) | 0x8000;
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ADC1_MG = sum;
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#endif
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calibrating = 0;
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}
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__enable_irq();
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}
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// ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC.
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// VREFH/VREFL - connected as the primary reference option
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// 1.2 V VREF_OUT - connected as the VALT reference option
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#define DEFAULT 0
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#define INTERNAL 2
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#define INTERNAL1V2 2
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#define INTERNAL1V1 2
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#define EXTERNAL 0
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void analogReference(uint8_t type)
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{
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if (type) {
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// internal reference requested
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if (!analog_reference_internal) {
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analog_reference_internal = 1;
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if (calibrating) {
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ADC0_SC3 = 0; // cancel cal
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#if defined(__MK20DX256__)
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ADC1_SC3 = 0; // cancel cal
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#endif
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}
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analog_init();
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}
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} else {
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// vcc or external reference requested
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if (analog_reference_internal) {
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analog_reference_internal = 0;
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if (calibrating) {
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ADC0_SC3 = 0; // cancel cal
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#if defined(__MK20DX256__)
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ADC1_SC3 = 0; // cancel cal
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#endif
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}
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analog_init();
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}
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}
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}
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void analogReadRes(unsigned int bits)
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{
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unsigned int config;
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if (bits >= 13) {
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if (bits > 16) bits = 16;
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config = 16;
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} else if (bits >= 11) {
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config = 12;
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} else if (bits >= 9) {
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config = 10;
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} else {
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config = 8;
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}
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analog_right_shift = config - bits;
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if (config != analog_config_bits) {
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analog_config_bits = config;
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if (calibrating) ADC0_SC3 = 0; // cancel cal
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analog_init();
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}
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}
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void analogReadAveraging(unsigned int num)
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{
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if (calibrating) wait_for_cal();
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if (num <= 1) {
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num = 0;
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ADC0_SC3 = 0;
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} else if (num <= 4) {
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num = 4;
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ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
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} else if (num <= 8) {
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num = 8;
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ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
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} else if (num <= 16) {
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num = 16;
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ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);
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} else {
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num = 32;
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ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);
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}
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analog_num_average = num;
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}
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// The SC1A register is used for both software and hardware trigger modes of operation.
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#if defined(__MK20DX128__)
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static const uint8_t channel2sc1a[] = {
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5, 14, 8, 9, 13, 12, 6, 7, 15, 4,
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0, 19, 3, 21, 26, 22, 23
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};
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#elif defined(__MK20DX256__)
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static const uint8_t channel2sc1a[] = {
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5, 14, 8, 9, 13, 12, 6, 7, 15, 4,
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0, 19, 3, 19+128, 26, 18+128, 23,
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5+192, 5+128, 4+128, 6+128, 7+128, 4+192
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// A15 26 E1 ADC1_SE5a 5+64
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// A16 27 C9 ADC1_SE5b 5
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// A17 28 C8 ADC1_SE4b 4
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// A18 29 C10 ADC1_SE6b 6
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// A19 30 C11 ADC1_SE7b 7
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// A20 31 E0 ADC1_SE4a 4+64
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};
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#endif
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// TODO: perhaps this should store the NVIC priority, so it works recursively?
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static volatile uint8_t analogReadBusyADC0 = 0;
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#if defined(__MK20DX256__)
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static volatile uint8_t analogReadBusyADC1 = 0;
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#endif
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int analogRead(uint8_t pin)
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{
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int result;
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uint8_t index, channel;
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//serial_phex(pin);
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//serial_print(" ");
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if (pin <= 13) {
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index = pin; // 0-13 refer to A0-A13
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} else if (pin <= 23) {
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index = pin - 14; // 14-23 are A0-A9
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#if defined(__MK20DX256__)
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} else if (pin >= 26 && pin <= 31) {
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index = pin - 9; // 26-31 are A15-A20
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#endif
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} else if (pin >= 34 && pin <= 40) {
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index = pin - 24; // 34-37 are A10-A13, 38 is temp sensor,
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// 39 is vref, 40 is unused (A14 on Teensy 3.1)
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} else {
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return 0; // all others are invalid
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}
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//serial_phex(index);
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//serial_print(" ");
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channel = channel2sc1a[index];
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//serial_phex(channel);
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//serial_print(" ");
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//serial_print("analogRead");
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//return 0;
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if (calibrating) wait_for_cal();
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//pin = 5; // PTD1/SE5b, pin 14, analog 0
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#if defined(__MK20DX256__)
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if (channel & 0x80) goto beginADC1;
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#endif
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__disable_irq();
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startADC0:
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//serial_print("startADC0\n");
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ADC0_SC1A = channel;
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analogReadBusyADC0 = 1;
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__enable_irq();
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while (1) {
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__disable_irq();
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if ((ADC0_SC1A & ADC_SC1_COCO)) {
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result = ADC0_RA;
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analogReadBusyADC0 = 0;
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__enable_irq();
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result >>= analog_right_shift;
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return result;
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}
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// detect if analogRead was used from an interrupt
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// if so, our analogRead got canceled, so it must
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// be restarted.
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if (!analogReadBusyADC0) goto startADC0;
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__enable_irq();
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yield();
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}
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#if defined(__MK20DX256__)
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beginADC1:
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__disable_irq();
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startADC1:
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//serial_print("startADC0\n");
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// ADC1_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b.
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if (channel & 0x40) {
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ADC1_CFG2 &= ~ADC_CFG2_MUXSEL;
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} else {
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ADC1_CFG2 |= ADC_CFG2_MUXSEL;
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}
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ADC1_SC1A = channel & 0x3F;
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analogReadBusyADC1 = 1;
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__enable_irq();
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while (1) {
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__disable_irq();
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if ((ADC1_SC1A & ADC_SC1_COCO)) {
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result = ADC1_RA;
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analogReadBusyADC1 = 0;
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__enable_irq();
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result >>= analog_right_shift;
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return result;
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}
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// detect if analogRead was used from an interrupt
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// if so, our analogRead got canceled, so it must
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// be restarted.
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if (!analogReadBusyADC1) goto startADC1;
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__enable_irq();
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yield();
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}
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#endif
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}
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void analogWriteDAC0(int val)
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{
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#if defined(__MK20DX256__)
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SIM_SCGC2 |= SIM_SCGC2_DAC0;
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if (analog_reference_internal) {
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DAC0_C0 = DAC_C0_DACEN; // 1.2V ref is DACREF_1
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} else {
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DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
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}
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if (val < 0) val = 0; // TODO: saturate instruction?
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else if (val > 4095) val = 4095;
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*(int16_t *)&(DAC0_DAT0L) = val;
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#endif
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}
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