58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
#include "vxBoot/hardware.h"
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#include <gint/mmu.h>
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/* __ram_get_size() : try to determine the RAM size */
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static ptrdiff_t __ram_get_size(uintptr_t start_ram)
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{
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volatile uint32_t *ptr = (void*)start_ram;
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volatile uint32_t *tst = (void*)start_ram;
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uint32_t backup;
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//TODO: use UTLB page size information to walk through each pages
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while (1) {
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ptr = &ptr[4096];
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backup = ptr[0];
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ptr[0] = 0xdeadbeef;
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if (ptr[0] != 0xdeadbeef || ptr[0] == tst[0]) break;
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ptr[0] = backup;
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}
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ptr[0] = backup;
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return ((ptrdiff_t)((uintptr_t)ptr - (uintptr_t)tst));
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}
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/* hardware_get_info() : get hardware information */
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int hardware_get_info(struct hwinfo * const hwinfo)
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{
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if (hwinfo == NULL)
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return (-1);
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uintptr_t uram = mmu_translate(0x08100000, NULL);
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hwinfo->ram.physical.origin_addr = uram & 0xff000000;
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hwinfo->ram.physical.kernel_addr = uram + mmu_uram_size();
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hwinfo->ram.physical.user_addr = uram;
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hwinfo->ram.size = __ram_get_size(uram | 0xa0000000);
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hwinfo->ram.available = hwinfo->ram.size;
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hwinfo->ram.available -= hwinfo->ram.physical.kernel_addr & 0x00ffffff;
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return (0);
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}
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/* hardware_utlb_patch() : patch the UTLB NULL page set by Casio */
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void hardware_utlb_patch(void)
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{
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for (int i = 0; i < 64; ++i) {
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utlb_addr_t *addr = (void*)utlb_addr(i);
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utlb_data_t *data = (void*)utlb_data(i);
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if(!addr->V || !data->V) continue;
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uintptr_t vaddr = addr->VPN << 10;
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if (vaddr == 0x00000000) {
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addr->V = 0;
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data->V = 0;
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return;
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}
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}
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}
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