VxKernel 0.6.0-19 : Add DMA driver
@add <> board/fxcg50/board | add DMA module support <> src/driver/mpu/sh/sh7305/dma | add async transfer primitives | add DMA memcpy algorithm | add DMA memset algorithm | add DMA wait primitives @update <> vhex/dma | [types] change dma_id_t type | [interface] add dma_spinwait primitives <> vhex/driver | add DMA flags for driver interface <> vhex/driver/mpu/sh/sh7305/dma | expose kernel-level primitives | add internal types definitions <> src/driver/mpu/sh/sh7305/dma | proper channel cache | proper channel interrupt handler | proper channel error handler | proper address translation | proper driver installation (context save/restore) | proper driver interface exposition @fix <> vhex/keyboard/keycode | fix typedef again <> src/dma | fix driver exposition | fix driver interface link dump <> src/driver/mpu/sh/sh7305/intc | fix generic handler installation
This commit is contained in:
Yann MAGNIN
parent
7e01fb8444
commit
b8abc2eae7
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@ -11,6 +11,7 @@ modules = [
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'kmalloc',
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'timer',
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'rtc',
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'dma'
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]
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[drivers]
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@ -8,6 +8,7 @@ struct dma_drv_interface
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dma_id_t (*dma_memcpy)(void * restrict, void * restrict, size_t);
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dma_id_t (*dma_memset)(void * restrict, int, size_t);
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int (*dma_wait)(dma_id_t);
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int (*dma_spinwait)(dma_id_t);
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};
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#endif /* __VHEX_DMA_INTERFACE__ */
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@ -3,6 +3,6 @@
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#include <vhex/defs/types.h>
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typedef uint32_t dma_id_t;
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typedef int32_t dma_id_t;
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#endif /* __VHEX_DMA_TYPES__ */
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@ -48,7 +48,7 @@ struct vhex_driver
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uint8_t TIMER :1;
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uint8_t DISPLAY :1;
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uint8_t :1;
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uint8_t DMA :1;
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uint8_t :1;
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uint8_t SHARED :1;
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uint8_t UNUSED :1;
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@ -4,6 +4,8 @@
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#include <vhex/defs/attributes.h>
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#include <vhex/defs/types.h>
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#include <vhex/dma/types.h>
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//---
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// SH7305 Direct Memory Access Controller. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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@ -94,7 +96,80 @@ struct __sh7305_dma
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#define SH7305_DMA (*((volatile struct __sh7305_dma *)0xfe008020))
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//---
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// Kernel-level API
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//---
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/* dma_size_t - Transfer block size */
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typedef enum
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{
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/* Normal transfers of 1, 2, 4, 8, 16 or 32 bytes at a time */
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DMA_BLOCK_SIZE_1B = 0,
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DMA_BLOCK_SIZE_2B = 1,
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DMA_BLOCK_SIZE_4B = 2,
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DMA_BLOCK_SIZE_8B = 7,
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DMA_BLOCK_SIZE_16B = 3,
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DMA_BLOCK_SIZE_32B = 4,
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/* Transfers of 16 or 32 bytes divided in two operations */
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DMA_BLOCK_SIZE_16B_DIV = 11,
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DMA_BLOCK_SIZE_32B_DIV = 12,
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} dma_block_size_t;
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/* dma_addr_op_t - Addressing mode for source and destination regions */
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typedef enum
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{
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/* Fixed address mode: the same address is read/written at each step */
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DMA_ADDR_FIXED = 0,
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/* Increment: address is incremented by transfer size at each step */
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DMA_ADDR_INC = 1,
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/* Decrement: only allowed for 1/2/4-byte transfers */
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DMA_ADDR_DEC = 2,
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/* Fixed division mode: address is fixed even in 16/32-divide mode */
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DMA_ADDR_FIXEDDIV = 3,
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} dma_addr_op_t;
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/* sh7305_dma_id_t : internal DMA ID structure */
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typedef union {
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uint32_t lword;
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struct {
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uint32_t INVALID : 1;
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uint32_t IDX : 3;
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uint32_t KEYFRAME : 28;
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};
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} sh7305_dma_id_t;
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/* internal cache channel information */
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typedef struct {
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sh7305_dma_id_t id;
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volatile struct __sh7305_dma_channel *hw;
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} sh7305_dma_channel_t;
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extern dma_id_t sh7305_dma_transfert_async(
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uintptr_t src, dma_addr_op_t src_op,
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uintptr_t dst, dma_addr_op_t dst_op,
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dma_block_size_t block_size,
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int block_count
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);
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/* dma_memcpy() : memcpy using DMA */
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extern dma_id_t sh7305_dma_memcpy(void * restrict, void * restrict, size_t);
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/* dma_memset() : memset using the DMA */
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extern dma_id_t sh7305_dma_memset(void *dst, int c, size_t sz);
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/* dma_wait() : wait the end of the DMA channel transfer */
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extern int sh7305_dma_wait(dma_id_t id);
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/* dma_wait() : wait the end of the DMA channel transfer without interruption */
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extern int sh7305_dma_spinwait(dma_id_t id);
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/* sh7305_dma_wait() : wait DAM channel */
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extern int sh7305_dma_channel_wait(sh7305_dma_channel_t *ch, int atomic);
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/* sh7305_dma_channel_find() : find a channel using the ID */
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extern sh7305_dma_channel_t *sh7305_dma_channel_find(sh7305_dma_id_t id);
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#endif /* __VHEX_DRIVER_MPU_SH_SH7305_DMA__ */
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@ -6,7 +6,7 @@
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(((row & 0x0f) << 4) | ((column & 0x0f) << 0))
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/* Define all keycode */
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enum
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typedef enum
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{
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KEY_F1 = 0x41,
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KEY_F2 = 0x42,
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@ -68,6 +68,6 @@ enum
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KEY_UNUSED = 0xff,
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KEY_NONE = 0xfe,
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};
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} key_t;
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#endif /* __VHEX_KEYBOARD_KEYCODE__ */
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@ -4,6 +4,8 @@
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#include <vhex/defs/types.h>
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#include <vhex/defs/attributes.h>
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#include <vhex/keyboard/keycode.h>
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/* key_event_t: Low-level or high-level keyboard event
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This structure represents an event that occurs on the keyboard. It is first
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@ -54,7 +56,5 @@ enum
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KEYEV_REP_NEXT = 2,
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};
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/* keyboard key */
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typedef int key_t;
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#endif /* __VHEX_KEYBOARD_TYPES__ */
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@ -19,7 +19,7 @@ static void __dma_init(void)
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for (int i = 0; i < vhex_driver_count(); ++i) {
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if (driver[i].flags.DMA) {
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memcpy(
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&rtc_info.driver,
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&dma_info.driver,
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driver[i].module_data,
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sizeof(struct dma_drv_interface)
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);
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@ -36,7 +36,7 @@ static void __dma_quit(void)
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/* declare the timer module */
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struct vhex_module mod_rtc = {
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struct vhex_module mod_dma = {
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.name = "DMA",
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.init = &__dma_init,
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.quit = &__dma_quit,
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@ -1,31 +1,253 @@
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#include <vhex/driver/mpu/sh/sh7305/dma.h>
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#include <vhex/driver/mpu/sh/sh7305/intc.h>
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#include <vhex/driver/cpu.h>
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//#include <vhex/driver/mpu/sh/sh7305/power.h>
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#include <vhex/driver.h>
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#include <vhex/defs/call.h>
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#include <vhex/dma/interface.h>
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#include <vhex/display.h>
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/* internal DMA cache information */
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static struct {
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uint32_t keyframe;
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sh7305_dma_channel_t channel[6];
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} dmac_info = {
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.keyframe = 0x00000000,
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.channel = {
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{
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.id = {
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.INVALID = 1,
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.IDX = 0b111,
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.KEYFRAME = 0
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},
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.hw = &SH7305_DMA.DMA0
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},
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{
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.id = {
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.INVALID = 1,
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.IDX = 0b111,
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.KEYFRAME = 0
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},
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.hw = &SH7305_DMA.DMA1
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},
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{
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.id = {
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.INVALID = 1,
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.IDX = 0b111,
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.KEYFRAME = 0
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},
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.hw = &SH7305_DMA.DMA2
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},
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{
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.id = {
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.INVALID = 1,
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.IDX = 0b111,
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.KEYFRAME = 0
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},
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.hw = &SH7305_DMA.DMA3
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},
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{
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.id = {
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.INVALID = 1,
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.IDX = 0b111,
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.KEYFRAME = 0
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},
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.hw = &SH7305_DMA.DMA4
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},
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{
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.id = {
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.INVALID = 1,
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.IDX = 0b111,
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.KEYFRAME = 0
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},
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.hw = &SH7305_DMA.DMA5
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},
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}
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};
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//---
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// Driver internals
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//---
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/* dma_translate(): Translate virtual address to DMA-suitable form */
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static uintptr_t sh7305_dma_translate_addr(uintptr_t a)
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{
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/* Preserve RS addresses (as of SH7724 Reference, 11.2.2) */
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if(a >= 0xfd800000 && a < 0xfd800800)
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return a;
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/* Translate virtual addresses to IL memory to physical addresses; the
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same address is used (as of SH7724 Reference, 10.3.3) */
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if(a >= 0xe5200000 && a < 0xe5204000)
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return a;
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/* First additional on-chip memory area (XRAM) */
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if(a >= 0xe5007000 && a < 0xe5009000)
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return a;
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/* Second on-chip memory area (YRAM) */
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if(a >= 0xe5017000 && a < 0xe5019000)
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return a;
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/* Translate P1 and P2 addresses to ROM and RAM to physical form */
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if(a >= 0x80000000 && a < 0xc0000000)
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return a & 0x1fffffff;
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/* By default: I don't know what this is, let's preserve it */
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return a;
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}
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/* sh7305_dma_channel_reserve() : wait until a channel is free and reserve it */
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static sh7305_dma_channel_t *sh7305_dma_channel_reserve(void)
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{
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sh7305_dma_channel_t *ch;
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ch = NULL;
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while (1)
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{
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cpu_atomic_start();
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for (int i = 5; i >= 0; --i) {
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if (dmac_info.channel[i].id.INVALID == 0)
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continue;
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dmac_info.keyframe += 1;
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ch = &dmac_info.channel[i];
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ch->id.INVALID = 0;
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ch->id.IDX = i;
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ch->id.KEYFRAME = dmac_info.keyframe;
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break;
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}
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cpu_atomic_end();
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if (ch != NULL)
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break;
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__asm__ volatile ("sleep");
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}
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return ch;
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}
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/* sh7305_dma_channel_release() : release DMA channel */
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static int sh7305_dma_channel_release(sh7305_dma_channel_t * ch, int atomic)
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{
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if (sh7305_dma_channel_wait(ch, atomic) != 0)
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return -1;
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ch->id.INVALID = 1;
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return 0;
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}
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/* sh7305_dma_channel_find() : find a channel using the ID */
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sh7305_dma_channel_t *sh7305_dma_channel_find(sh7305_dma_id_t id)
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{
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if (id.INVALID == 1)
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return NULL;
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if (id.IDX < 0 && id.IDX >= 6)
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return NULL;
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return &dmac_info.channel[id.IDX];
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}
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/* sh7305_dma_wait() : wait DAM channel */
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int sh7305_dma_channel_wait(sh7305_dma_channel_t *ch, int atomic)
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{
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int find;
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find = -1;
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cpu_atomic_start();
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for (int i = 0; i < 6; ++i) {
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if (ch != &dmac_info.channel[i])
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continue;
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find = 0;
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break;
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}
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cpu_atomic_end();
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if (find != 0)
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return find;
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while (1) {
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if (ch->hw->CHCR.DE == 0)
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break;
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if (atomic == 1)
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__asm__ volatile ("sleep");
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}
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return 0;
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}
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#define DMA SH7305_DMA
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//#define POWER SH7305_POWER
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typedef volatile struct __sh7305_dma_channel channel_t;
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//---
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// Driver public API
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//---
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static channel_t *sh7305_dma_channel(int channel)
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{
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if (channel < 0 || channel >= 6)
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return NULL;
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return (channel_t *[6]){
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&DMA.DMA0, &DMA.DMA1, &DMA.DMA2,
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&DMA.DMA3, &DMA.DMA4, &DMA.DMA5,
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}[channel];
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}
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/* sh7305_dma_transfert_async() : start asynchronous transfert */
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dma_id_t sh7305_dma_transfert_async(
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uintptr_t src, dma_addr_op_t src_op,
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uintptr_t dst, dma_addr_op_t dst_op,
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dma_block_size_t block_size,
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int block_count
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) {
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sh7305_dma_channel_t *ch;
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static void sh7305_dma_spinwait(channel_t *ch)
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{
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(void)ch;
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ch = sh7305_dma_channel_reserve();
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if (ch == NULL)
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return -1;
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/* disable channel */
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ch->hw->CHCR.DE = 0;
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/* set source / destination address and block counter */
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ch->hw->SAR = sh7305_dma_translate_addr(src);
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ch->hw->DAR = sh7305_dma_translate_addr(dst);
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ch->hw->TCR = block_count & 0x0fffffff;
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/* common channel configuration
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<> enable release of the bus mastership between reading and writting
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<> select normal mode (channel 0..3)
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<> select asynchronous DREQ sampling (channel 0)
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<> detect overrun 0 (channel 0)
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<> clear half-end flags
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<> disable half-end interruption
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<> select DACK output at read cycle (channel 0)
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<> select low-active output of DACK (channel 0)
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<> set the approriate destination addressing mode
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<> set the approriate source addressing mode
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<> select auto-request transfert
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<> select DREQ detection on low-level (channel 0)
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<> select cycle steal mode
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<> enable interruption
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<> clear interrupt flags */
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ch->hw->CHCR.LCKN = 1;
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ch->hw->CHCR.RPT = 0b000;
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ch->hw->CHCR.DA = 0;
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ch->hw->CHCR.DO = 0;
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ch->hw->CHCR.HE = 0;
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ch->hw->CHCR.HIE = 0;
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ch->hw->CHCR.AM = 0;
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ch->hw->CHCR.AL = 0;
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ch->hw->CHCR.DM = dst_op;
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ch->hw->CHCR.SM = src_op;
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ch->hw->CHCR.RS = 0b0100;
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ch->hw->CHCR.DL = 0;
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ch->hw->CHCR.DS = 0;
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ch->hw->CHCR.TB = 0;
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ch->hw->CHCR.IE = 1;
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ch->hw->CHCR.TE = 0;
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/* set the block size */
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ch->hw->CHCR.TS3 = (block_size & 0b1000) >> 3;
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ch->hw->CHCR.TS2 = (block_size & 0b0100) >> 2;
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ch->hw->CHCR.TS1 = (block_size & 0b0010) >> 1;
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ch->hw->CHCR.TS0 = (block_size & 0b0001) >> 0;
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/* start DMA channel */
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ch->hw->CHCR.DE = 1;
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return ch->id.lword;
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}
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//---
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@ -33,9 +255,43 @@ static void sh7305_dma_spinwait(channel_t *ch)
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//---
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/* Interrupt handler for all finished DMA transfers */
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static void sh7305_dma_interrupt_transfer_ended(channel_t *ch)
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static void sh7305_dma_interrupt_transfer_ended(sh7305_dma_channel_t *ch)
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{
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(void)ch;
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ch->hw->CHCR.IE = 0;
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ch->hw->CHCR.DE = 0;
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ch->hw->CHCR.TE = 0;
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SH7305_DMA.DMAOR.AE = 0;
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SH7305_DMA.DMAOR.NMIF = 0;
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ch->id.INVALID = 1;
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}
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/* DMA error handler (interrupt) */
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static void sh7305_dma_error_handler(void)
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{
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||||
dclear(C_WHITE);
|
||||
dprint(0, 0, C_BLACK,
|
||||
"DMA error handler !!!\n"
|
||||
" DMA0.CHCR = %p\n"
|
||||
" DMA1.CHCR = %p\n"
|
||||
" DMA2.CHCR = %p\n"
|
||||
" DMA3.CHCR = %p\n"
|
||||
" DMA4.CHCR = %p\n"
|
||||
" DMA5.CHCR = %p\n"
|
||||
" DMAOR = %p\n"
|
||||
"reset the device..."
|
||||
,
|
||||
SH7305_DMA.DMA0.CHCR.lword,
|
||||
SH7305_DMA.DMA1.CHCR.lword,
|
||||
SH7305_DMA.DMA2.CHCR.lword,
|
||||
SH7305_DMA.DMA3.CHCR.lword,
|
||||
SH7305_DMA.DMA4.CHCR.lword,
|
||||
SH7305_DMA.DMA5.CHCR.lword,
|
||||
SH7305_DMA.DMAOR.word
|
||||
);
|
||||
dupdate();
|
||||
while (1) { __asm__ volatile ("sleep"); }
|
||||
}
|
||||
|
||||
//---
|
||||
|
|
@ -44,7 +300,7 @@ static void sh7305_dma_interrupt_transfer_ended(channel_t *ch)
|
|||
|
||||
//FIXME: avoid manualy sync DMAOR with header o(x_x)o
|
||||
struct dma_ctx {
|
||||
channel_t ch[6];
|
||||
volatile struct __sh7305_dma_channel ch[6];
|
||||
word_union(DMAOR,
|
||||
uint16_t CMS :4; /* Cycle steal Mode Select */
|
||||
|
||||
|
|
@ -73,8 +329,8 @@ static void __dma_configure(struct dma_ctx *s)
|
|||
sh7305_intc_install_inth_generic(
|
||||
codes[i],
|
||||
VHEX_CALL(
|
||||
sh7305_dma_interrupt_transfer_ended,
|
||||
(void*)sh7305_dma_channel(i)
|
||||
&sh7305_dma_interrupt_transfer_ended,
|
||||
(void*)&dmac_info.channel[i]
|
||||
)
|
||||
);
|
||||
|
||||
|
|
@ -83,22 +339,27 @@ static void __dma_configure(struct dma_ctx *s)
|
|||
s->ch[i].TCR = 0x00000000;
|
||||
|
||||
s->ch[i].CHCR.DE = 0;
|
||||
|
||||
dmac_info.channel[i].id.INVALID = 1;
|
||||
}
|
||||
|
||||
/* Configure the DMA operations
|
||||
<> select normal cycle steal mode
|
||||
<> select "normal" priority (CH0->CH1->CH2->...)
|
||||
<> select round-robin mode
|
||||
<> clear address error flags
|
||||
<> clear NMIF flags
|
||||
<> enable the master switch */
|
||||
s->DMAOR.CMS = 0b0000;
|
||||
s->DMAOR.PR = 0b00;
|
||||
s->DMAOR.PR = 0b11;
|
||||
s->DMAOR.AE = 0;
|
||||
s->DMAOR.NMIF = 0;
|
||||
s->DMAOR.DME = 1;
|
||||
|
||||
/* Install Address Error interrupt gate */
|
||||
sh7305_intc_install_inth_gate(0xbc0, sh7305_dma_inth_ae, 32);
|
||||
sh7305_intc_install_inth_generic(
|
||||
0xbc0,
|
||||
VHEX_CALL(&sh7305_dma_error_handler)
|
||||
);
|
||||
|
||||
/* Set interrupt priority to 3, except for the channels that are
|
||||
used by the USB driver (channel 0) */
|
||||
|
|
@ -114,37 +375,40 @@ static void __dma_configure(struct dma_ctx *s)
|
|||
/* __rtc_hsave() : save hardware information */
|
||||
static void __dma_hsave(struct dma_ctx *s)
|
||||
{
|
||||
sh7305_dma_channel_t * ch;
|
||||
|
||||
for(int i = 0; i < 6; i++) {
|
||||
channel_t *ch = sh7305_dma_channel(i);
|
||||
sh7305_dma_spinwait(ch);
|
||||
ch->SAR = s->ch[i].SAR;
|
||||
ch->DAR = s->ch[i].DAR;
|
||||
ch->TCR = s->ch[i].TCR;
|
||||
ch->CHCR.lword = s->ch[i].CHCR.lword;
|
||||
ch = &dmac_info.channel[i];
|
||||
sh7305_dma_channel_wait(ch, 1);
|
||||
s->ch[i].SAR = ch->hw->SAR;
|
||||
s->ch[i].DAR = ch->hw->DAR;
|
||||
s->ch[i].TCR = ch->hw->TCR;
|
||||
s->ch[i].CHCR.lword = ch->hw->CHCR.lword;
|
||||
}
|
||||
|
||||
DMA.DMAOR.word = s->DMAOR.word;
|
||||
s->DMAOR.word = SH7305_DMA.DMAOR.word;
|
||||
}
|
||||
|
||||
/* __dma_hrestore() : restore hardware information */
|
||||
static void __dma_hrestore(struct dma_ctx *s)
|
||||
{
|
||||
DMA.DMAOR.DME = 0;
|
||||
sh7305_dma_channel_t * ch;
|
||||
|
||||
SH7305_DMA.DMAOR.DME = 0;
|
||||
|
||||
for(int i = 0; i < 6; i++)
|
||||
{
|
||||
channel_t *ch = sh7305_dma_channel(i);
|
||||
ch->SAR = s->ch[i].SAR;
|
||||
ch->DAR = s->ch[i].DAR;
|
||||
ch->TCR = s->ch[i].TCR;
|
||||
ch->CHCR.lword = s->ch[i].CHCR.lword;
|
||||
ch = &dmac_info.channel[i];
|
||||
ch->hw->SAR = s->ch[i].SAR;
|
||||
ch->hw->DAR = s->ch[i].DAR;
|
||||
ch->hw->TCR = s->ch[i].TCR;
|
||||
ch->hw->CHCR.lword = s->ch[i].CHCR.lword;
|
||||
}
|
||||
|
||||
DMA.DMAOR.word = s->DMAOR.word;
|
||||
SH7305_DMA.DMAOR.word = s->DMAOR.word;
|
||||
}
|
||||
|
||||
#if 0
|
||||
struct vhex_driver drv_rtc = {
|
||||
struct vhex_driver drv_dma = {
|
||||
.name = "DMA",
|
||||
.hsave = (void*)&__dma_hsave,
|
||||
.hrestore = (void*)&__dma_hrestore,
|
||||
|
|
@ -155,6 +419,11 @@ struct vhex_driver drv_rtc = {
|
|||
.SHARED = 0,
|
||||
.UNUSED = 0,
|
||||
},
|
||||
.module_data = &(struct dma_drv_interface){
|
||||
.dma_memcpy = &sh7305_dma_memcpy,
|
||||
.dma_memset = &sh7305_dma_memset,
|
||||
.dma_wait = &sh7305_dma_wait,
|
||||
.dma_spinwait = &sh7305_dma_spinwait
|
||||
}
|
||||
};
|
||||
VHEX_DECLARE_DRIVER(05, drv_dma);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,9 +1,79 @@
|
|||
#include <vhex/driver/mpu/sh/sh7305/dma.h>
|
||||
#include <vhex/dma.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
/* dma_memcpy() : memcpy using DMA */
|
||||
dma_id_t sh7305_dma_memcpy(void * restrict dst, void * restrict src, size_t sz)
|
||||
{
|
||||
(void)dst;
|
||||
(void)src;
|
||||
(void)sz;
|
||||
uintptr_t _dst;
|
||||
uintptr_t _src;
|
||||
uintptr_t dma_src;
|
||||
uintptr_t dma_dst;
|
||||
ptrdiff_t delta;
|
||||
int dma_block_count;
|
||||
dma_block_size_t dma_block_size;
|
||||
int divisor;
|
||||
ptrdiff_t gap_size_pre;
|
||||
ptrdiff_t gap_size_end;
|
||||
dma_id_t id;
|
||||
|
||||
if (sz < 64) {
|
||||
memcpy(dst, src, sz);
|
||||
return 0;
|
||||
}
|
||||
|
||||
_dst = (uintptr_t)dst;
|
||||
_src = (uintptr_t)src;
|
||||
|
||||
delta = (dst > src) ? dst - src : src - dst;
|
||||
if ((delta & 0x0000001f) == 0) {
|
||||
dma_block_size = DMA_BLOCK_SIZE_32B;
|
||||
divisor = 32;
|
||||
} else if ((delta & 0x0000000f) == 0) {
|
||||
dma_block_size = DMA_BLOCK_SIZE_16B;
|
||||
divisor = 16;
|
||||
} else if ((delta & 0x00000007) == 0) {
|
||||
dma_block_size = DMA_BLOCK_SIZE_8B;
|
||||
divisor = 8;
|
||||
} else if ((delta & 0x00000003) == 0) {
|
||||
dma_block_size = DMA_BLOCK_SIZE_4B;
|
||||
divisor = 4;
|
||||
} else if ((delta & 0x00000001) == 0) {
|
||||
dma_block_size = DMA_BLOCK_SIZE_2B;
|
||||
divisor = 2;
|
||||
} else {
|
||||
dma_block_size = DMA_BLOCK_SIZE_1B;
|
||||
divisor = 1;
|
||||
}
|
||||
|
||||
dma_src = ((_src + divisor - 1) / divisor) * divisor;
|
||||
dma_dst = ((_dst + divisor - 1) / divisor) * divisor;
|
||||
gap_size_pre = dma_dst - _dst;
|
||||
dma_block_count = (sz - gap_size_pre) / divisor;
|
||||
gap_size_end = (sz - gap_size_pre) - (dma_block_count * divisor);
|
||||
|
||||
id = sh7305_dma_transfert_async(
|
||||
dma_src, DMA_ADDR_INC,
|
||||
dma_dst, DMA_ADDR_INC,
|
||||
dma_block_size,
|
||||
dma_block_count
|
||||
);
|
||||
if (id < 0)
|
||||
return id;
|
||||
|
||||
for (int i = 0; i < gap_size_pre; ++i) {
|
||||
((uint8_t*)_dst)[0] = ((uint8_t*)_src)[0];
|
||||
_dst += 1;
|
||||
_src += 1;
|
||||
}
|
||||
_dst += dma_block_count * divisor;
|
||||
_src += dma_block_count * divisor;
|
||||
for (int i = 0; i < gap_size_end; ++i) {
|
||||
((uint8_t*)_dst)[0] = ((uint8_t*)_src)[0];
|
||||
_dst += 1;
|
||||
_src += 1;
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,9 +1,66 @@
|
|||
#include <vhex/driver/mpu/sh/sh7305/dma.h>
|
||||
#include <vhex/dma.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
/* Allocate a 32-byte buffer in ILRAM */
|
||||
VALIGNED(32) VSECTION(".xram") static uint32_t Xbuf[8];
|
||||
|
||||
/* dma_memset() : memset using the DMA */
|
||||
dma_id_t sh7305_dma_memset(void *dst, int c, size_t sz)
|
||||
{
|
||||
(void)dst;
|
||||
(void)c;
|
||||
(void)sz;
|
||||
uintptr_t dma_src;
|
||||
uintptr_t dma_dst;
|
||||
ptrdiff_t gap_size_pre;
|
||||
ptrdiff_t gap_size_end;
|
||||
uint32_t mask;
|
||||
int dma_block_count;
|
||||
dma_id_t id;
|
||||
|
||||
if (sz < 64) {
|
||||
memset(dst, c, sz);
|
||||
return 0;
|
||||
}
|
||||
|
||||
mask = ((c & 0xff) << 24)
|
||||
| ((c & 0xff) << 16)
|
||||
| ((c & 0xff) << 8)
|
||||
| ((c & 0xff) << 0);
|
||||
|
||||
/* Prepare the XRAM buffer. We need to use XRAM because the DMA will
|
||||
have to read the operand once per block, as opposed to an assembler
|
||||
routine that would hold it in a register. If we place it in RAM, the
|
||||
DMA will perform twice as many RAM accesses as the handwritten
|
||||
assembler, which would be very slow. By using XRAM we use two
|
||||
different memory regions, making the DMA faster than the CPU. */
|
||||
for(int i = 0; i < 8; i++) Xbuf[i] = mask;
|
||||
|
||||
//FIXME: SPU
|
||||
|
||||
dma_src = (uintptr_t)Xbuf;
|
||||
dma_dst = (uintptr_t)dst & 0xffffffe0;
|
||||
gap_size_pre = dma_dst - (uintptr_t)dst;
|
||||
dma_block_count = (sz - gap_size_pre) >> 5;
|
||||
gap_size_end = (sz - gap_size_pre) - (dma_block_count << 5);
|
||||
|
||||
id = sh7305_dma_transfert_async(
|
||||
dma_src, DMA_ADDR_FIXED,
|
||||
dma_dst, DMA_ADDR_INC,
|
||||
DMA_BLOCK_SIZE_32B,
|
||||
dma_block_count
|
||||
);
|
||||
if (id < 0)
|
||||
return id;
|
||||
|
||||
for (int i = 0; i < gap_size_pre; ++i) {
|
||||
((uint8_t*)dst)[0] = c;
|
||||
dst = &((uint8_t*)dst)[1];
|
||||
}
|
||||
dst += dma_block_count << 5;
|
||||
for (int i = 0; i < gap_size_end; ++i) {
|
||||
((uint8_t*)dst)[0] = c;
|
||||
dst = &((uint8_t*)dst)[1];
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
#include <vhex/driver/mpu/sh/sh7305/dma.h>
|
||||
|
||||
//---
|
||||
// Internal functions
|
||||
//---
|
||||
|
||||
static int sh7305_dma_wait_core(sh7305_dma_id_t id, int atomic)
|
||||
{
|
||||
sh7305_dma_channel_t *ch;
|
||||
|
||||
ch = sh7305_dma_channel_find(id);
|
||||
if (ch == NULL)
|
||||
return -1;
|
||||
|
||||
if (ch->id.KEYFRAME == id.KEYFRAME)
|
||||
sh7305_dma_channel_wait(ch, atomic);
|
||||
return 0;
|
||||
}
|
||||
|
||||
//---
|
||||
// User-level API
|
||||
//---
|
||||
|
||||
/* dma_wait() : wait the end of the DMA channel transfer */
|
||||
int sh7305_dma_wait(dma_id_t id)
|
||||
{
|
||||
sh7305_dma_id_t _id;
|
||||
|
||||
_id.lword = id;
|
||||
return sh7305_dma_wait_core(_id, 0);
|
||||
}
|
||||
|
||||
/* dma_wait() : wait the end of the DMA channel transfer without interruption */
|
||||
int sh7305_dma_spinwait(dma_id_t id)
|
||||
{
|
||||
sh7305_dma_id_t _id;
|
||||
|
||||
_id.lword = id;
|
||||
return sh7305_dma_wait_core(_id, 1);
|
||||
}
|
||||
|
|
@ -128,15 +128,14 @@ void *sh7305_intc_install_inth_generic(int event_code, vhex_call_t callback)
|
|||
|
||||
uint8_t *h = sh7305_intc_install_inth_gate(
|
||||
event_code,
|
||||
sh7305_intc_inth_generic_gate,
|
||||
&sh7305_intc_inth_generic_gate,
|
||||
32
|
||||
);
|
||||
if(h == NULL)
|
||||
return false;
|
||||
|
||||
memcpy(&h[8], &callback, 20);
|
||||
memcpy(&h[28], &sh7305_inth_callback, 4);
|
||||
|
||||
if(h != NULL) {
|
||||
uintptr_t workaround = (uintptr_t)&sh7305_inth_callback;
|
||||
memcpy(&h[8], &callback, 20);
|
||||
memcpy(&h[28], &workaround, 4);
|
||||
}
|
||||
return h;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue