531 lines
20 KiB
C
531 lines
20 KiB
C
#ifndef __VHEX_MPU_SH7305_USB__
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# define __VHEX_MPU_SH7305_USB__
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#include <vhex/defs/attributes.h>
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#include <vhex/defs/types.h>
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struct __sh7305_usb
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{
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/* SYSCFG - System Configuration Control Register */
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word_union(SYSCFG,
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uint16_t const : 5;
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uint16_t SCKE : 1; /* USB clock module controller */
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uint16_t const : 1;
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uint16_t const : 1;
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uint16_t HSE : 1; /* High-speed operations enable */
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uint16_t DCFM : 1; /* Function controller */
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uint16_t DRPD : 1; /* D+/- Resistor Control */
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uint16_t DPRPU : 1; /* D+ Resistor Control */
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uint16_t const : 3;
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uint16_t USBE : 1; /* USB operation enable */
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);
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/* BUSWAIT - CPU Bus Wait Setting Register */
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word_union(BUSWAIT,
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uint16_t const :12;
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uint16_t BWAIT : 4; /* CPU Bus wait */
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);
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/* SYSSTS - System Configuration Status Register
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* @notes
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* - emulator allows writting LNST */
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word_union(SYSSTS,
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uint16_t const : 5;
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uint16_t HIGH : 1; /* Should be 1 */
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uint16_t const : 8;
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uint16_t LNST : 2; /* USB Data Line Status */
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);
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pad(0x02);
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/* DVTSTCCTR - Device State Controle Register */
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word_union(DVSTCTR,
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uint16_t const : 7;
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uint16_t WKUP : 1; /* Wakeup Output */
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uint16_t RWUPE : 1; /* Wakeup Detection Enable */
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uint16_t USBRT : 1; /* USB Reset Output */
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uint16_t RESUME : 1; /* Resume Output */
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uint16_t UACT : 1; /* USB Bus Enable */
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uint16_t const : 1;
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uint16_t RHST : 3; /* Reset Handshake */
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);
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pad(0x02);
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/* TESTMODE - Test Mode Register */
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word_union(TESTMODE,
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uint16_t const :12;
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uint16_t UTST : 4; /* Test Mode */
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);
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pad(0x06);
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/* [C/Dx]FIFO - FIFO Port Registers */
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uint32_t CFIFO; /* DCP FIFO port */
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uint32_t D0FIFO; /* Data 0 FIFO port */
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uint32_t D1FIFO; /* Data 1 FIFO port */
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/* CFIFOSEL - FIFO Port Select Register
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* @notes
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* - emulator register mask is 0xcd4f
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* - physical (and SH7724) mask is 0xcd2f (ISEL shifted) */
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word_union(CFIFOSEL,
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uint16_t RCNT : 1; /* Read Count Mode */
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uint16_t REW : 1; /* Pointer Buffer Rewind */
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uint16_t const : 2;
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uint16_t MBW : 2; /* Access Bits Width */
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uint16_t const : 1;
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uint16_t BIGEND : 1; /* Endiant Control */
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uint16_t const : 2;
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uint16_t ISEL : 1; /* Access Direction When DCP is used */
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uint16_t const : 1;
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uint16_t CURPIPE :4; /* Port Access Pipe Specification */
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);
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/* CFIFOCTR - FIFO Port Control Register */
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word_union(CFIFOCTR,
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uint16_t BVAL : 1; /* Buffer Memory Valid Flags */
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uint16_t BCLR : 1; /* CPU Buffer Clear */
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uint16_t FRDY : 1; /* FIFO Port Ready */
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uint16_t const : 1;
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uint16_t DTLN :12; /* Receive Data Length */
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);
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pad(0x04);
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/* D0FIFOSEL - FIFO Port Select Register */
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word_union(D0FIFOSEL,
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uint16_t RCNT : 1; /* Read Count Mode */
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uint16_t REW : 1; /* Pointer Buffer Rewind */
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uint16_t DCLRM : 1; /* Auto Buffer Clear Mode */
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uint16_t DREQE : 1; /* DMA Transfert Request Enable */
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uint16_t MBW : 2; /* Access Bits Width */
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uint16_t const : 1;
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uint16_t BIGEND : 1; /* Endiant Control */
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uint16_t const : 4;
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uint16_t CURPIPE :4; /* Port Access Pipe Specification */
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);
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/* D0FIFOCTR - FIFO Port Control Register */
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word_union(D0FIFOCTR,
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uint16_t BVAL : 1; /* Buffer Memory Valid Flags */
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uint16_t BCLR : 1; /* CPU Buffer Clear */
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uint16_t FRDY : 1; /* FIFO Port Ready */
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uint16_t const : 1;
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uint16_t DTLN :12; /* Receive Data Length */
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);
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/* D1FIFOSEL - FIFO Port Select Register */
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word_union(D1FIFOSEL,
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uint16_t RCNT : 1; /* Read Count Mode */
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uint16_t REW : 1; /* Pointer Buffer Rewind */
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uint16_t DCLRM : 1; /* Auto Buffer Clear Mode */
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uint16_t DREQE : 1; /* DMA Transfert Request Enable */
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uint16_t MBW : 2; /* Access Bits Width */
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uint16_t const : 1;
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uint16_t BIGEND : 1; /* Endiant Control */
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uint16_t const : 4;
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uint16_t CURPIPE :4; /* Port Access Pipe Specification */
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);
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/* D1FIFOCTR - FIFO Port Control Register */
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word_union(D1FIFOCTR,
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uint16_t BVAL : 1; /* Buffer Memory Valid Flags */
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uint16_t BCLR : 1; /* CPU Buffer Clear */
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uint16_t FRDY : 1; /* FIFO Port Ready */
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uint16_t const : 1;
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uint16_t DTLN :12; /* Receive Data Length */
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);
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/* INTENB0 - Interrupt Enable Register */
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word_union(INTENB0,
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uint16_t VBSE : 1; /* VBUS */
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uint16_t RSME : 1; /* Resume */
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uint16_t SOFE : 1; /* Frame Number Update */
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uint16_t DVSE : 1; /* Device State Transition */
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uint16_t CTRE : 1; /* Control Transfert Stage Transition */
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uint16_t BEMPE : 1; /* Buffer Empty */
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uint16_t NRDYE : 1; /* Buffer Not Ready */
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uint16_t BRDYE : 1; /* Buffer Ready */
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uint16_t const : 8;
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);
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pad(4);
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/* BRDYENB - BRDY Interrupt Enable Register */
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word_union(BRDYENB,
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uint16_t const :6;
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uint16_t PIPE9BRDYE :1; /* BRDY Interrupt enable for PIPE9 */
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uint16_t PIPE8BRDYE :1; /* BRDY Interrupt enable for PIPE8 */
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uint16_t PIPE7BRDYE :1; /* BRDY Interrupt enable for PIPE7 */
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uint16_t PIPE6BRDYE :1; /* BRDY Interrupt enable for PIPE6 */
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uint16_t PIPE5BRDYE :1; /* BRDY Interrupt enable for PIPE5 */
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uint16_t PIPE4BRDYE :1; /* BRDY Interrupt enable for PIPE4 */
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uint16_t PIPE3BRDYE :1; /* BRDY Interrupt enable for PIPE3 */
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uint16_t PIPE2BRDYE :1; /* BRDY Interrupt enable for PIPE2 */
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uint16_t PIPE1BRDYE :1; /* BRDY Interrupt enable for PIPE1 */
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uint16_t PIPE0BRDYE :1; /* BRDY Interrupt enable for PIPE0 */
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);
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/* NRDYENB - NRDY Interrupt Enable Register */
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word_union(NRDYENB,
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uint16_t const :6;
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uint16_t PIPE9NRDYE :1; /* NRDY Interrupt enable for PIPE9 */
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uint16_t PIPE8NRDYE :1; /* NRDY Interrupt enable for PIPE8 */
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uint16_t PIPE7NRDYE :1; /* NRDY Interrupt enable for PIPE7 */
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uint16_t PIPE6NRDYE :1; /* NRDY Interrupt enable for PIPE6 */
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uint16_t PIPE5NRDYE :1; /* NRDY Interrupt enable for PIPE5 */
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uint16_t PIPE4NRDYE :1; /* NRDY Interrupt enable for PIPE4 */
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uint16_t PIPE3NRDYE :1; /* NRDY Interrupt enable for PIPE3 */
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uint16_t PIPE2NRDYE :1; /* NRDY Interrupt enable for PIPE2 */
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uint16_t PIPE1NRDYE :1; /* NRDY Interrupt enable for PIPE1 */
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uint16_t PIPE0NRDYE :1; /* NRDY Interrupt enable for PIPE0 */
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);
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/* BEMPENB - BEMP Interrupt Enable Register */
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word_union(BEMPENB,
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uint16_t const :6;
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uint16_t PIPE9BEMPE :1; /* BEMP Interrupt enable for PIPE9 */
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uint16_t PIPE8BEMPE :1; /* BEMP Interrupt enable for PIPE8 */
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uint16_t PIPE7BEMPE :1; /* BEMP Interrupt enable for PIPE7 */
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uint16_t PIPE6BEMPE :1; /* BEMP Interrupt enable for PIPE6 */
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uint16_t PIPE5BEMPE :1; /* BEMP Interrupt enable for PIPE5 */
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uint16_t PIPE4BEMPE :1; /* BEMP Interrupt enable for PIPE4 */
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uint16_t PIPE3BEMPE :1; /* BEMP Interrupt enable for PIPE3 */
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uint16_t PIPE2BEMPE :1; /* BEMP Interrupt enable for PIPE2 */
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uint16_t PIPE1BEMPE :1; /* BEMP Interrupt enable for PIPE1 */
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uint16_t PIPE0BEMPE :1; /* BEMP Interrupt enable for PIPE0 */
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);
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/* SOFCFG - SOF Control Register */
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word_union(SOFCFG,
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uint16_t :7;
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uint16_t TRNENSEL :1; /* Transaction-Enabled Time Select */
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uint16_t :1;
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uint16_t BRDYM :1; /* BRDY Status Clear Timing */
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uint16_t HIGH :1; /* SHOULD BE SET TO 1 MANUALLY */
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uint16_t :5;
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);
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pad(2);
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/* Interrupt Status Registers */
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word_union(INTSTS0,
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uint16_t VBINT : 1; /* VBUS */
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uint16_t RESM : 1; /* Resume */
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uint16_t SOFR : 1; /* Frame Number Refresh */
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uint16_t DVST : 1; /* Device State Transition */
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uint16_t CTRT : 1; /* Control Transfer Stage Transition */
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uint16_t BEMP : 1; /* Buffer Empty */
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uint16_t NRDY : 1; /* Buffer Not Ready */
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uint16_t BRDY : 1; /* Buffer Ready */
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uint16_t VBSTS : 1; /* VBUS Input Status */
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uint16_t DVSQ : 3; /* Device state */
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uint16_t VALID : 1; /* USB Request Reception */
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uint16_t CTSQ : 3; /* Control Transfer Stage */
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);
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pad(4);
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/* BRDYENB - BRDY Interrupt Status Register */
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word_union(BRDYSTS,
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uint16_t const :6;
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uint16_t PIPE9BRDY :1; /* BRDY Interrupt Status for PIPE9 */
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uint16_t PIPE8BRDY :1; /* BRDY Interrupt Status for PIPE8 */
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uint16_t PIPE7BRDY :1; /* BRDY Interrupt Status for PIPE7 */
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uint16_t PIPE6BRDY :1; /* BRDY Interrupt Status for PIPE6 */
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uint16_t PIPE5BRDY :1; /* BRDY Interrupt Status for PIPE5 */
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uint16_t PIPE4BRDY :1; /* BRDY Interrupt Status for PIPE4 */
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uint16_t PIPE3BRDY :1; /* BRDY Interrupt Status for PIPE3 */
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uint16_t PIPE2BRDY :1; /* BRDY Interrupt Status for PIPE2 */
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uint16_t PIPE1BRDY :1; /* BRDY Interrupt Status for PIPE1 */
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uint16_t PIPE0BRDY :1; /* BRDY Interrupt Status for PIPE0 */
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);
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/* NRDYENB - NRDY Interrupt Status Register */
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word_union(NRDYSTS,
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uint16_t const :6;
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uint16_t PIPE9NRDY :1; /* NRDY Interrupt Status for PIPE9 */
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uint16_t PIPE8NRDY :1; /* NRDY Interrupt Status for PIPE8 */
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uint16_t PIPE7NRDY :1; /* NRDY Interrupt Status for PIPE7 */
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uint16_t PIPE6NRDY :1; /* NRDY Interrupt Status for PIPE6 */
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uint16_t PIPE5NRDY :1; /* NRDY Interrupt Status for PIPE5 */
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uint16_t PIPE4NRDY :1; /* NRDY Interrupt Status for PIPE4 */
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uint16_t PIPE3NRDY :1; /* NRDY Interrupt Status for PIPE3 */
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uint16_t PIPE2NRDY :1; /* NRDY Interrupt Status for PIPE2 */
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uint16_t PIPE1NRDY :1; /* NRDY Interrupt Status for PIPE1 */
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uint16_t PIPE0NRDY :1; /* NRDY Interrupt Status for PIPE0 */
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);
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/* BEMPENB - BEMP Interrupt Status Register */
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word_union(BEMPSTS,
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uint16_t const :6;
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uint16_t PIPE9BEMP :1; /* BEMP Interrupt Status for PIPE9 */
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uint16_t PIPE8BEMP :1; /* BEMP Interrupt Status for PIPE8 */
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uint16_t PIPE7BEMP :1; /* BEMP Interrupt Status for PIPE7 */
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uint16_t PIPE6BEMP :1; /* BEMP Interrupt Status for PIPE6 */
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uint16_t PIPE5BEMP :1; /* BEMP Interrupt Status for PIPE5 */
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uint16_t PIPE4BEMP :1; /* BEMP Interrupt Status for PIPE4 */
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uint16_t PIPE3BEMP :1; /* BEMP Interrupt Status for PIPE3 */
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uint16_t PIPE2BEMP :1; /* BEMP Interrupt Status for PIPE2 */
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uint16_t PIPE1BEMP :1; /* BEMP Interrupt Status for PIPE1 */
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uint16_t PIPE0BEMP :1; /* BEMP Interrupt Status for PIPE0 */
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);
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/* FRMNUM - Frame Number Register */
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word_union(FRMNUM,
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uint16_t OVRN : 1; /* Overrun/Underrun Detection Status */
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uint16_t CRCE : 1; /* Receive Data Error */
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uint16_t : 3;
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uint16_t FRNM :11; /* Frame Number */
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);
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/* UFRMNUM - uFrame Number Register */
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word_union(UFRMNUM,
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uint16_t :13;
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uint16_t UFRNM : 3; /* uFrame */
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);
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/* USBADDR - USB Address Register
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* @notes
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* - emulator allow writting to this register but is probably only for
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* register initialization */
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word_union(USBADDR,
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uint16_t : 9;
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uint16_t USBADDR : 7; /* USB Address */
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);
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pad(2);
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/* USBREQ - USB Request Type Register */
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word_union(USBREQ,
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uint16_t BREQUEST :8; /* USB request data value */
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uint16_t BMREQUEST :8; /* USB request type value */
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);
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/* USBVAL - USB Request Value Register */
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word_union(USBVAL,
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uint16_t WVALUE :16; /* USB request wValue value */
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);
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/* USBINDX - USB Request Index Register */
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word_union(USBINDX,
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uint16_t WINDEX :16; /* USB USB request wIndex value */
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);
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/* USBLENG - USB Request Length Register */
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word_union(USBLENG,
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uint16_t WLENGTH :16; /* USB USB request wLength value */
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);
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/* DCPCFG - DCP Configuration Register */
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word_union(DCPCFG,
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uint16_t :11;
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uint16_t DIR : 1; /* Transfer Direction */
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uint16_t : 4;
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);
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/* DCPMAXP - DCP Maximum Packet Size Register */
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word_union(DCPMAXP,
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uint16_t DEVSEL : 4; /* Device Select */
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uint16_t : 5;
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uint16_t MXPS : 7; /* Maximum Packet Size */
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);
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/* DCPCTR - DCP Control Register */
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word_union(DCPCTR,
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uint16_t BSTS : 1; /* Buffer Status */
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uint16_t SUREQ : 1; /* SETUP Token Transmission */
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uint16_t CSCLR : 1; /* C-SPLIT Status Clear */
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uint16_t CSSTS : 1; /* C-SPLIT Status */
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uint16_t SUREQCLR : 1; /* SUREQ Bit Clear */
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uint16_t : 2;
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uint16_t SQCLR : 1; /* Toggle Bit Clear */
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uint16_t SQSET : 1; /* Toggle Bit Set */
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uint16_t SQMON : 1; /* Sequence Toggle Bit Monitor */
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uint16_t PBUSY : 1; /* Pipe Busy */
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uint16_t PINGE : 1; /* PING Token Issue Enable */
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uint16_t : 1;
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uint16_t CCPL : 1; /* Control Transfer End Enable */
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uint16_t PID : 2; /* Response PID */
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);
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pad(2);
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/* PIPESEL - Pipe Window Select Register */
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word_union(PIPESEL,
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uint16_t :12;
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uint16_t PIPESEL : 4; /* Pipe Window Select */
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);
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pad(2);
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/* PIPECFG - Pipe Configuration Register */
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word_union(PIPECFG,
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uint16_t TYPE : 2; /* Transfer Type */
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uint16_t : 3;
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uint16_t BFRE : 1; /* BRDY Interrupt Operation Specification */
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uint16_t DBLB : 1; /* Double Buffer Mode */
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uint16_t CNTMD : 1; /* Continuous Transfer Mode */
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uint16_t SHTNAK : 1; /* Pipe Disabled at End of Transfer */
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uint16_t : 2;
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uint16_t DIR : 1; /* Transfer Direction */
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uint16_t EPNUM : 4; /* Endpoint Number */
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);
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/* PIPEBUF - Pipe Buffer Setting Register */
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word_union(PIPEBUF,
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uint16_t : 1;
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uint16_t BUFSIZE : 5; /* Buffer Size */
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uint16_t : 2;
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uint16_t BUFNMB : 8; /* Buffer Number */
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);
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/* PIPEMAXP - Pipe Maximum Packet Size Register */
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word_union(PIPEMAXP,
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uint16_t DEVSEL : 4; /* Device Select */
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uint16_t : 1;
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uint16_t MXPS :11; /* Maximum Packet Size */
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);
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/* PIPEPERI - Pipe Timing Control Register */
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word_union(PIPEPERI,
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uint16_t : 3;
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uint16_t IFIS : 1; /* Isochronous IN Buffer Flush */
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uint16_t : 9;
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uint16_t IITV : 3; /* Interval Error Detection Interval */
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);
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/* PIPECTR - PIPEn Control Registers
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* @notes
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* - PIPECTR1 mask = 0xf7e3
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* - PIPECTR2 mask = 0xf7e3
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* - PIPECTR3 mask = 0xf7e3
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* - PIPECTR4 mask = 0xf7e3
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* - PIPECTR5 mask = 0xf7e3
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* - PIPECTR6 mask = 0xb3e3
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* - PIPECTR7 mask = 0xb3e3
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* - PIPECTR8 mask = 0xb3e3
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* - PIPECTR9 mask = 0xb3e3 */
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word_union(PIPECTR[9],
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uint16_t BSTS : 1; /* Buffer Status */
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uint16_t INBUFM : 1; /* IN Buffer Monitor (PIPE1..5) */
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uint16_t CSCLR : 1; /* C-SPLIT Status Clear Bit */
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uint16_t CSSTS : 1; /* CSSTS Status Bit */
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uint16_t : 1;
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uint16_t ATREPM : 1; /* Auto Response Mode (PIPE1..5) */
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uint16_t ACLRM : 1; /* Auto Buffer Clear Mode */
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uint16_t SQCLR : 1; /* Toggle Bit Clear */
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uint16_t SQSET : 1; /* Toggle Bit Set */
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uint16_t SQMON : 1; /* Toggle Bit Confirmation */
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uint16_t PBUSY : 1; /* Pipe Busy */
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uint16_t : 3;
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uint16_t PID : 2; /* Response PID */
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);
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pad(14);
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/* PIPEnTRE - PIPEn Transaction Counter Enable Registers and */
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/* PIPEnTRN - PIPEn Transaction Counter Registers */
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struct {
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word_union(PIPEnTRE,
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uint16_t : 6;
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uint16_t TRENB : 1; /* Transaction Counter Enable */
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uint16_t TRCLR : 1; /* Transaction Counter Clear */
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uint16_t : 8;
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);
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word_union(PIPEnTRN,
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uint16_t TRCNT :16; /* Transaction Counter */
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);
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} PIPETR[5];
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};
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/* UPONCR - USB Power Control Register */
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union __sh7305_usb_uponcr
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{
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uint16_t word;
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struct {
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uint16_t const : 5;
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uint16_t UPON : 2; /* USB Power Control */
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uint16_t const : 9;
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} __attribute__((packed, aligned(2)));
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} __attribute__((packed, aligned(2)));
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|
|
|
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#define SH7305_USB (*(volatile struct __sh7305_usb *)0xa4d80000)
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#define SH7305_USB_UPONCR (*(volatile union __sh7305_usb_uponcr *)0xa40501d4)
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|
|
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//---
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|
// Kernel-level USB API
|
|
//---
|
|
|
|
/* SH7305_USB_DVSQ_* - device state value */
|
|
enum {
|
|
SH7305_USB_DVSQ_POWERED = 0,
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|
SH7305_USB_DVSQ_DEFAULT = 1,
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|
SH7305_USB_DVSQ_ADDRESS = 2,
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|
SH7305_USB_DVSQ_CONFIGURED = 3,
|
|
};
|
|
/* SH&SH7305_USB_REQT_* - device request value */
|
|
enum {
|
|
SH7305_USB_REQT_GET_STATUS = 0x00,
|
|
SH7305_USB_REQT_CLEAR_FEATURE = 0x01,
|
|
SH7305_USB_REQT_SET_FEATURE = 0x03,
|
|
SH7305_USB_REQT_SET_ADDRESS = 0x05,
|
|
SH7305_USB_REQT_GET_DESCRIPTOR = 0x06,
|
|
SH7305_USB_REQT_SET_DESCRIPTOR = 0x07,
|
|
SH7305_USB_REQT_GET_CONFIGURATION = 0x08,
|
|
SH7305_USB_REQT_SET_CONFIGURATION = 0x09,
|
|
};
|
|
|
|
/* sh7305_usb_hpowered() : check if the USB module is powered */
|
|
extern bool sh7305_usb_hpowered(void);
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|
|
|
/* sh7305_usb_hpoweron() : power on the USB module */
|
|
extern int sh7305_usb_hpoweron(void);
|
|
|
|
/* sh7305_usb_hpoweroff() : power off the USB module */
|
|
extern int sh7305_usb_hpoweroff(void);
|
|
|
|
|
|
/* sh7305_usb_interrupt_handler() : interrupt handler invoked by hardware */
|
|
extern void sh7305_usb_interrupt_handler(void);
|
|
|
|
/* sh7305_usb_request_handle() : handle USB request */
|
|
extern void sh7305_usb_request_handle(void);
|
|
|
|
#include <vhex/usb/configuration.h>
|
|
|
|
/* sh7305_usb_open() : power on the module and setup USB module */
|
|
extern int sh7305_usb_open(struct usb_full_device *device);
|
|
|
|
|
|
|
|
/* sh7305_pipe_find() : try to find a pipe */
|
|
extern int sh7305_usb_pipe_find(int type);
|
|
|
|
|
|
|
|
/* sh7305_usb_dcp_prepare() : prepare FIFO buffer */
|
|
extern void sh7305_usb_dcp_prepare(void);
|
|
|
|
/* sh7305_usb_dcp_write() : send data through DCP pipe */
|
|
extern int sh7305_usb_dcp_write(void *buffer, size_t n);
|
|
|
|
/* sh7305_usb_dcp_commit() : send data */
|
|
extern void sh7305_usb_dcp_commit(void);
|
|
|
|
|
|
//---
|
|
// Utils
|
|
//---
|
|
|
|
#include <vhex/driver/mpu/sh/sh7305/tmu.h>
|
|
#include <vhex/usb/logger.h>
|
|
#include <vhex/defs/call.h>
|
|
|
|
/* SH7305_USB_REG_SYN() : activly wait the condition. */
|
|
#define SH7305_USB_REG_SYNC(condition) ({ \
|
|
volatile int __trigger = 0; \
|
|
int __timer = sh7305_tmu_configure( \
|
|
100000 /*µs*/, \
|
|
VHEX_CALL_SET_STOP(&__trigger) \
|
|
); \
|
|
if(__timer >= 0) { timer_start(__timer); } \
|
|
while((condition) && __trigger == 0) { \
|
|
; \
|
|
} \
|
|
sh7305_tmu_stop(__timer); \
|
|
if(__trigger != 0) { \
|
|
usb_logger_write( \
|
|
"%s: %d: (" #condition ") holds\n", \
|
|
__FUNCTION__, \
|
|
__LINE__ \
|
|
); \
|
|
} \
|
|
})
|
|
|
|
/* SH7305_USB_INTSTS0_CLEAR() : clear interrup flags */
|
|
#define SH7305_USB_INTSTS0_CLEAR(field_name) ({ \
|
|
__typeof__(SH7305_USB.INTSTS0) __intsts0 = { .word = 0xffff }; \
|
|
__intsts0.field_name = 0; \
|
|
do SH7305_USB.INTSTS0 = __intsts0; \
|
|
while(SH7305_USB.INTSTS0.field_name != 0); \
|
|
})
|
|
|
|
#endif /*__VHEX_MPU_SH7305_USB_ */
|