131 lines
4.9 KiB
C
131 lines
4.9 KiB
C
#ifndef VXGOS_BOOTLOADER_RASPI3B_AUXILIARY_H
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#define VXGOS_BOOTLOADER_RASPI3B_AUXILIARY_H
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#include "raspi3b/utils.h"
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//---
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// BCM2837 Auxiliary peripheral
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//
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// @note
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// <> all of theses bits is based on the documentation on
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// https://cs140e.sergio.bz/docs/BCM2837-ARM-Peripherals.pdf
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// <> we use MSB instead of LSB packed struct because of the architecture
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// note that this cannot be modified with compiler flags.
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//---
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struct __bcm2837_aux
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{
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/* [0x00215000] pending interrupt flags */
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const u32_union(AUX_IRQ,
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uint32_t MiniUART :1; /* Enable Mini UART */
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uint32_t SPI1 :1; /* Enable SPI1 */
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uint32_t SPI2 :1; /* Enable SPI2 */
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uint32_t :29;
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);
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/* [0x00215004] enable auxialiary modules */
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u32_union(AUX_ENABLE,
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uint32_t MiniUART :1; /* Enable Mini UART */
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uint32_t SPI1 :1; /* Enable SPI1 */
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uint32_t SPI2 :1; /* Enable SPI2 */
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uint32_t :29;
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);
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pad(0x38);
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//---
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// Mini UART register
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//---
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/* [0x00215040] used to write or write data from the FIFOs. */
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u32_union(AUX_MU_IO,
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uint32_t DATA : 8;
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uint32_t :24;
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);
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/* [0x00215044] used to enable interrupts */
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u32_union(AUX_MU_IER,
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uint32_t RIE :1; /* Receive Interrupt Enable */
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uint32_t TIE :1; /* Transmit Interrupt Enable */
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uint32_t :30;
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);
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/* [0x00215048] Interrupt Status */
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u32_union(AUX_MU_IIR,
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uint32_t PENDING :1; /* =0 if pending interrupts */
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uint32_t TXFLUSH :1; /* Receiver holds valid byte */
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uint32_t RXFLUSH :1; /* Transmit holding register empty */
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uint32_t :3;
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uint32_t FIFO :2; /* FIFO enabled (TODO: check RX/TX) */
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uint32_t :24;
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);
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/* [0x0021504c] Control Line Data */
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u32_union(AUX_MU_LCR,
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uint32_t CHR :2; /* Character Length */
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uint32_t :4;
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uint32_t BREAK :1; /* Pull down the UART1_TX line */
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uint32_t DLAB :1; /* Give access to the Baudrate reg */
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uint32_t :24;
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);
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/* [0x00215050] Control the 'modem' signals */
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u32_union(AUX_MU_MCR,
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uint32_t :1;
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uint32_t RTS :1; /* Pull down the UART1_RTS line */
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uint32_t :30;
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);
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/* [0x00215054] Data Status */
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const u32_union(AUX_MU_LSR,
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uint32_t DRIE :1; /* Received Data Ready */
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uint32_t ORER :1; /* Overrrun Error */
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uint32_t :3;
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uint32_t TDFE :1; /* Transmitter Empty */
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uint32_t TDFI :1; /* Transmitter Idle */
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uint32_t :25;
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);
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/* [0x00215058] Data 'modem' status */
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const u32_union(AUX_MU_MSR,
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uint32_t :4;
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uint32_t CTS :1; /* Inverse of the UART1_CTS input */
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uint32_t :27;
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);
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/* [0x0021505c] Single Byte Storage */
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u32_union(AUX_MU_SCRATCH,
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uint32_t SCRATCH :8; /* SDC byte extra */
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uint32_t :24;
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);
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/* [0x00215060] Access to Extra features */
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u32_union(AUX_MU_CNTL,
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uint32_t RE :1; /* Receiver Enable */
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uint32_t TE :1; /* Transmitter Enable */
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uint32_t ERAF :1; /* Enable Rx Auto Flow-control */
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uint32_t ETAF :1; /* Enable Tx Auto Flow-control */
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uint32_t RTS_AUTO :2; /* Rx Auto Flow Level */
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uint32_t RTS_ASSERT :1; /* Rx RTS invert */
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uint32_t CTS_ASSERT :1; /* CTS invert */
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uint32_t :24;
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);
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/* [0x00215064] Internal Status */
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const u32_union(AUX_MU_STAT,
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uint32_t SYMA :1; /* Symbol Available */
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uint32_t SPCA :1; /* Tx can accept a least one byte */
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uint32_t RII :1; /* Rx is idle */
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uint32_t TII :1; /* Tx is idle */
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uint32_t ROVRE :1; /* Rx overrun */
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uint32_t TDFF :1; /* Tx FIFO is full */
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uint32_t RTS :1; /* status of the UART1_RTS line */
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uint32_t CTS :1; /* status of the UART1_CTS line */
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uint32_t TDFE :1; /* Tx FIFO is empty */
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uint32_t TEND :1; /* Tx End */
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uint32_t :6;
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uint32_t RFFL :4; /* Rx FIFO fill level */
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uint32_t :4;
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uint32_t TFFL :4; /* Tx FIFO fill level */
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uint32_t :4;
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);
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/* [0x00215068] baudrate counter */
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u32_union(AUX_MU_BAUD,
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uint32_t BAUD :16; /* Baudrate */
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uint32_t :16;
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);
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} VPACKED(4);
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#define BCM2837_AUXILIARY (*((volatile struct __bcm2837_aux *)0x3f215000))
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#endif /* VXGOS_BOOTLOADER_RASPI3B_AUXILIARY_H */
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