141 lines
2.9 KiB
C
141 lines
2.9 KiB
C
#ifndef __VHEX_MPU_SH7305_CPG__
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# define __VHEX_MPU_SH7305_CPG__
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#include <vhex/defs/attributes.h>
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#include <vhex/defs/types.h>
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//---
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// SH7305 Clock Pulse Generator. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 17: "Clock Pulse Generator (CPG)"
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//---
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/* sh7305_cpg - Clock Pulse Generator registers
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Fields marked with [*] don't have the meaning described in the SH7724
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documentation. */
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struct __sh7305_cpg
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{
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lword_union(FRQCR,
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uint32_t KICK :1; /* Flush FRQCRA modifications */
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uint32_t :1;
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uint32_t STC :6; /* PLL multiplication [*] */
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uint32_t IFC :4; /* Iphi divider 1 [*] */
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uint32_t :4;
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uint32_t SFC :4; /* Sphi divider 1 [*] */
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uint32_t BFC :4; /* Bphi divider 1 [*] */
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uint32_t :4;
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uint32_t PFC :4; /* Pphi divider 1 [*] */
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);
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pad(0x4);
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lword_union(FSICLKCR,
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uint32_t :16;
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uint32_t DIVB :6; /* Division ratio for port B */
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uint32_t :1;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t SRC :2; /* Clock source select */
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uint32_t DIVA :6; /* Division ratio for port A */
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);
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pad(0x04);
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lword_union(DDCLKCR,
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uint32_t :23;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t SRC :1; /* Clock source select */
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uint32_t :1;
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uint32_t DIV :6;
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);
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lword_union(USBCLKCR,
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uint32_t :23;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t :8;
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);
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pad(0x0c);
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lword_union(PLLCR,
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uint32_t :17;
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uint32_t PLLE :1; /* PLL Enable */
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uint32_t :1;
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uint32_t FLLE :1; /* FLL Enable */
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uint32_t :10;
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uint32_t CKOFF :1; /* CKO Output Stop */
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uint32_t :1;
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);
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lword_union(PLL2CR,
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uint32_t KICK :1; /* Flush ??? modification */
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uint32_t :1;
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uint32_t MUL :6; /* ??? multiplication ration */
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uint32_t :24;
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);
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pad(0x10);
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lword_union(SPUCLKCR,
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uint32_t :23;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t SRC :1; /* Clock source select */
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uint32_t :1;
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uint32_t DIV :6; /* Division ratio */
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);
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pad(0x4);
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lword_union(SSCGCR,
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uint32_t SSEN :1; /* Spread Spectrum Enable */
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uint32_t :30;
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uint32_t SSEN_EMU:1; /* Emulateur enable */
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);
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pad(0x8);
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lword_union(FLLFRQ,
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uint32_t :16;
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uint32_t SELXM :2; /* FLL output division */
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uint32_t :3;
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uint32_t FLF :11; /* FLL Multiplication Ratio */
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);
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pad(0x0c);
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lword_union(LSTATS,
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uint32_t :31;
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uint32_t FRQF : 1; /* frequency changing status */
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);
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} VPACKED(4);
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#define SH7305_CPG (*((volatile struct __sh7305_cpg *)0xa4150000))
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//---
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// kernel-level API
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//---
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/* cpg_clock_frequency
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A dump of the Clock Pulse Generator's (CPG) configuration.*/
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struct cpg_clock_frequency {
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int PLL;
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int FLL;
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int base;
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int Bphi_div;
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int Iphi_div;
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int Sphi_div;
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int Pphi_div;
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int RTCCLK_f;
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int Bphi_f;
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int Iphi_f;
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int Sphi_f;
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int Pphi_f;
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};
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/* cpg_clock_freq() - get the frequency of the main clocks
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This function returns the address of a static object which is used by the
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module; this address never changes. */
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void cpg_clock_freq(struct cpg_clock_frequency *freq);
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#endif /* __VHEX_MPU_SH7305_CPG__ */
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