101 lines
2.6 KiB
C
101 lines
2.6 KiB
C
#ifndef __VHEX_DRIVER_MPU_SH_SH7305_DMA__
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# define __VHEX_DRIVER_MPU_SH_SH7305_DMA__
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#include <vhex/defs/attributes.h>
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#include <vhex/defs/types.h>
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//---
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// SH7305 Direct Memory Access Controller. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 16: "Direct Memory Access Controller (DMAC)"
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//
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// However, there is some (minor) differencies with the DMA controller of
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// the SH7305. Mainly, only the first channel have special features that
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// other don't.
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//---
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/* sh7305_dma_channel_t - One of the main 6 channels of the DMA
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Note that the many settings are only available on channels 0 to 3 (denoted
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by [0..3]) or on channels 0 (denoted by [0]).
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The documentation is apparently wrong about the placement is TS[3:2], the
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neighboring read-only bit must be swapped before TS[3:2]. */
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struct __sh7305_dma_channel
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{
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uint32_t SAR;
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uint32_t DAR;
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/* Mind that the 8 upper bits should always be written as 0 */
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uint32_t TCR;
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lword_union(CHCR,
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uint32_t :1;
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uint32_t LCKN :1; /* Bus Right Release Enable */
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uint32_t :2;
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uint32_t RPT :3; /* Repeat setting [0..3] */
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uint32_t DA :1; /* DREQ Asynchronous [0] */
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uint32_t DO :1; /* DMA Overrun [0] */
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uint32_t :1;
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uint32_t TS3 :1; /* Transfer Size (bit3) */
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uint32_t TS2 :1; /* Transfer Size (bit2) */
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uint32_t HE :1; /* Half-End flag [0..3] */
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uint32_t HIE :1; /* Half-end Interrupt Enable [0..3] */
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uint32_t AM :1; /* Acknowledge mode [0] */
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uint32_t AL :1; /* Acknowledge level [0] */
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uint32_t DM :2; /* Destination address Mode */
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uint32_t SM :2; /* Source address Mode */
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uint32_t RS :4; /* Resource Select */
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uint32_t DL :1; /* DREQ Level [0] */
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uint32_t DS :1; /* DREQ Source select[0] */
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uint32_t TB :1; /* Transfer Bus Mode */
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uint32_t TS1 :1; /* Transfer Size (bit1) */
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uint32_t TS0 :1; /* Transfer Size (bit0) */
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uint32_t IE :1; /* Interrupt Enable */
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uint32_t TE :1; /* Transfer End flag */
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uint32_t DE :1; /* DMA Enable */
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);
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} VPACKED(4);
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/* sh7305_dma_t - DMA Controller */
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struct __sh7305_dma
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{
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struct __sh7305_dma_channel DMA0;
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struct __sh7305_dma_channel DMA1;
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struct __sh7305_dma_channel DMA2;
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struct __sh7305_dma_channel DMA3;
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word_union(DMAOR,
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uint16_t CMS :4; /* Cycle steal Mode Select */
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uint16_t :2;
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uint16_t PR :2; /* PRiority mode */
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uint16_t :4;
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uint16_t :1;
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uint16_t AE :1; /* Address Error flag */
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uint16_t NMIF :1; /* NMI Flag */
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uint16_t DME :1; /* DMA Master Enable */
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);
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pad(14);
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struct __sh7305_dma_channel DMA4;
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struct __sh7305_dma_channel DMA5;
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} VPACKED(4);
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#define SH7305_DMA (*((volatile struct __sh7305_dma *)0xfe008020))
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#endif /* __VHEX_DRIVER_MPU_SH_SH7305_DMA__ */
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