288 lines
7.1 KiB
C
288 lines
7.1 KiB
C
#include <vhex/driver.h>
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#include <vhex/driver/mpu/sh/sh7305/intc.h>
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#include <vhex/driver/mpu/sh/sh7305/power.h>
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#include <string.h>
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/* Construct the Interrupt Controller */
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struct sh7305_intc SH7305_INTC = {
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.ICR0 = (void *)0xa4140000,
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.ICR1 = (void *)0xa414001c,
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.INTPRI00 = (void *)0xa4140010,
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.INTREQ00 = (void *)0xa4140024,
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.INTMSK00 = (void *)0xa4140044,
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.INTMSKCLR00 = (void *)0xa4140064,
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.NMIFCR = (void *)0xa41400c0,
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.IPR = (void *)0xa4080000,
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.MSK = (void *)0xa4080080,
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.MSKCLR = (void *)0xa40800c0,
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.USERIMASK = (void *)0xa4700000,
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// PINTCR = (void *)0xa40501dc,
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// PINTSR = (void *)0xa40501ea,
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};
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/* define the private INTerrupt Controller context structure */
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struct intc_ctx {
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uint16_t ipr[12];
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uint8_t imr[13];
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sh7305_intc_userimask_t userimask;
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sh7305_intc_icr0_t icr0;
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sh7305_intc_icr1_t icr1;
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sh7305_intc_intpri00_t intpri00;
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sh7305_intc_intreq00_t intreq00;
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sh7305_intc_intmsk00_t intmsk00;
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sh7305_intc_nmifcr_t nmifcr;
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};
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//---
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// hardware-level API
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//---
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/* Interrupt IPR and IMR positions. */
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/* Friendly names for IPR and IMR register numbers */
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enum{ IPRA, IPRB, IPRC, IPRD, IPRE, IPRF, IPRG, IPRH, IPRI, IPRJ, IPRK, IPRL };
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enum{ IMR0, IMR1, IMR2, IMR3, IMR4, IMR5, IMR6, IMR7, IMR8, IMR9, IMR10 };
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#define _ 0,0
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static struct info {
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uint16_t IPR4, IPR4bits, IMR, IMRbits;
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} const info[] = {
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/* Standard TMU */
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{ IPRA, 0xf000, IMR4, 0x10 },
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{ IPRA, 0x0f00, IMR4, 0x20 },
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{ IPRA, 0x00f0, IMR4, 0x40 },
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/* ETMU */
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{ IPRJ, 0xf000, IMR6, 0x08 },
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{ IPRG, 0x0f00, IMR5, 0x02 },
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{ IPRG, 0x00f0, IMR5, 0x04 },
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{ IPRE, 0x00f0, IMR2, 0x01 },
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{ IPRI, 0xf000, IMR6, 0x10 },
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{ IPRL, 0xf000, IMR8, 0x02 },
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/* DMA */
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{ IPRE, 0xf000, IMR1, 0x01 },
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{ IPRE, 0xf000, IMR1, 0x02 },
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{ IPRE, 0xf000, IMR1, 0x04 },
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{ IPRE, 0xf000, IMR1, 0x08 },
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{ IPRF, 0x0f00, IMR5, 0x10 },
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{ IPRF, 0x0f00, IMR5, 0x20 },
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{ IPRF, 0x0f00, IMR5, 0x40 },
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/* RTC */
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{ IPRK, 0xf000, IMR10, 0x04 },
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{ IPRK, 0xf000, IMR10, 0x02 },
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{ IPRK, 0xf000, IMR10, 0x01 },
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/* SPU */
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{ IPRC, 0x000f, IMR3, 0x04 },
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{ IPRC, 0x000f, IMR4, 0x08 },
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/* USB */
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{ IPRF, 0x00f0, IMR9, 0x02 },
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/* KEYSC */
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{ IPRF, 0xf000, IMR5, 0x80 }
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};
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/* sh7305_intc_priority() : set the interruption level */
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int sh7305_intc_priority(int intname, int level)
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{
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struct info const *i = &info[intname];
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int IPRn = i->IPR4, IPRbits = i->IPR4bits;
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/* Bit-shift for the mask */
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int shift = 0;
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while(IPRbits >>= 4) shift += 4;
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uint16_t volatile *IPR = &SH7305_INTC.IPR[IPRn << 1];
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int oldlevel = (*IPR >> shift) & 0xf;
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*IPR = (*IPR & ~(0xf << shift)) | (level << shift);
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if(level > 0) {
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uint8_t volatile *MSKCLR = SH7305_INTC.MSKCLR;
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MSKCLR[4*i->IMR] = i->IMRbits;
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} else {
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uint8_t volatile *MSK = SH7305_INTC.MSK;
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MSK[4*i->IMR] = i->IMRbits;
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}
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return oldlevel;
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}
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/* sh7305_intc_install_inth() : install interrupt gate */
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void *sh7305_intc_install_inth_gate(int event_code, void *gate, size_t size)
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{
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extern uintptr_t vhex_vbr;
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return memcpy(
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(void*)((uintptr_t)&vhex_vbr + 0x600 + 0x40 + (event_code - 0x400)),
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gate,
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size
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);
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}
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/* sh7305_intc_generic_handler() : install generic interrupt handler */
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void *sh7305_intc_install_inth_generic(int event_code, vhex_call_t callback)
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{
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extern void sh7305_intc_inth_generic_gate(void);
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extern void sh7305_inth_callback(void);
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uint8_t *h = sh7305_intc_install_inth_gate(
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event_code,
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&sh7305_intc_inth_generic_gate,
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32
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);
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if(h != NULL) {
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uintptr_t workaround = (uintptr_t)&sh7305_inth_callback;
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memcpy(&h[8], &callback, 20);
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memcpy(&h[28], &workaround, 4);
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}
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return h;
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}
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//---
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// hardware configuration call
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//---
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#if 0
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static bool __intc_hpowered(void)
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{
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return (SH7305_POWER.MSTPCR0.INTC == 0);
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}
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static int __intc_hpoweron(void)
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{
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SH7305_POWER.MSTPCR0.INTC = 0;
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return 0;
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}
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static int __intc_hpoweroff(void)
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{
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SH7305_POWER.MSTPCR0.INTC = 1;
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return 0;
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}
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#endif
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/* __intc_configure() : configure the Interrupt Controller
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Note that we don't touch to the NMI configuration because this part is
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obscure. I have done some reverse-ingenering in this part, but Casio seems
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use this part oddly. So, to avoid any probleme with Non-Maskable Interrupt,
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we will use the Casio's configuration.
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So, by default, mask all interrupt and enable all interrupt is the user
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interrupt mask */
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static void __intc_configure(struct intc_ctx *state)
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{
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memset(state, 0x00, sizeof(struct intc_ctx));
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for (int i = 0; i < 12; ++i)
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state->ipr[i] = 0x0000;
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for (int i = 0; i < 13; ++i)
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state->imr[i] = 0x00;
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state->userimask._0xa5 = 0xa5;
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state->userimask.UIMASK = 0x00;
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/* interrupt control register 0 (NMI)
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<> enable NMI interruption when a input level is low
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<> keep NMI interrupt pending while the SR.BL=1
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<> interrupt request is detected on falling edge */
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state->icr0.MAI = 0;
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state->icr0.NMIB = 0;
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state->icr0.NMIE = 0;
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state->icr0._HIGH = 0b11;
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/* Interrupt control register 1 (IRQ)
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<> interrupt request is detected on low-level of IRQx input */
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state->icr1.IRQ0S = 0b10;
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state->icr1.IRQ1S = 0b10;
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state->icr1.IRQ2S = 0b10;
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state->icr1.IRQ3S = 0b10;
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/* Interrupt priority (IRQ)
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<> mask all IRQx interrupt */
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state->intpri00.IRQ0 = 0b0000;
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state->intpri00.IRQ1 = 0b0000;
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state->intpri00.IRQ2 = 0b0000;
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state->intpri00.IRQ3 = 0b0000;
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/* Interrupt request (IRQ)
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<> clear all pending interrupt request */
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state->intreq00.IRQ0 = 0;
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state->intreq00.IRQ1 = 0;
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state->intreq00.IRQ2 = 0;
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state->intreq00.IRQ3 = 0;
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/* Interurpt mask (IRQ)
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<> mask all IRQ interrupt */
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state->intmsk00.IRQ0 = 1;
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state->intmsk00.IRQ1 = 1;
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state->intmsk00.IRQ2 = 1;
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state->intmsk00.IRQ3 = 1;
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/* NMI Interrupt flags (clear) */
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state->nmifcr.NMIFL = 0;
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}
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/* hardware hypervisor call */
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/* __intc_hsave() : save hardware information */
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static void __intc_hsave(struct intc_ctx *state)
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{
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for (int i = 0; i < 12; ++i)
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state->ipr[i] = SH7305_INTC.IPR[i << 1];
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for (int i = 0; i < 13; ++i)
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state->imr[i] = SH7305_INTC.MSK[i << 2];
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state->userimask = *SH7305_INTC.USERIMASK;
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state->icr0 = *SH7305_INTC.ICR0;
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state->icr1 = *SH7305_INTC.ICR1;
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state->intpri00 = *SH7305_INTC.INTPRI00;
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state->intreq00 = *SH7305_INTC.INTREQ00;
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state->intmsk00 = *SH7305_INTC.INTMSK00;
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}
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/* __intc_hrestore() : restore hardware information */
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static void __intc_hrestore(struct intc_ctx *state)
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{
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for (int i = 0; i < 12; ++i)
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SH7305_INTC.IPR[i << 1] = state->ipr[i];
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for (int i = 0; i < 13; ++i) {
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SH7305_INTC.MSKCLR[i << 2] = 0xff;
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SH7305_INTC.MSK[i << 2] = state->imr[i];
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}
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state->userimask._0xa5 = 0xa5;
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*SH7305_INTC.USERIMASK = state->userimask;
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*SH7305_INTC.ICR0 = state->icr0;
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*SH7305_INTC.ICR1 = state->icr1;
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*SH7305_INTC.INTPRI00 = state->intpri00;
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*SH7305_INTC.INTREQ00 = state->intreq00;
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*SH7305_INTC.INTMSKCLR00 = (sh7305_intc_intmskclr00_t){
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.IRQ0 = 1,
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.IRQ1 = 1,
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.IRQ2 = 1,
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.IRQ3 = 1,
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};
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*SH7305_INTC.INTMSK00 = state->intmsk00;
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}
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/* declare the INTC driver */
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struct vhex_driver drv_intc = {
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.name = "INTC",
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.hsave = (void*)&__intc_hsave,
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.hrestore = (void*)&__intc_hrestore,
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.configure = (void*)&__intc_configure,
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.state_size = sizeof(struct intc_ctx)
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};
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VHEX_DECLARE_DRIVER(01, drv_intc);
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