79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
#include <vhex/driver/mpu/sh/sh7305/cpg.h>
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#include <vhex/driver.h>
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#define CPG SH7305_CPG
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void cpg_clock_freq(struct cpg_clock_frequency *freq)
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{
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/* The meaning of the PLL setting on SH7305 differs from the
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documentation of SH7224; the value must not be doubled. */
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int pll = CPG.FRQCR.STC + 1;
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freq->PLL = pll;
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/* The FLL ratio is the value of the setting, halved if SELXM=1 */
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int fll = CPG.FLLFRQ.FLF;
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if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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freq->FLL = fll;
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/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
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the SH7305 it is 1 / (2^setting + 1). */
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int divb = CPG.FRQCR.BFC;
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int divi = CPG.FRQCR.IFC;
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int divs = CPG.FRQCR.SFC;
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int divp = CPG.FRQCR.P1FC;
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freq->Bphi_div = 1 << (divb + 1);
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freq->Iphi_div = 1 << (divi + 1);
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freq->Sphi_div = 1 << (divs + 1);
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freq->Pphi_div = 1 << (divp + 1);
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/* Deduce the input frequency of divider 1 */
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freq->base = 32768;
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if(CPG.PLLCR.FLLE) freq->base *= fll;
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if(CPG.PLLCR.PLLE) freq->base *= pll;
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/* And the frequency of all other input clocks */
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freq->RTCCLK_f = 32768;
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freq->Bphi_f = freq->base >> (divb + 1);
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freq->Iphi_f = freq->base >> (divi + 1);
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freq->Sphi_f = freq->base >> (divs + 1);
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freq->Pphi_f = freq->base >> (divp + 1);
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}
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//---
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// Define driver information
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//---
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struct cpg_ctx {
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uint32_t SSCGCR;
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};
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/* __cpg_configure() : configure the CPG */
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static void __cpg_configure(struct cpg_ctx *state)
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{
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(void)state;
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}
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/* __cpg_hsave() : save hardware information */
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static void __cpg_hsave(struct cpg_ctx *state)
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{
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(void)state;
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}
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/* __cpg_hrestore() : restore hardware information */
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static void __cpg_hrestore(struct cpg_ctx *state)
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{
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(void)state;
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}
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struct vhex_driver drv_cpg = {
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.name = "CPG",
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.hsave = (void*)&__cpg_hsave,
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.hrestore = (void*)&__cpg_hrestore,
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.configure = (void*)&__cpg_configure,
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.state_size = sizeof(struct cpg_ctx)
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};
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VHEX_DECLARE_DRIVER(03, drv_cpu);
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