56 lines
982 B
ArmAsm
56 lines
982 B
ArmAsm
.section .vhex.exch.pretext, "ax"
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.global _vhex_exch_sh7305
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_vhex_exch_sh7305:
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! Generate "CPU" context
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sts.l pr, @-r15
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stc.l spc, @-r15
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stc.l ssr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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stc.l gbr, @-r15
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stc.l sgr, @-r15
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mov.l r14, @-r15
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mov.l r13, @-r15
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mov.l r12, @-r15
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mov.l r11, @-r15
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mov.l r10, @-r15
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mov.l r9, @-r15
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mov.l r8, @-r15
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stc.l R7_BANK, @-r15
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stc.l R6_BANK, @-r15
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stc.l R5_BANK, @-r15
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stc.l R4_BANK, @-r15
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stc.l R3_BANK, @-r15
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stc.l R2_BANK, @-r15
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stc.l R1_BANK, @-r15
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stc.l R0_BANK, @-r15
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/* Set BL=0, IMASK=15 */
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stc sr, r9
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mov.l SR_set_IMASK, r1
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or r9, r1
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mov.l SR_clear_BL, r2
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and r2, r1
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ldc r1, sr
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/* Call the kernel panic and leave if it returns zero (exception
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handled) */
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mov.l expevt_sh4, r8
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mov.l kernel_exch_panic, r0
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mov r15, r5
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jmp @r0
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mov.l @r8, r4
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.balign 4
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expevt_sh4:
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.long 0xff000024
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kernel_exch_panic:
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.long _sh7305_intc_exch_panic
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SR_set_IMASK:
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.long (0xf << 4)
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SR_clear_BL:
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.long ~(1 << 28)
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