76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
#ifndef __VHEX_ARCH_SH7305_CPU__
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# define __VHEX_ARCH_SH7305_CPU__
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#include <vhex/defs/types.h>
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#include <vhex/defs/attributes.h>
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//---
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// Access to CPU registers
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//---
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/* cpu_get_vbr() : get the VBR register */
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extern uintptr_t cpu_get_vbr(void);
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/* cpu_set_vbr() : set the new VBR address */
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extern void cpu_set_vbr(uint32_t VBR);
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/* cpu_cpuopm_t : Bits of the CPU Operation Mode */
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typedef lword_union(cpu_cpuopm_t,
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uint32_t : 22;
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uint32_t _HIGH : 4; /* SOULD be 1 */
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uint32_t RABD : 1; /* Speculative fetching */
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uint32_t : 1;
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uint32_t INTMU : 1; /* Interrupt mode */
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uint32_t : 3;
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);
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/* cpu_get_cpuopm() : read the CPU Operation Mode register. */
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cpu_cpuopm_t cpu_get_cpuopm(void);
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/* cpu_set_cpuopm() : Update the CPU Operation Mode register.
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After a write, the register is re-read and an (icbi) instruction is executed
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to apply the change. Non-writable bits should be left to their initial value
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during a write. */
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extern void cpu_set_cpuopm(cpu_cpuopm_t cpuopm);
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/* cpu_str_t: Bits of the Status Register */
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typedef lword_union(cpu_sr_t,
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uint32_t : 1;
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uint32_t MD : 1; /* Processing mode */
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uint32_t RB : 1; /* Register bank */
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uint32_t BL : 1; /* Exception / Interrupt Block */
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uint32_t RC : 12; /* Repeat counter */
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uint32_t : 3;
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uint32_t DSP : 1; /* Enable DSP */
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uint32_t DMY : 1; /* Y pointer modulo addressing */
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uint32_t DMX : 1; /* X pointer module addressing */
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uint32_t M : 1; /* M bit (used in div0u, ...) */
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uint32_t Q : 1; /* Q bit (used in div0u, ...) */
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uint32_t IMASK : 4; /* Interrupt Mask */
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uint32_t RF : 2; /* Repeat flags */
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uint32_t S : 1; /* S bit (used with MAC operation) */
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uint32_t T : 1; /* T but (true/false, condition, ...) */
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);
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/* cpu_get_sr() : get the Status Register */
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extern cpu_sr_t cpu_get_sr(void);
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/* cpu_set_st() : write the SR register.
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When writing, only "permanent" bits are set:
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* MD, RB, BL, DSP, IMASK are set.
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* M, Q, S and T are not set to preserve the behavior of ongoing divisions
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and tests. You can change T with (sett) and (clrt).
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* RC, DMY, DMX and DF are not set: use (setrc), (setdmx), (setdmy), and
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(clrdmxy). DF is preserved for old-style (setrc) loops to work. */
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extern void cpu_set_sr(cpu_sr_t sr);
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#endif /* __VHEX_ARCH_SH7305_CPU__ */
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