52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
#include <kernel/devices/ubc.h>
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#include <kernel/hardware/ubc.h>
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#include <kernel/hardware/power.h>
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#include <kernel/syscall.h>
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#include <kernel/extra.h>
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#include <kernel/dbr.h>
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// Internal data used by UBC device.
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void *casio_dbr;
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// Internal function.
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extern void ubc_handler_pre(void);
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int ubc_open(void)
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{
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//FIXME: check MPU before call this function !!!
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// Power ON the User Break Controller.
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SH7305_POWER.MSTPCR0.UBC = 0;
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// Set Debug Based Register address.
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casio_dbr = dbr_set(&ubc_handler_pre);
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// Setup Channel 0.
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SH7305_UBC.CRR0.PCB = 1; // Set PC break adter instruction break.
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SH7305_UBC.CRR0.BIE = 1; // Request a Break.
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SH7305_UBC.CBR0.MFE = 0; // Enable Match Flag.
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SH7305_UBC.CBR0.MFI = 0b000000; // Set UBC.CCMFR.MF0 = 1, when break occur.
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SH7305_UBC.CBR0.AIE = 0; // Disable ASID check.
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SH7305_UBC.CBR0.SZ = 0b010; // Disable Match condition.
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SH7305_UBC.CBR0.CD = 0; // Use Operand Bus for Operand Access.
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SH7305_UBC.CBR0.ID = 0b01; // Selecte instruction Fetch cycle.
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SH7305_UBC.CBR0.RW = 0b11; // Use Read or Write for match condition.
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SH7305_UBC.CBR0.CE = 0; // Disable Channel 0.
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// Set up target address.
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SH7305_UBC.CAR0 = 0x00000000; // Tested programe address !
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SH7305_UBC.CAMR0 = 0x00000000; // Address Mask.
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// Setup Control register.
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SH7305_UBC.CBCR.UBDE = 1; // Use DBR instead of VBR.
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//@note:
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// You *SHOULD* use `icbi` SH4 instruction
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// After channel enable, otherwise the calculator
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// will freeze.
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SH7305_UBC.CBR0.CE = 1; // Enable Channel 0 !
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icbi((void*)0xa0000000);
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return (0);
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}
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