102 lines
3.6 KiB
C
102 lines
3.6 KiB
C
#ifndef __KERNEL_MODULES_SH7724_STANDBY_H__
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# define __KERNEL_MODULES_SH7724_STANDBY_H__
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#include <stdint.h>
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#include <stddef.h>
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#include <kernel/def/union_types.h>
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#include <kernel/def/attributes.h>
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struct power_s
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{
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volatile long_union(STBCR, /* Standby Control Register */
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uint32_t const : 24;
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uint32_t STBY : 1;
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uint32_t const : 1;
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uint32_t RSTBY : 1;
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uint32_t USTBY : 1;
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uint32_t const : 4;
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);
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GAPS(12);
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volatile long_union(MSTPCR0, /* Module Stop Register 0 */
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uint32_t TLB : 1; /* TLB */
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uint32_t IC : 1; /* Instruction cache */
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uint32_t OC : 1; /* Operand cache */
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uint32_t RS : 1; /* RS memory */
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uint32_t IL : 1; /* IL memory */
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uint32_t SC : 1; /* Secondary cache */
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uint32_t const : 1; /* All 0 */
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uint32_t FPU : 1; /* Floating Point Unit */
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uint32_t const : 1; /* All 0*/
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uint32_t INTC : 1; /* Interrupt Controller */
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uint32_t DMAC0 : 1; /* Direct Memory Access Controller 0 */
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uint32_t SuperH : 1; /* SuperHyway */
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uint32_t HUID : 1; /* User Debugging Interface */
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uint32_t DBG : 1; /* Debugging function */
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uint32_t UBC : 1; /* User Break Controller */
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uint32_t const : 1; /* Reserved (R/W) */
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uint32_t TMU0 : 1; /* Timer Unit 0 */
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uint32_t CMT : 1; /* Compare Match Timer */
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uint32_t RWDT : 1; /* Wathdog Timer */
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uint32_t DMAC1 : 1; /* Direct Memory Access Controller 1 */
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uint32_t const : 1; /* All 0 */
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uint32_t TMU1 : 1; /* Timer Unit 1 */
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uint32_t SCIF0 : 1; /* Serial Controller Interface 0 */
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uint32_t SCIF1 : 1; /* Serial Controller Interface 1 (Additionnal timer !!) */
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uint32_t SCIF2 : 1; /* Serial Controller Interface 2 */
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uint32_t SCIF3 : 1; /* Serial Controller Interface 3 */
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uint32_t SCIF4 : 1; /* Serial Controller Interface 4 */
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uint32_t SCIF5 : 1; /* Serial Controller Interface 5 */
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uint32_t const : 1; /* All 0 */
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uint32_t MSIOF0 : 1; /* Clock-synch. Serial Interface 0 */
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uint32_t MSIOF1 : 1; /* Clock-synch. Serial Interface 0 */
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uint32_t const : 1; /* All 0 */
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);
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volatile long_union(MSTPCR1, /* Module Stop Register 1 */
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uint32_t const : 19; /* All 0 */
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uint32_t KEYSC : 1; /* Key Scan Interface */
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uint32_t RTC : 1; /* Real Time Clock */
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uint32_t const : 1; /* All 0 */
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uint32_t I2C0 : 1; /* I2C 0 */
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uint32_t I2C1 : 1; /* I2C 1 */
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uint32_t const : 8; /* All 0 */
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);
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volatile long_union(MSTPCR2, /* Module Stop Register 2 */
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uint32_t const : 2; /* All 0 */
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uint32_t MMC : 1; /* Multi Media Card Interface (?) */
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uint32_t EMAC : 1; /* Ether Controller */
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uint32_t const : 1; /* All 0 */
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uint32_t ATAPI : 1; /* ATAPI */
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uint32_t TPU : 1; /* Timer Pulse Unit */
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uint32_t IrDA : 1; /* IrDA interface */
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uint32_t const : 1; /* All 0 */
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uint32_t TSIF : 1; /* TS interface */
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uint32_t USB1 : 1; /* USB 1 */
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uint32_t USB0 : 1; /* USB 0 */
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uint32_t _2DG : 1; /* 2D graphics accelerator */
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uint32_t SDHI0 : 1; /* SD card host */
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uint32_t SDHI1 : 1; /* IrDA interface */
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uint32_t const : 1; /* All 0 */
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uint32_t VEU1 : 1; /* */
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uint32_t const : 1; /* All 0 */
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uint32_t CEU1 : 1; /* */
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uint32_t BEU1 : 1; /* */
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uint32_t const : 1; /* All 0 */
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uint32_t _2DDMAC: 1; /* */
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uint32_t SPU : 1; /* Sound Processing Unit */
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uint32_t const : 1; /* All 0 */
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uint32_t GCU : 1; /* */
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uint32_t JPU : 1; /* JPEG processing Unit */
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uint32_t VOU : 1; /* Video Output Unit */
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uint32_t BEU0 : 1; /* */
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uint32_t CEU0 : 1; /* */
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uint32_t VPU : 1; /* Video Processing Unit */
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uint32_t LCDC : 1; /* LCD controller */
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);
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GAPS(4);
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volatile uint32_t const BAR; /* Boot Address Register */
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};
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#define SH7305_POWER (*(volatile struct power_s *)0xa4150020)
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#endif /*__KERNEL_MODULES_SH7724_STANDBY_H__*/
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