94 lines
1.6 KiB
Plaintext
94 lines
1.6 KiB
Plaintext
OUTPUT_ARCH(sh3)
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OUTPUT_FORMAT(elf32-sh)
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ENTRY(_start)
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MEMORY
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{
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/*
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** bootram is the RAM physical location for global variable
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** during the bootloader step.
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** This location is realy important because no Casio's OS data
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** should be overwrite (specially TLB information stored by Casio).
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*/
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bootram (rwx) : o = 0x88040000, l = 252k
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osram (rwx) : o = 0x8807f000, l = 4k
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rom (rx) : o = 0x00300200, l = 512k
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}
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SECTIONS
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{
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/*
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** ROM sections
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*/
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. = ORIGIN(rom);
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.text : {
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*(.pretext)
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*(.text)
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. = ALIGN(4);
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*(.rodata)
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*(.rodata.*)
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} > rom
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/*
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** RAM sctions
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*/
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. = ORIGIN(bootram);
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/* BootStrap Stack: should be wiped later ! */
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/* (we force the section to be non loadable when the program is run) */
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.bss (NOLOAD) : {
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_bbss = . ;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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} > bootram :NONE
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_sbss = SIZEOF(.bss);
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/* Read-write data going to RAM */
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.data : ALIGN(4) {
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_bdata_rom = LOADADDR(.data) ;
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_bdata_ram = . ;
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*(.data)
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/* Video RAM space */
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_VRAM = ALIGN(4);
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. = (. + 1024);
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} > bootram AT> rom
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_sdata = SIZEOF(.data);
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/*
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** VBR space !
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*/
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/* Interrupt / exception handlers */
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.vhex : SUBALIGN(4) {
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_bvhex_rom = LOADADDR(.vhex) ;
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_bvhex_ram = . ;
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_vhex_vbr = . - 0x100;
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*(.vhex.exception) ;
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. = _vhex_vbr + 0x400 ;
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*(.vhex.tlb) ;
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. = _vhex_vbr + 0x600 ;
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*(.vhex.interrupt) ;
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. = ALIGN(4);
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} > osram AT> rom
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_svhex = SIZEOF(.vhex);
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/* unwanted section */
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/DISCARD/ : {
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*(.debug_info)
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*(.debug_abbrev)
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*(.debug_loc)
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*(.debug_aranges)
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*(.debug_ranges)
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*(.debug_line)
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*(.debug_str)
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*(.jcr)
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*(.eh_frame_hdr)
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*(.eh_frame)
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*(.comment)
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}
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}
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