58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
#include <kernel/drivers/cpg.h>
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#include <kernel/hardware/cpg.h>
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#include <kernel/bits/driver.h>
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// Internal struct
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struct cpg cpg_info;
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// @note: we just get the frequencies
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static void sh7305_cpg_driver_install(void)
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{
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// Calculate FLL frequency (Khz)
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// @note: RCLK = 32 768 Hz
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cpg_info.fll_freq = SH7305_CPG.FLLFRQ.FLF * 32768; // Hz
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cpg_info.fll_freq /= (1 << SH7305_CPG.FLLFRQ.SELXM); // Check FLL output division
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// Calculate PLL frequency (Khz)
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cpg_info.pll_freq = cpg_info.fll_freq * (SH7305_CPG.FRQCRA.STC + 1);
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// Calculate CPU clock frequency !
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cpg_info.cpu_freq = cpg_info.pll_freq / (1 << (SH7305_CPG.FRQCRA.IFC + 1));
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// Calculate BUS clock frequency !
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cpg_info.bus_freq = cpg_info.pll_freq / (1 << (SH7305_CPG.FRQCRA.BFC + 1));
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// Calculate Peripheral clock frequency !
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cpg_info.per_freq = cpg_info.pll_freq / (1 << (SH7305_CPG.FRQCRA.PFC + 1));
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// Debug
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// TODO: device
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/*earlyterm_write("Calibrate frequencies...\n");
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earlyterm_write(
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"* FLL freq: %d.%d Mhz\n"
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"* PLL freq: %d.%d Mhz\n"
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"* CPU freq: %d.%d Mhz\n"
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"* BUS freq: %d.%d Mhz\n"
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"* Per freq: %d.%d Mhz\n",
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cpg_info.fll_freq / 1000000, (((cpg_info.fll_freq - ((cpg_info.fll_freq / 1000000)) * 1000000)) + 999) / 1000,
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cpg_info.pll_freq / 1000000, (((cpg_info.pll_freq - ((cpg_info.pll_freq / 1000000)) * 1000000)) + 999) / 1000,
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cpg_info.cpu_freq / 1000000, (((cpg_info.cpu_freq - ((cpg_info.cpu_freq / 1000000)) * 1000000)) + 999) / 1000,
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cpg_info.bus_freq / 1000000, (((cpg_info.bus_freq - ((cpg_info.bus_freq / 1000000)) * 1000000)) + 999) / 1000,
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cpg_info.per_freq / 1000000, (((cpg_info.per_freq - ((cpg_info.per_freq / 1000000)) * 1000000)) + 999) / 1000
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);*/
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}
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static void sh7305_cpg_driver_uninstall(void)
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{
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// Nothing for now
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}
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// Create driver object
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VHEX_DRIVER(2, driver_cpg_sh7305) = {
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.arch = MPU_SH7305,
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.install = &sh7305_cpg_driver_install,
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.uninstall = &sh7305_cpg_driver_uninstall,
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.name = "cpg"
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};
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