2020-07-13 16:59:42 +02:00
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---
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layout: page
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title: "A/D Converter (ADC) documentation"
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permalink: /hardware/sh7305/adc.html
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author: Yatis
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---
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This module is really close to the SH7705 but with additional feature (like the SH7731?).
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Unfortunately, I couldn't find all the features that this module offer but I have
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the main part of this module: interruption, scan mode and channel informations.
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<u>Features</u>
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* 10-bit resolution
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* Four input channels (Only the Channel can be used here)
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* Minimum conversion time: 8.5 μs per channel (Pφ = 33 MHz operation)
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* Three conversion modes
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* Single mode: A/D conversion on one channel
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* Multi mode: A/D conversion on one to four channels
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* Scan mode: Continuous A/D conversion on one to four channels
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* 16-bit data registers
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* A/D conversion results are transferred for storage into 16-bit data registers corresponding
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to the channels.
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* Sample-and-hold function
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* Interrupt source
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* At the end of A/D conversion, an A/D conversion end interrupt (ADI) can be requested.
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* The interruption ADI set 0x560 int the INTEVT register.
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* Module standby mode can be set
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__Chapters:__<br>
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1. [ADC registers documentation<br>](#adc-registers-documentation)
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2. [Module Operations](#module-operations)
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* [Single mode](#single-mode)
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* [Multi mode](#milti-mode)
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* [Scan mode](#scan-mode)
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3. [Other notes](#other-notes)
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4. [Small C-code ADC driver implementation](#small-c-code-adc-driver-implementation)
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---
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## ADC registers documentation
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After many tests, there is all register with their bits field.
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Many feature is still unknown bacause Casio's do not use it and it's pretty complicated
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to find informations.
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[Registers list:]({{ site.baseurl }}/hardware/sh7305/registers_list.html#adc---analogdigital-converter)
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* [(0xa4610080) ADDRA - A/D Data Registers A](#ad-data-registers-a-to-d-addra-to-addrd)
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* [(0xa4610082) ADDRB - A/D Data Registers B](#ad-data-registers-a-to-d-addra-to-addrd)
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* [(0xa4610084) ADDRC - A/D Data Registers C](#ad-data-registers-a-to-d-addra-to-addrd)
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* [(0xa4610086) ADDRD - A/D Data Registers D](#ad-data-registers-a-to-d-addra-to-addrd)
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* [(0xa4610088) ADCSR - A/D Control/Status Registers](#ad-controlstatus-registers-adcsr-address0xa4610088--bitmask0x70f3)
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* [(0xa461008a) ADCCSR - A/D Custom Control Registers](#ad-custom-control-adccsr-address0xa461008a--bitmask0x63ff)
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* [(0xa461008c) ADCUST - A/D Control Registers](#ad-control-adcust-address0xa461008c--bitmask0x8001)
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* [(0xa461008e) ADPCTL - A/D Port control](#ad-port-control-adpctl-address0xa461008e--bitmask0xf0ff)
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<br>
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## A/D Data Registers A to D (ADDRA to ADDRD)
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The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
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results of A/D conversion.
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An A/D conversion produces 10-bit data, which is transferred for storage into bits 15 to 6 in the
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A/D data register corresponding to the selected channel. Bits 5 to 0 of an A/D data register are
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reserved bits that are always read as 0.
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The A/D data registers are initialized to H'0000.
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| Bit | Bit name | Initial Value | R/W |Description |
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|----------|:--------:|---------------|:---:|----------------------------------------------------------------------------------|
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| 15 to 6 | AD | All 0 | R | 10-bit data |
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| 5 to 0 | - | All 0 | R | Reserved.<br>These bits are always read as 0.The write value should always be 0. |
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NOTE:
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* Only Channel C can be used, otherwise the "Scalle-error"(0x3ff) will be read each time.
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* Data resolution: 0,01157894737 volts per bits
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<br>
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## A/D Control/Status Registers (ADCSR: address=0xa4610088 && bitmask=0x70F3)
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ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
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| Bit | Bit name | Initial Value | R/W |Description |
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|----------|:--------:|---------------|:---:|----------------------------------------------------------------------------------|
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| 15 | ADF | 0 | R/W | A/D Interrupt End Flag |
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| 14 | ADIE | 0 | R/W | A/D Interrupt Enable |
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| 13 | ADST | 0 | R/W | A/D Start convertion |
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| 12 | DMASL | 0 | R/W | DMAC Select(?) |
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| 11 to 8 | - | All 0 | R | Reserved.<br>These bits are always read as 0.The write value should always be 0. |
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| 7, 6 | CKS | 0b01 | R/W | Clock Select. Selects the A/D conversion time. |
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| 5, 4 | MULTI | 0b00 | R/W | Mode Select: single mode, multi mode, or scan mode. |
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| 3, 2 | - | All 0 | R | Reserved.<br>These bits are always read as 0.The write value should always be 0. |
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| 1, 0 | CH | 0b00 | R/W | Channel Select |
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<u>Bit 15: ADF</u><br>
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Indicates the end of A/D conversion.
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* Setting conditions
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* Single mode: A/D conversion ends
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* Multi mode: A/D conversion ends cycling through the selected channels
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* Scan mode: A/D conversion ends cycling through the selected channels
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* Clearing conditions
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1. Reading ADF while ADF = 1, then writing 0 to ADF
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2. DMAC is activated by ADI interrupt and ADDR is read
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Note: * Clear this bit by writing 0. Writing 1 is ignored.
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<u>Bit 14: ADIE</u><br>
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Enables or disables the interrupt (ADI, 0x560) requested by ADF.
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Set the ADIE bit while the ADST bit is 0.
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* 0: Interrupt (ADI, 0x560) requested by ADF is disabled
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* 1: Interrupt (ADI, 0x560) requested by ADF is enabled
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<u>Bit 13: ADST</u><br>
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Starts or stops A/D conversion. The ADST bit remains set to
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1 during A/D conversion.
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* 0: A/D conversion is stopped.
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* 1: A/D conversion is processing.
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* Single mode:<br>
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A/D conversion starts; ADST is automatically cleared to 0 when
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conversion ends on selected channels.
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* Multi mode:<br>
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A/D conversion starts; when conversion is completed cycling through
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the selected channels, ADST is automatically cleared.
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* Scan mode:<br>
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A/D conversion starts and continues, A/D conversion is continuously
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performed until ADST is cleared to 0 by software, by a reset, or
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by a transition to standby mode.
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<u>Bit 12: DMASL(?)</u><br>
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Selects an interrupt due to ADF or activation of the DMAC.
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Set the DMASL bit while the ADST bit is 0.
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* 0: An interrupt by ADF is selected.
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* 1: Activation of the DMAC by ADF is selected.
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NOTE: No tested yet !
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<u>Bit 7, 6: CLKS</u><br>
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Selects the A/D conversion time. Clear the ADST bit to 0
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before changing the conversion time.
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* 00: Conversion time = 151 states (maximum) at Pφ/4
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* 01: Conversion time = 285 states (maximum) at Pφ/8
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* 10: Conversion time = 545 states (maximum) at Pφ/16
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2021-05-13 22:35:41 +02:00
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* 11: Setting prohibited (but the emulator use like 10, so 545 states (maximum) at Pφ/16)
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2020-07-13 16:59:42 +02:00
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Note: If the minimum conversion time is not satisfied,
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lack of accuracy or abnormal operation may
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occur.
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<u>Bit 5, 4: MULTI</u><br>
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Selects single mode, multi mode, or scan mode.
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* 00: Single mode
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* 01: Setting prohibited
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* 10: Multi mode
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* 11: Scan mode
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<u>Bit 1, 0: CH</u><br>
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These bits and the MULTI bit select the analog input
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channels. Clear the ADST bit to 0 before changing the
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channel selection.
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* Single mode:
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* 00: ADDRA
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* 01: ADDRB
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* 10: ADDRC
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* 11: ADDRD
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* Multi mode:
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* 00: ADDRA
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* 01: ADDRA, ADDRB
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* 10: ADDRA to ADDRC
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* 11: ADDRA to ADDRD
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* Scan mode:
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* 00: ADDRA
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* 01: ADDRA, ADDRB
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* 10: ADDRA to ADDRC
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* 11: ADDRA to ADDRD
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<br>
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## A/D Custom control (ADCCSR: address=0xa461008a && bitmask=0x63ff)
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ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
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Seems to be used to start the ADC using external trigger like DMA(?), TMU(?) or CMT(?).
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Casio do not use this register unless in their ADC interruption handler which they clear the interrupt flags and the wait flags(?)
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| Bit | Bit name | Initial Value | R/W |Description |
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|----------|:--------:|---------------|:---:|----------------------------------------------------------------------------------|
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| 15 | ADF | 0 | R/W | A/D Interrupt Trigger End Flag |
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2021-05-13 22:35:41 +02:00
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| 14 | ADIE | 0 | R/W | A/D Interrupt Trigger Enable |
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| 13 | ADST | 0 | R/W | A/D Wait trigger convertion(?) |
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| 12 to 10 | - | All 0 | R | Reserved.<br>These bits are always read as 0.The write value should always be 0. |
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| 9 to 8 | CKS | 0 | R/W | Clock Select. Selects the A/D conversion time. |
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| 7 to 0 | unknown | 0 | R/W | Unknown, seems linked with the clock configuration. (clock multiplicator?) |
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2020-07-13 16:59:42 +02:00
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<u>Bit 15: ADF</u><br>
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Indicates the end of A/D conversion.
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* Setting conditions
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* Single mode: A/D conversion ends
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* Multi mode: A/D conversion ends cycling through the selected channels
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* Scan mode: A/D conversion ends cycling through the selected channels
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* Clearing conditions
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1. Reading ADF while ADF = 1, then writing 0 to ADF
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2021-05-13 22:35:41 +02:00
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<u>Bit 14: ADIE</u></br>
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Enables or disables the interrupt (ADI, 0x560) requested by ADF.
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Set the ADIE bit while the ADST bit is 0.
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* 0: Interrupt (ADI, 0x560) requested by ADF is disabled
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* 1: Interrupt (ADI, 0x560) requested by ADF is enabled
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<u>Bit 9 to 8</u><br>
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Selects the A/D conversion time. Clear the ADST bit to 0
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before changing the conversion time.
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* 00: Conversion time = <unknown>
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* 01: Conversion time = <unknown>
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* 10: Conversion time = <unknown>
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* 11: Setting prohibited
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Note: If the minimum conversion time is not satisfied,
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lack of accuracy or abnormal operation may
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occur.
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<u>Bit 7 to 0</u></br>
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Really unknown for now, seems used like clock multiplicator...(TODO)
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2020-07-13 16:59:42 +02:00
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<br>
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## A/D Control (ADCUST: address=0xa461008c && bitmask=0x8001)
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2021-05-13 22:35:41 +02:00
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ADCSR is a 16-bit readable/writable register used to control the ADC (handle
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the reset and the mode).
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2020-07-13 16:59:42 +02:00
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| Bit | Bit name | Initial Value | R/W |Description |
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|----------|:--------:|---------------|:---:|----------------------------------------------------------------------------------|
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| 15 | MODE | 0 | R/W | Selects the mode |
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| 14 to 1 | - | All 0 | R | Reserved.<br>These bits are always read as 0.The write value should always be 0. |
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2021-05-13 22:35:41 +02:00
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| 0 | RESET | 0 | R/W | Reset the ADC |
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<u>Bit 15: MODE</u>
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Mode selector:
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* 0 = select the ADCSR (ADCCSR is not taken into account)
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* 1 = selecte the ADCCSR (ADCSR is not taken into account)
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<u>Bit 0: RESET</u>
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Reset the register ADCSR, ADCCSR and ADPCTL (set to 0).
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Automatically, cleared to 0 when the ADM is completelly reseted.
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2020-07-13 16:59:42 +02:00
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<u>Note</u>
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* Casio set all bit to 0
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<br>
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## A/D Port control (ADPCTL: address=0xa461008e && bitmask=0xf0ff)
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ADCSR is a 16-bit readable/writable register used to ????
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| Bit | Bit name | Initial Value | R/W |Description |
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|----------|:--------:|---------------|:---:|----------------------------------------------------------------------------------|
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| 15 to 12 | unknown | ?????? | R/W | Unknown |
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| 11 to 8 | - | All 0 | R | Reserved.<br>These bits are always read as 0.The write value should always be 0. |
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| 7 to 0 | unknown | ?????? | R/W | Unknown |
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<u>Note</u>
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* Casio set all bit to 0
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<br>
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---
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## Module Operations
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The A/D converter operates by successive approximations with 10-bit resolution.
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It has three operating modes: single mode, multi mode, and scan mode.
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To avoid malfunction, switch operating modes while the ADST bit of ADCSR is 0.
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Changing operating modes and channels and setting the ADST bit can be performed
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simultaneously.
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## Single Mode
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Single mode should be selected when only one A/D conversion on one channel is required.
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1. A/D conversion of the selected channel starts when the ADST bit of ADCSR is set
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to 1 by software.
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2. When conversion ends, the conversion results are transmitted to the A/D data
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register that corresponds to the channel.
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3. When conversion ends, the ADF bit of ADCSR is set to 1. If the ADIE bit is also
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set to 1, an ADI interrupt is requested at this time.
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4. The ADST bit holds 1 during A/D conversion. When A/D conversion is completed, the ADST
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bit is cleared to 0 and the A/D converter becomes idle. When the ADST bit is cleared to 0
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during A/D conversion, the conversion is halted and the A/D converter becomes idle.
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To clear the ADF flag to 0, first read ADF, then write 0 to ADF.
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## Multi Mode
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Multi mode should be selected when performing A/D conversions on one or more channels.
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1. When the ADST bit is set to 1 by software, A/D conversion starts with the smaller
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number of the analog input channel in the group (for instance, ADDRA, and ADDRB to ADDRD).
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2. When conversion of each channel ends, the conversion results are transmitted
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to the A/D data register that corresponds to the channel.
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3. When conversion of all selected channels ends, the ADF bit of ADCSR is set to 1.
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If the ADIE bit is also set to 1, an ADI interrupt is requested at this time.
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4. When A/D conversion is completed, the ADST bit is cleared to 0 and the A/D converter
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becomes idle. When the ADST bit is cleared to 0 during A/D conversion, the conversion is
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halted and the A/D converter becomes idle.
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To clear the ADF flag to 0, first read ADF, then write 0 to ADF.
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## Scan Mode
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Scan mode should be selected when performing A/D conversions of analog inputs on one or more
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specified channels. Scan mode is useful for monitoring analog inputs.
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1. When the ADST bit is set to 1 by software, A/D conversion starts with the smaller
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number of the analog input channel in the group (for instance, ADDRA, and ADDRB to ADDRD).
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2. When conversion of each channel ends, the conversion results are transmitted
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to the A/D data register that corresponds to the channel.
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3. When conversion of all selected channels ends, the ADF bit of ADCSR is set to 1.
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If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. A/D
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conversion then starts with the smaller number of the analog input channel.
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4. The ADST bit is not automatically cleared to 0. When the ADST bit is set to 1,
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steps 2 and 3 above are repeated. When the ADST bit is cleared to 0, the conversion
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is halted and the A/D converter becomes idle.
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To clear the ADF flag to 0, first read ADF, then write 0 to ADF.
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<br>
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---
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## Other notes
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1. Interruption informations:
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* event code: 0x560
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* Interrupt level (disable): INTC.IPRB & 0x0fff
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* Interrupt level (set): INT.IPRB \| 0xc000
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* Interrupt mask: INTC.IMR4 \| 0x08
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* Interrupt clear mask: INTC.IMCR4 \| 0x08
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2. Casio's informations:
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* Use Single mode with interruption
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* Use channel C
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* Use interrupt level 14
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* Seem to use the Channel B for internal testing(?)
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* not used by the device Graph75 - OS:01.00.0000
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* Seem start convertion each time GetKeyWait() is involved(?)
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* Seem use only the ADCSR register
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* baterry levels (in volt):
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| Device name | OS version | Full | middle | low |
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|-------------|------------|------------|------------|-----------|
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| graph75 | 01.00.0000 | ] -, 4.4[ | [4.4, 4.2] | ]4.2, - [ |
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| graph35+E | 02.05.2201 | ] -, 4.4[ | [4.4, 4.2] | ]4.2, - [ |
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| graph35+EII | 03.00.2200 | ] -, 4.4[ | [4.4, 4.2] | ]4.2, - [ |
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---
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## Small C-code ADC driver implementation
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Based on Casio's syscall `0x49C: int Battery_GetStatus()` and Casio's interrupt
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handler that I have disassembled to understand the module.
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This little piece of code will scan the battery status (channel C) and display
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the battery voltage.
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```c
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#include "tests.h"
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#include "utils.h"
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#include "hardware/sh7305/adc.h"
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#include "hardware/sh7305/power.h"
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#include "hardware/sh7305/intc.h"
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void adc_interrupt_handler(void)
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{
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// mask ADC interruption
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SH7305_INTC.IMR4.ADC = 1;
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SH7305_INTC.IPRB.ADC = 0b0000;
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// Clear interrupts flags
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// @note: Casio clear the 2 end flags but only the ADCSR.ADIF can be cleared here
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SH7305_ADC.ADCSR.ADF = 0;
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SH7305_ADC.ADCCSR.ADF = 0;
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// DEBUG: Display baterry tention
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uint32_t baterry = SH7305_ADC.ADDRC.AD * 11578;
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printk(
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"battery = %d,%d V\n",
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baterry / 1000000,
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baterry - ((baterry / 1000000) * 1000000)
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);
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|
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// Enable ADC interruption
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SH7305_INTC.IPRB.ADC = 0b1000;
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SH7305_INTC.IMCR4.ADC = 1;
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}
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|
|
void test_adc(void)
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|
{
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|
|
// mask ADC interruption
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SH7305_INTC.IMR4.ADC = 1;
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|
SH7305_INTC.IPRB.ADC = 0b0000;
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|
|
// power up the ADC module
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|
|
SH7305_POWER.MSTPCR2.ADC = 0;
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|
|
// default initialization of the ADC module
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|
|
SH7305_ADC.ADCSR.WORD = 0x0000;
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|
|
SH7305_ADC.ADCCSR.WORD = 0x0000;
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SH7305_ADC.ADCUST.WORD = 0x0000;
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|
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SH7305_ADC.ADPCTL.WORD = 0x0000;
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|
|
// Enable ADC interruption
|
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|
|
SH7305_INTC.IPRB.ADC = 0b1000;
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|
|
SH7305_INTC.IMCR4.ADC = 1;
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|
|
// Set up the ADC to scan the channel C
|
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|
SH7305_ADC.ADCSR.MULTI = 0b11; // select the scan mode
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|
|
SH7305_ADC.ADCSR.CH = 0b10; // select the channel C (ADDRC)
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|
|
SH7305_ADC.ADCSR.CKS = 0b00; // select Pφ/4
|
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|
|
SH7305_ADC.ADCSR.ADIE = 1; // enable ADI interrupt (0x560)
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|
|
SH7305_ADC.ADCSR.ADST = 1; // start ADC convertion
|
|
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|
|
|
// log and wait
|
|
|
|
printk("ADC initialized, wait interruption...\n");
|
|
|
|
while (1);
|
|
|
|
}
|
|
|
|
```
|