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gint-with-thread/fxcg50.ld

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Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/*
Linker script for fxcg50 add-ins. Most symbols are used in the startup
routine in core/start.c; some others in core/setup.c.
*/
/* All fxcg50 have SH4 processors (finally rid of compatibility issues) */
OUTPUT_ARCH(sh4)
/* ELF offers a lot of symbol/section/relocation insights */
OUTPUT_FORMAT(elf32-sh)
/* Located in core/start.c */
ENTRY(_start)
MEMORY
{
/* Userspace mapping of the add-in (without G3A header) */
core: accept large add-ins and setup TLB management (UNSTABLE) This change modifies the fx-CG 50 linker script to allow add-ins up to 2M and no longer complains about add-ins that don't fit in the TLB. It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on fxcg50) that answers TLB misses. This syscall can be called manually from an add-in to load some pages and seems to work without problem. However, this version does not provide any automatic TLB management, some key areas of the kernel are still under TLB and some user code (such as timer callbacks) is not! This version is suitable only for add-ins smaller than 220k!
2020-06-14 11:01:27 +02:00
rom (rx): o = 0x00300000, l = 2M
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* Static RAM; stack grows down from the end of this region.
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
The first 5k (0x1400 bytes) are reserved by gint for the VBR space,
which is loaded dynamically and accessed through P1 */
fxcg50: remove rram region and fxcg20-friendly VBR address This change removes the RRAM region which was inherited from the fx9860g memory layout but no longer relevant on fxcg50. This removed one occurrence of a hardcoded user stack address in the linker script, the other being the VBR address. But since the VBR only contains position-independent code that is manually "relocated" at startup, the linker script needs not actually use its value, so this is not a true dependency. gint should now more or less be able to boot up on an fxcg20, except for the hardcoded VRAM addresses which need to be moved to the fxcg20 system stack.
2020-06-18 09:59:31 +02:00
ram (rw): o = 0x08101400, l = 507k
support data loading in ILRAM, XRAM and YRAM This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
2019-09-15 19:29:47 +02:00
/* On-chip IL memory */
ilram (rwx): o = 0xe5200000, l = 4k
/* On-chip X and Y memory */
xram (rwx): o = 0xe5007000, l = 8k
yram (rwx): o = 0xe5017000, l = 8k
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
}
SECTIONS
{
/*
support data loading in ILRAM, XRAM and YRAM This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
2019-09-15 19:29:47 +02:00
** ROM sections
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*/
/* First address to be mapped to ROM */
_brom = 0x00300000;
/* Size of ROM mappings */
_srom = SIZEOF(.text) + SIZEOF(.rodata)
+ SIZEOF(.gint.drivers) + SIZEOF(.gint.blocks);
/* Machine code going to ROM:
general cleanup of the kernel * Removed .pretext sections since the TLB is now entirely dynamic; left only .text.entry for the start symbol. * Reworked the main files of src/core to move the INTC to its own driver and let the kernel handle only VBR space and CPU (now: VBR & CPUOPM). * Moved src/core/gint.c to src/core/kernel.c and centralized all driver loops that save or restore context for more robustness. This leaves the callbacks of cpu_setVBR() (formerly gint_setvbr()) pretty short. * Coalesced gint_switch_out() and gint_switch_in() into a single function callback for cpu_setVBR(). * Added an abstraction of interrupt signals as an enumerated value so that drivers no longer hardcode the IPR and IMR numbers and bits, sometimes even with isSH3() due to differences in the SH7705. * Changed the interrupt blocking method in cpu_setVBR() from SR.BL=1 to SR.IMASK=15 so that TLB misses are still handled. This removes the need for callback functions to be GMAPPED. * Moved gint_osmenu() and its utilities to a new file src/core/osmenu.c.
2020-06-20 17:18:51 +02:00
- Entry function (.text.entry)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
- Compiler-provided constructors (.ctors) and destructors (.dtors)
- All text from .text and .text.* (including user code) */
.text : {
general cleanup of the kernel * Removed .pretext sections since the TLB is now entirely dynamic; left only .text.entry for the start symbol. * Reworked the main files of src/core to move the INTC to its own driver and let the kernel handle only VBR space and CPU (now: VBR & CPUOPM). * Moved src/core/gint.c to src/core/kernel.c and centralized all driver loops that save or restore context for more robustness. This leaves the callbacks of cpu_setVBR() (formerly gint_setvbr()) pretty short. * Coalesced gint_switch_out() and gint_switch_in() into a single function callback for cpu_setVBR(). * Added an abstraction of interrupt signals as an enumerated value so that drivers no longer hardcode the IPR and IMR numbers and bits, sometimes even with isSH3() due to differences in the SH7705. * Changed the interrupt blocking method in cpu_setVBR() from SR.BL=1 to SR.IMASK=15 so that TLB misses are still handled. This removes the need for callback functions to be GMAPPED. * Moved gint_osmenu() and its utilities to a new file src/core/osmenu.c.
2020-06-20 17:18:51 +02:00
*(.text.entry)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
general cleanup of the kernel * Removed .pretext sections since the TLB is now entirely dynamic; left only .text.entry for the start symbol. * Reworked the main files of src/core to move the INTC to its own driver and let the kernel handle only VBR space and CPU (now: VBR & CPUOPM). * Moved src/core/gint.c to src/core/kernel.c and centralized all driver loops that save or restore context for more robustness. This leaves the callbacks of cpu_setVBR() (formerly gint_setvbr()) pretty short. * Coalesced gint_switch_out() and gint_switch_in() into a single function callback for cpu_setVBR(). * Added an abstraction of interrupt signals as an enumerated value so that drivers no longer hardcode the IPR and IMR numbers and bits, sometimes even with isSH3() due to differences in the SH7705. * Changed the interrupt blocking method in cpu_setVBR() from SR.BL=1 to SR.IMASK=15 so that TLB misses are still handled. This removes the need for callback functions to be GMAPPED. * Moved gint_osmenu() and its utilities to a new file src/core/osmenu.c.
2020-06-20 17:18:51 +02:00
_bctors = . ;
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.ctors .ctors.*)
general cleanup of the kernel * Removed .pretext sections since the TLB is now entirely dynamic; left only .text.entry for the start symbol. * Reworked the main files of src/core to move the INTC to its own driver and let the kernel handle only VBR space and CPU (now: VBR & CPUOPM). * Moved src/core/gint.c to src/core/kernel.c and centralized all driver loops that save or restore context for more robustness. This leaves the callbacks of cpu_setVBR() (formerly gint_setvbr()) pretty short. * Coalesced gint_switch_out() and gint_switch_in() into a single function callback for cpu_setVBR(). * Added an abstraction of interrupt signals as an enumerated value so that drivers no longer hardcode the IPR and IMR numbers and bits, sometimes even with isSH3() due to differences in the SH7705. * Changed the interrupt blocking method in cpu_setVBR() from SR.BL=1 to SR.IMASK=15 so that TLB misses are still handled. This removes the need for callback functions to be GMAPPED. * Moved gint_osmenu() and its utilities to a new file src/core/osmenu.c.
2020-06-20 17:18:51 +02:00
_ectors = . ;
_bdtors = . ;
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.dtors .dtors.*)
general cleanup of the kernel * Removed .pretext sections since the TLB is now entirely dynamic; left only .text.entry for the start symbol. * Reworked the main files of src/core to move the INTC to its own driver and let the kernel handle only VBR space and CPU (now: VBR & CPUOPM). * Moved src/core/gint.c to src/core/kernel.c and centralized all driver loops that save or restore context for more robustness. This leaves the callbacks of cpu_setVBR() (formerly gint_setvbr()) pretty short. * Coalesced gint_switch_out() and gint_switch_in() into a single function callback for cpu_setVBR(). * Added an abstraction of interrupt signals as an enumerated value so that drivers no longer hardcode the IPR and IMR numbers and bits, sometimes even with isSH3() due to differences in the SH7705. * Changed the interrupt blocking method in cpu_setVBR() from SR.BL=1 to SR.IMASK=15 so that TLB misses are still handled. This removes the need for callback functions to be GMAPPED. * Moved gint_osmenu() and its utilities to a new file src/core/osmenu.c.
2020-06-20 17:18:51 +02:00
_edtors = . ;
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
_gint_exch_start = . ;
*(.gint.exch)
_gint_exch_size = ABSOLUTE(. - _gint_exch_start);
_gint_tlbh_start = . ;
*(.gint.tlbh)
_gint_tlbh_size = ABSOLUTE(. - _gint_tlbh_start);
exc: add exception handlers, use them in the DMA This change introduces exception handlers that default to a fatal error with an on-screen description of the exception and some debugging information. It also adds the dprint() function as a definitely-needed helper and removes bootlog_unmapped() by using the exception handler for the fatal error display. (Also printf() is now required in all gint add-ins; this is sad, but space is not as much of a constraint as debugging.) Finally, the exception handler is used to handle an interrupt which is an exception in practice, the DMA address error. On fx-CG 50, additional DMA-related information is displayed on the screen. This is left out on fx-9860G as there is not enough space.
2019-09-03 22:15:00 +02:00
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.text .text.*)
} > rom
render-cg: allow VRAM in user stack This is currently unused and has some artifacts in gintctl for reasons I haven't understood yet. Will have to investigate later.
2020-07-02 15:47:11 +02:00
/* gint's interrupt handler blocks (.gint.blocks)
Although gint's blocks end up in VBR space, they are relocated at
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
startup by the library/drivers, so we store them here for now */
.gint.blocks : {
KEEP(*(.gint.blocks));
} > rom
render-cg: allow VRAM in user stack This is currently unused and has some artifacts in gintctl for reasons I haven't understood yet. Will have to investigate later.
2020-07-02 15:47:11 +02:00
/* Exposed driver interfaces (.gint.drivers)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
The driver information is required to start and configure the
driver, even if the symbols are not referenced */
.gint.drivers : {
_bdrv = . ;
More timers, RTC, basic overclock-resistant keyboard, CPG, PFC, driver levels.
2018-08-19 17:11:37 +02:00
KEEP(*(.gint.drivers.0));
KEEP(*(.gint.drivers.1));
KEEP(*(.gint.drivers.2));
KEEP(*(.gint.drivers.3));
KEEP(*(.gint.drivers.4));
KEEP(*(.gint.drivers.5));
KEEP(*(.gint.drivers.6));
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
_edrv = . ;
} > rom
/* Read-only data going to ROM:
- Resources or assets from fxconv or similar converters
- Data marked read-only by the compiler (.rodata and .rodata.*) */
.rodata : SUBALIGN(4) {
/* Put these first, they need to be 4-aligned */
support data loading in ILRAM, XRAM and YRAM This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
2019-09-15 19:29:47 +02:00
*(.rodata.4)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.rodata .rodata.*)
} > rom
/*
support data loading in ILRAM, XRAM and YRAM This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
2019-09-15 19:29:47 +02:00
** RAM sections
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*/
. = ORIGIN(ram);
/* BSS data going to RAM. The BSS section is to be stripped from the
ELF file later, and wiped at startup */
.bss (NOLOAD) : {
_rbss = . ;
render-cg: allow VRAM in user stack This is currently unused and has some artifacts in gintctl for reasons I haven't understood yet. Will have to investigate later.
2020-07-02 15:47:11 +02:00
*(.bss.vram)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.bss COMMON)
. = ALIGN(16);
} > ram :NONE
_sbss = SIZEOF(.bss);
code review and display driver changes t6k11: use the gint array for variant detection r61524: use true triple buffering by default display: define DWIDTH and DHEIGHT display: add C_RGB(r,g,b) (0 ≤ r,g,b ≤ 31) [fxcg50]
2020-02-23 15:49:55 +01:00
/* Read-write data sections going to RAM (.data and .data.*) */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
.data ALIGN(4) : ALIGN(4) {
_ldata = LOADADDR(.data);
_rdata = . ;
*(.data .data.*)
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* References to mapped code - no relocation needed */
*(.gint.mappedrel)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
. = ALIGN(16);
} > ram AT> rom
way too much, including bopti/topti, timers, and more.
2019-02-21 20:58:38 +01:00
/* Read-write data sub-aligned to 4 bytes (mainly from fxconv) */
.data.4 : SUBALIGN(4) {
*(.data.4)
. = ALIGN(16);
} > ram AT> rom
_sdata = SIZEOF(.data) + SIZEOF(.data.4);
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
support data loading in ILRAM, XRAM and YRAM This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
2019-09-15 19:29:47 +02:00
/* On-chip memory sections: IL, X and Y memory */
. = ORIGIN(ilram);
.ilram ALIGN(4) : ALIGN(4) {
_lilram = LOADADDR(.ilram);
_rilram = . ;
*(.ilram)
core: backport TLB handling to fx9860g, fix return-to-menu (UNSTABLE) This change ports the TLB management system to fx9860g through %003. This raises the size limit for add-ins to about 500k. Because SH3 fx9860g does not have ILRAM, the GMAPPED attribute has been made to generate content to a .gint.mapped section which is sent to the P1 RAM section historically dubbed "real ram" in which gint's data and VBR are installed. (Now that I think about it, gint's data should try to go to normal RAM instead to reduce pressure on this invasion.) Return-to-menu was also fixed on both platforms by narrowing down the need for code to remain mapped to the chance of running it with interrupts disabled. The natural distribution of GMAPPED under this criterion showed that _gint_setvbr had been left under TLB control; moving it to the proper RAM area fixed gint switches. Finally, an omission in the bound checks for mappable TEA addresses (TEA >= 0x00300000) prevented the appearance of a non-interactible System ERROR popup when some unmapped addresses are accessed. This version still does not enable interrupts in timer callbacks, exposing any application to a crash if a timer underflows while its callback is not mapped. It is not suitable for any stable application!
2020-06-15 20:55:18 +02:00
/* Code that must remain mapped is placed here */
*(.gint.mapped)
support data loading in ILRAM, XRAM and YRAM This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
2019-09-15 19:29:47 +02:00
. = ALIGN(16);
} > ilram AT> rom
. = ORIGIN(xram);
.xram ALIGN(4) : ALIGN(4) {
_lxram = LOADADDR(.xram);
_rxram = . ;
*(.xram)
. = ALIGN(16);
} > xram AT> rom
. = ORIGIN(yram);
.yram ALIGN(4) : ALIGN(4) {
_lyram = LOADADDR(.yram);
_ryram = . ;
*(.yram)
. = ALIGN(16);
} > yram AT> rom
_silram = SIZEOF(.ilram);
_sxram = SIZEOF(.xram);
_syram = SIZEOF(.yram);
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
/* gint's uninitialized BSS section, going to static RAM. All the large
data arrays will be located here */
.gint.bss (NOLOAD) : {
remove the .gint.data section Since both platforms now have their VBR and gint-specific data loaded along the add-in's data, the .gint.data section is entirely unused. The .gint.bss section is still used for uninitialized objects (it has different semantics than .bss which is initially cleared) and the .gint.data.sh3 and .gint.bss.sh3 sections that are dropped on the SH4-only fx-CG 50 are also still used.
2020-07-10 16:36:05 +02:00
*(.gint.bss)
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
. = ALIGN(16);
fxcg50: remove rram region and fxcg20-friendly VBR address This change removes the RRAM region which was inherited from the fx9860g memory layout but no longer relevant on fxcg50. This removed one occurrence of a hardcoded user stack address in the linker script, the other being the VBR address. But since the VBR only contains position-independent code that is manually "relocated" at startup, the linker script needs not actually use its value, so this is not a true dependency. gint should now more or less be able to boot up on an fxcg20, except for the hardcoded VRAM addresses which need to be moved to the fxcg20 system stack.
2020-06-18 09:59:31 +02:00
} > ram :NONE
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
_sgbss = SIZEOF(.gint.bss);
/*
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
** Unused sections
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*/
/DISCARD/ : {
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* SH3-only data sections */
*(.gint.data.sh3 .gint.bss.sh3)
/* Debug sections (often from libgcc) */
More interrupt system, exceptions, timers.
2018-08-01 20:41:36 +02:00
*(.debug_info .debug_abbrev .debug_loc .debug_aranges
.debug_ranges .debug_line .debug_str)
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* Java class registration (why are they even here?!) */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.jcr)
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* Asynchronous unwind tables: no C++ exception handling */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.eh_frame_hdr)
*(.eh_frame)
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* Comments or anything the compiler might generate */
Hybrid build system and runtime (no interrupts). t6k11 driver. Basic r61524 driver.
2018-04-19 13:24:26 +02:00
*(.comment)
}
}