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gint-with-thread/src/kernel/tlbh.S

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core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
.global _gint_tlbh
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
.section .gint.tlbh, "ax"
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
.align 4
_gint_tlbh:
sts.l pr, @-r15
stc.l gbr, @-r15
sts.l mach, @-r15
sts.l macl, @-r15
/* Get HWMPU in gint's hardware info. If last bit is set, we're SH3 */
mov.l .gint, r0
mov.l @r0, r0
tst #1, r0
mov.l .tea_sh4, r0
bt test_tea
mov.l .tea_sh3, r0
test_tea:
core: backport TLB handling to fx9860g, fix return-to-menu (UNSTABLE) This change ports the TLB management system to fx9860g through %003. This raises the size limit for add-ins to about 500k. Because SH3 fx9860g does not have ILRAM, the GMAPPED attribute has been made to generate content to a .gint.mapped section which is sent to the P1 RAM section historically dubbed "real ram" in which gint's data and VBR are installed. (Now that I think about it, gint's data should try to go to normal RAM instead to reduce pressure on this invasion.) Return-to-menu was also fixed on both platforms by narrowing down the need for code to remain mapped to the chance of running it with interrupts disabled. The natural distribution of GMAPPED under this criterion showed that _gint_setvbr had been left under TLB control; moving it to the proper RAM area fixed gint switches. Finally, an omission in the bound checks for mappable TEA addresses (TEA >= 0x00300000) prevented the appearance of a non-interactible System ERROR popup when some unmapped addresses are accessed. This version still does not enable interrupts in timer callbacks, exposing any application to a crash if a timer underflows while its callback is not mapped. It is not suitable for any stable application!
2020-06-15 20:55:18 +02:00
/* Check TEA to see if we want to map a page or raise a SysERROR */
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
mov.l @r0, r0
mov.l .max_mapped_rom, r1
cmp/ge r1, r0
bt panic
core: backport TLB handling to fx9860g, fix return-to-menu (UNSTABLE) This change ports the TLB management system to fx9860g through %003. This raises the size limit for add-ins to about 500k. Because SH3 fx9860g does not have ILRAM, the GMAPPED attribute has been made to generate content to a .gint.mapped section which is sent to the P1 RAM section historically dubbed "real ram" in which gint's data and VBR are installed. (Now that I think about it, gint's data should try to go to normal RAM instead to reduce pressure on this invasion.) Return-to-menu was also fixed on both platforms by narrowing down the need for code to remain mapped to the chance of running it with interrupts disabled. The natural distribution of GMAPPED under this criterion showed that _gint_setvbr had been left under TLB control; moving it to the proper RAM area fixed gint switches. Finally, an omission in the bound checks for mappable TEA addresses (TEA >= 0x00300000) prevented the appearance of a non-interactible System ERROR popup when some unmapped addresses are accessed. This version still does not enable interrupts in timer callbacks, exposing any application to a crash if a timer underflows while its callback is not mapped. It is not suitable for any stable application!
2020-06-15 20:55:18 +02:00
mov.l .min_mapped_rom, r1
cmp/ge r1, r0
bf panic
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
map:
core: backport TLB handling to fx9860g, fix return-to-menu (UNSTABLE) This change ports the TLB management system to fx9860g through %003. This raises the size limit for add-ins to about 500k. Because SH3 fx9860g does not have ILRAM, the GMAPPED attribute has been made to generate content to a .gint.mapped section which is sent to the P1 RAM section historically dubbed "real ram" in which gint's data and VBR are installed. (Now that I think about it, gint's data should try to go to normal RAM instead to reduce pressure on this invasion.) Return-to-menu was also fixed on both platforms by narrowing down the need for code to remain mapped to the chance of running it with interrupts disabled. The natural distribution of GMAPPED under this criterion showed that _gint_setvbr had been left under TLB control; moving it to the proper RAM area fixed gint switches. Finally, an omission in the bound checks for mappable TEA addresses (TEA >= 0x00300000) prevented the appearance of a non-interactible System ERROR popup when some unmapped addresses are accessed. This version still does not enable interrupts in timer callbacks, exposing any application to a crash if a timer underflows while its callback is not mapped. It is not suitable for any stable application!
2020-06-15 20:55:18 +02:00
/* If TEA is mappable, map a page and return */
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
#ifdef FX9860G
mov #3, r0
#endif
#ifdef FXCG50
mov #12, r0
#endif
mov.l .syscall, r2
jsr @r2
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
nop
lds.l @r15+, macl
lds.l @r15+, mach
ldc.l @r15+, gbr
lds.l @r15+, pr
rte
nop
panic:
core: backport TLB handling to fx9860g, fix return-to-menu (UNSTABLE) This change ports the TLB management system to fx9860g through %003. This raises the size limit for add-ins to about 500k. Because SH3 fx9860g does not have ILRAM, the GMAPPED attribute has been made to generate content to a .gint.mapped section which is sent to the P1 RAM section historically dubbed "real ram" in which gint's data and VBR are installed. (Now that I think about it, gint's data should try to go to normal RAM instead to reduce pressure on this invasion.) Return-to-menu was also fixed on both platforms by narrowing down the need for code to remain mapped to the chance of running it with interrupts disabled. The natural distribution of GMAPPED under this criterion showed that _gint_setvbr had been left under TLB control; moving it to the proper RAM area fixed gint switches. Finally, an omission in the bound checks for mappable TEA addresses (TEA >= 0x00300000) prevented the appearance of a non-interactible System ERROR popup when some unmapped addresses are accessed. This version still does not enable interrupts in timer callbacks, exposing any application to a crash if a timer underflows while its callback is not mapped. It is not suitable for any stable application!
2020-06-15 20:55:18 +02:00
/* Otherwise, panic by defaulting to the exception handler (the TLB
miss may still be resolved by a panic handler) */
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
lds.l @r15+, macl
lds.l @r15+, mach
ldc.l @r15+, gbr
lds.l @r15+, pr
stc vbr, r0
mov #1, r1
shll8 r1
add r1, r0
jmp @r0
nop
.align 4
.gint:
.long _gint
.tea_sh4:
.long 0xff00000c
.tea_sh3:
.long 0xfffffffc
core: backport TLB handling to fx9860g, fix return-to-menu (UNSTABLE) This change ports the TLB management system to fx9860g through %003. This raises the size limit for add-ins to about 500k. Because SH3 fx9860g does not have ILRAM, the GMAPPED attribute has been made to generate content to a .gint.mapped section which is sent to the P1 RAM section historically dubbed "real ram" in which gint's data and VBR are installed. (Now that I think about it, gint's data should try to go to normal RAM instead to reduce pressure on this invasion.) Return-to-menu was also fixed on both platforms by narrowing down the need for code to remain mapped to the chance of running it with interrupts disabled. The natural distribution of GMAPPED under this criterion showed that _gint_setvbr had been left under TLB control; moving it to the proper RAM area fixed gint switches. Finally, an omission in the bound checks for mappable TEA addresses (TEA >= 0x00300000) prevented the appearance of a non-interactible System ERROR popup when some unmapped addresses are accessed. This version still does not enable interrupts in timer callbacks, exposing any application to a crash if a timer underflows while its callback is not mapped. It is not suitable for any stable application!
2020-06-15 20:55:18 +02:00
.min_mapped_rom:
.long 0x00300000
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
.max_mapped_rom:
.long 0x00300000 + _srom
core: finalize TLB management in timer callbacks (STABLE) This change enables interrupts within timer callbacks, making it possible to load pages to MMU while handling a timer underflow. The call to TLB_LoadPTEH() has been moved directly into the VBR handler to avoid jumping to ILRAM for a short call on SH4. The TMU and ETMU handlers have been changed to callback through a new function gint_inth_callback() that saves the user bank and a few registers, then invokes the callback with interrupts enabled and in user bank; until now, callbacks were invoked with interrupts disabled and in kernel bank. Note that IMASK is still set so a callback can only be interrupted by a high-priority interrupt. A timer_wait() function has also been added to simplify tests that involve timers. Finally, the priority level of the TMU0 underflow interrupt has been set to 13 (as per the comments) instead of 7. This version is the first stable version that handles TLB misses transparently for large add-ins. It is suitable for every gint application.
2020-06-17 11:36:05 +02:00
#ifdef FX9860G
.syscall:
.long 0x80010070
#endif
#ifdef FXCG50
.syscall:
.long 0x80020070
#endif