8 Commits

Author	SHA1	Message	Date
Lephe	bf21246f13	kernel: mask interrupts during callbacks on fx-CG Manager ... The fx-CG Manager holds but ignores the CPUOPM.INTMU bit, which means that we have to mask interrupts as on SH3.	2020-07-20 16:44:27 +02:00
Lephe	7d63a1b536	r61524 render-cg: support Prizm and fx-CG Manager ... This change adds a new HWCALC model, HWCALC_FXCG_MANAGER, which identifies Casio's official fx-CG Manager software. Both the Prizm and, to my surprise, the fx-CG Manager use the old RAM address of 88000000 (P1) and a8000000 (P2) instead of the new fx-CG 50 address of 8c000000 (P1) and ac000000 (P2). The VRAM is hence adjusted at startup to move hardcoded pointers into the proper space. Added to the kernel moving the VBR space dynamically on the Prizm, this allows gint to be fully compatible with these platforms. The fx-CG Manager is detected by its product ID made of 0xff. Also adds a proper interface to the R61524 driver, even though it's not any more complete than previously, and fixes an oversight where the HWURAM entry of the kernel data array was no longer computed since the TLB management change. As of now, the fx-CG Manager still has a bug regarding return-to-menu since returning from the main menu doesn't work very well and often loops. This has been seen occasionally on some Graph 90+E so it's unlikely to be a platform-specific problem.	2020-07-02 15:48:19 +02:00
Lephe	a91a0a483b	core: remove some useless hardware info	2020-06-20 19:23:50 +02:00
Lephe	0498344349	periodic check of SH3 compatibility	2020-05-31 22:26:30 +02:00
Lephe	61da7debc8	code review and display driver changes ... t6k11: use the gint array for variant detection r61524: use true triple buffering by default display: define DWIDTH and DHEIGHT display: add C_RGB(r,g,b) (0 ≤ r,g,b ≤ 31) [fxcg50]	2020-02-23 16:05:25 +01:00
Lephe	552b9b9a43	dma: only expose API on fxcg50 ... Currently there seems to be no DMA at all on fx9860g. Further investigation would be required, because this would be the first major difference between the SH7305's found in fx9860g and fxcg50 models. An automated peripheral register discovery strategy might help, but identifying discovered registers would be non trivial. Also use the pruning ability of the Makefile to avoid troublesome ifdef's in the code.	2019-09-15 10:20:37 +02:00
lephe	24fbeab55b	core: provide MPU type on unknown platforms ... This makes it possible to write application code without specifying the target machine, which is especially useful for libraries. The first user of this system is libprof.	2019-07-16 15:39:33 -04:00
lephe	3324d58afa	core: add a hardware detection interface	2019-07-04 12:11:43 -04:00