170 lines
3.9 KiB
C
170 lines
3.9 KiB
C
#ifndef __GINTRACE_UBC_H__
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# define __GINTRACE_UBC_H__
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#include <stddef.h>
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#include <stdint.h>
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#include <gint/defs/types.h>
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//---
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// Hardware information - Same as the SH7724
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//---
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#define SH7305_UBC (*(volatile struct sh7305_ubc *)0xff200000)
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struct sh7305_ubc {
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//---
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// Channel 0
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//---
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lword_union(CBR0,
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uint32_t MFE : 1; /* Match Flag Enable */
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uint32_t AIE : 1; /* ASID Enable */
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uint32_t MFI : 6; /* Match Flag Specify */
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uint32_t AIV : 8; /* ASID Specify */
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uint32_t const : 1; /* All 0 */
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uint32_t SZ : 3; /* Operend Size Select */
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uint32_t const : 4; /* All 0 */
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uint32_t CD : 2; /* Bus Select */
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uint32_t ID : 2; /* Instr Fetch/Operand Access Select */
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uint32_t const : 1; /* All 0 */
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uint32_t RW : 2; /* Bus Command Select */
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uint32_t CE : 1; /* Channel Enable */
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);
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lword_union(CRR0,
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uint32_t const : 18; /* All 0 */
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uint32_t const : 1; /* All 1 */
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uint32_t const : 11; /* All 0 */
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uint32_t PCB : 1; /* PC Breack Select */
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uint32_t BIE : 1; /* Breack Enable */
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);
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uint32_t CAR0; /* Compare Address */
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uint32_t CAMR0; /* Compare Address Mask */
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pad(0x10);
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//---
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// Channel 1
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//---
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lword_union(CBR1,
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uint32_t MFE : 1; /* Match Flag Enable */
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uint32_t AIE : 1; /* ASID Enable */
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uint32_t MFI : 6; /* Match Flag Specify */
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uint32_t AIV : 8; /* ASID Specify */
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uint32_t DBE : 1; /* Data Value Enable */
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uint32_t SZ : 3; /* Operend Size Select */
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uint32_t ETBE : 1; /* Execution Count Value Enable */
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uint32_t const : 3; /* All 0 */
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uint32_t CD : 2; /* Bus Select */
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uint32_t ID : 2; /* Instr Fetch/Operand Access Select */
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uint32_t const : 1; /* All 0 */
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uint32_t RW : 2; /* Bus Command Select */
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uint32_t CE : 1; /* Channel Enable */
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);
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lword_union(CRR1,
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uint32_t const : 18; /* All 0 */
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uint32_t const : 1; /* All 1 */
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uint32_t const : 11; /* All 0 */
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uint32_t PCB : 1; /* PC Breack Select */
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uint32_t BIE : 1; /* Breack Enable */
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);
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uint32_t CAR1; /* Compare Address */
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uint32_t CAMR1; /* Compare Address Mask */
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//--
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// Compare Data Part.
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//---
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uint32_t CDR1; /* Compare Data Value */
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uint32_t CDMR1; /* Compare Data Value Mask */
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//---
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// Execution Count Register
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//---
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lword_union(CETR1,
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uint32_t const : 20; /* All 0 */
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uint32_t CET : 12; /* Execution Count */
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);
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pad(0x5c4);
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//---
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// Channel Match Flag Register
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//---
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lword_union(CCMFR,
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uint32_t const : 30; /* All 0 */
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uint32_t MF1 : 1; /* Channel 1 Condition Match Flag */
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uint32_t MF0 : 1; /* Channel 0 Condition Match Flag */
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);
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pad(0x1c);
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//---
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// Control Register
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//---
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lword_union(CBCR,
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uint32_t const : 31; /* All 0 */
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uint32_t UBDE : 1; /* UBC Debugging Support Enable */
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);
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};
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/* hardware context */
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struct sh7305_ubc_context {
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uint32_t cbr0;
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uint32_t crr0;
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uint32_t car0;
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uint32_t camr0;
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uint32_t cbr1;
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uint32_t crr1;
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uint32_t car1;
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uint32_t camr1;
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uint32_t cdr1;
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uint32_t cdmr1;
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uint32_t cetr1;
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uint32_t ccmfr;
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uint32_t cbr;
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};
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//---
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// Software information
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//---
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/* ucontext: UBC context */
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struct ucontext {
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uintptr_t reg[16];
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uintptr_t gbr;
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uintptr_t macl;
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uintptr_t mach;
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uintptr_t ssr;
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uintptr_t spc;
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uintptr_t pr;
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};
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//---
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// User API
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//---
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/* ub_install(): Install UBC driver */
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extern void ubc_install(void);
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extern void ubc_uninstall(void);
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/* ubc_set_handler(): Setup the handler */
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extern int ubc_set_handler(void (*handler)(struct ucontext *ctx));
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/* ubc_set_breakpoint(): Setup one breakpoint */
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extern int ubc_set_breakpoint(int channel, void *address, void *mask);
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/* ubc_block(): Block UBC interruption */
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extern int ubc_block(void);
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/* ubc_unblock(): Unblock UBC interruption */
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extern int ubc_unblock(void);
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//---
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// "low-level" interface
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//---
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/* ubc_kernel_dbr_set(): Switch DBR register */
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extern void *ubc_kernel_dbr_set(void *dbr);
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/* ubc_kernel_inth: Content the relocalised UBC interrupt handler */
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extern void (*ubc_kernel_inth)(void);
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/* ubc_kernel_update(): Perform a cache reset */
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extern void ubc_kernel_update(void);
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#endif /*__GINTRACE_UBC_H__*/
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