134 lines
3.6 KiB
C
134 lines
3.6 KiB
C
#include "gintrace/ubc.h"
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#include <gint/mpu/power.h>
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#include <gint/drivers.h>
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/* internal UBC driver information */
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struct sh7305_ubc_context ubctx;
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void (*ubc_handler)(struct ucontext *ctx) = NULL;
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int ubc_driver_installed = 0;
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/* ubc_install(): Install the UBC driver */
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void ubc_install(void)
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{
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/* power on the UBC */
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SH7305_POWER.MSTPCR0.UDB = 0;
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/* switch the DBR */
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ubc_kernel_dbr_set(*ubc_kernel_inth);
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/* check if the driver has already been installed */
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if (ubc_driver_installed != 0) {
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SH7305_UBC.CBR0.lword = ubctx.cbr0;
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SH7305_UBC.CRR0.lword = ubctx.crr0;
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SH7305_UBC.CAR0 = ubctx.car0;
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SH7305_UBC.CAMR0 = ubctx.camr0;
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SH7305_UBC.CBR1.lword = ubctx.cbr1;
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SH7305_UBC.CRR1.lword = ubctx.crr1;
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SH7305_UBC.CAR1 = ubctx.car1;
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SH7305_UBC.CAMR1 = ubctx.camr1;
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SH7305_UBC.CDR1 = ubctx.cdr1;
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SH7305_UBC.CDMR1 = ubctx.cdmr1;
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SH7305_UBC.CETR1.lword = ubctx.cdr1;
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return;
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}
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/* wipe sofware information */
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ubc_handler = NULL;
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/* Default initialization */
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SH7305_UBC.CBR0.MFI = 0b000000;
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SH7305_UBC.CBR0.CE = 0;
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SH7305_UBC.CBR1.MFI = 0b000000;
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SH7305_UBC.CBR1.CE = 0;
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SH7305_UBC.CBCR.UBDE = 1;
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/* indicate that the UBC driver is installed */
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ubc_driver_installed = 1;
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}
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/* ubc_uninstall(): Uninstall the UBC driver */
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void ubc_uninstall(void)
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{
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if (ubc_driver_installed == 1) {
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ubctx.cbr0 = SH7305_UBC.CBR0.lword;
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ubctx.crr0 = SH7305_UBC.CRR0.lword;
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ubctx.car0 = SH7305_UBC.CAR0;
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ubctx.camr0 = SH7305_UBC.CAMR0;
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ubctx.cbr1 = SH7305_UBC.CBR1.lword;
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ubctx.crr1 = SH7305_UBC.CRR1.lword;
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ubctx.car1 = SH7305_UBC.CAR1;
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ubctx.camr1 = SH7305_UBC.CAMR1;
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ubctx.cdr1 = SH7305_UBC.CDR1;
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ubctx.cdmr1 = SH7305_UBC.CDMR1;
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ubctx.cdr1 = SH7305_UBC.CETR1.lword;
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}
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}
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/* ubc_set_breakpoint(): Setup one breakpoint */
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int ubc_set_breakpoint(int channel, void *address, void *mask)
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{
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if (channel == 0) {
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// Setup Channel 0.
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SH7305_UBC.CRR0.PCB = 1; // Set PC break after instruction break.
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SH7305_UBC.CRR0.BIE = 1; // Request a Break.
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SH7305_UBC.CBR0.MFE = 0; // Enable Match Flag.
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SH7305_UBC.CBR0.MFI = 0b000000; // Set UBC.CCMFR.MF0 = 1, when break occur.
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SH7305_UBC.CBR0.AIE = 0; // Disable ASID check.
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SH7305_UBC.CBR0.SZ = 0b010; // Disable Match condition.
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SH7305_UBC.CBR0.CD = 0; // Use Operand Bus for Operand Access.
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SH7305_UBC.CBR0.ID = 0b01; // Selecte instruction Fetch cycle.
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SH7305_UBC.CBR0.RW = 0b11; // Use Read or Write for match condition.
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SH7305_UBC.CBR0.CE = 0; // Disable Channel 0.
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SH7305_UBC.CAR0 = (uintptr_t)address; // update break address.
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SH7305_UBC.CAMR0 = (uintptr_t)mask; // update break address.
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SH7305_UBC.CBR0.CE = 1; // enable channel.
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} else {
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//TODO
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return (-1);
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}
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ubc_kernel_update();
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return (0);
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}
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/* ubc_set_handler(): Set the "user" handler */
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int ubc_set_handler(void (*handler)(struct ucontext *ctxt))
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{
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ubc_handler = handler;
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return (0);
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}
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static uint32_t __ubc_block_counter = 0;
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static uint32_t __ubc_cbcr_ubde = 0;
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static uint32_t __ubc_cbr0_ce = 0;
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/* ubc_block(): Block UBC interruption */
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int ubc_block(void)
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{
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if (__ubc_block_counter == 0) {
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__ubc_cbr0_ce = SH7305_UBC.CBR0.CE;
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__ubc_cbcr_ubde = SH7305_UBC.CBCR.UBDE;
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SH7305_UBC.CBCR.UBDE = 0;
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SH7305_UBC.CBR0.CE = 0;
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ubc_kernel_update();
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}
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__ubc_block_counter += 1;
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return (0);
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}
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/* ubc_block(): Block UBC interruption */
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int ubc_unblock(void)
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{
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if (__ubc_block_counter <= 0)
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return (-1);
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__ubc_block_counter -= 1;
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if (__ubc_block_counter == 0) {
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SH7305_UBC.CBCR.UBDE = __ubc_cbcr_ubde;
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SH7305_UBC.CBR0.CE = __ubc_cbr0_ce;
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ubc_kernel_update();
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}
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return (0);
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}
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