mibi88
/
PythonExtra
forked from Lephenixnoir/PythonExtra
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

renesas-ra: Add new port to Renesas RA. 

Signed-off-by: Takeo Takahashi <takeo.takahashi.xv@renesas.com>
This commit is contained in:
Takeo Takahashi 2022-04-29 10:49:44 +09:00
parent 4c9b00b425
commit 0f57ccf7f2
272 changed files with 30866 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

540
ports/renesas-ra/Makefile Normal file
View File

@ -0,0 +1,540 @@
# Select the board to build for: if not given on the command line,
# then default to RA6M2_EK.
BOARD ?= RA6M2_EK
# If the build directory is not given, make it reflect the board name.
BUILD ?= build-$(BOARD)
BOARD_DIR ?= boards/$(BOARD)
ifeq ($(wildcard $(BOARD_DIR)/.),)
$(error Invalid BOARD specified: $(BOARD_DIR))
endif
ifeq ($(BOARD),RA4M1_CLICKER)
BOARD_LOW = ra4m1_ek
CMSIS_MCU_LOW = ra4m1
CMSIS_MCU_CAP = RA4M1
USE_FSP_LPM = 0
endif
ifeq ($(BOARD),RA4M1_EK)
BOARD_LOW = ra4m1_ek
CMSIS_MCU_LOW = ra4m1
CMSIS_MCU_CAP = RA4M1
USE_FSP_LPM = 0
endif
ifeq ($(BOARD),RA4W1_EK)
BOARD_LOW = ra4w1_ek
CMSIS_MCU_LOW = ra4w1
CMSIS_MCU_CAP = RA4W1
USE_FSP_LPM = 1
endif
ifeq ($(BOARD),RA6M1_EK)
BOARD_LOW = ra6m1_ek
CMSIS_MCU_LOW = ra6m1
CMSIS_MCU_CAP = RA6M1
USE_FSP_LPM = 1
endif
ifeq ($(BOARD),RA6M2_EK)
BOARD_LOW = ra6m2_ek
CMSIS_MCU_LOW = ra6m2
CMSIS_MCU_CAP = RA6M2
USE_FSP_LPM = 1
endif
# select use wrapper function of FSP library
USE_FSP_FLASH = 1
include ../../py/mkenv.mk
-include mpconfigport.mk
include $(BOARD_DIR)/mpconfigboard.mk
# Files that are generated and needed before the QSTR build.
#QSTR_GENERATED_HEADERS = $(BUILD)/pins_qstr.h $(BUILD)/modstm_qstr.h
QSTR_GENERATED_HEADERS = $(BUILD)/pins_qstr.h
# qstr definitions (must come before including py.mk)
QSTR_DEFS += qstrdefsport.h $(QSTR_GENERATED_HEADERS)
QSTR_GLOBAL_DEPENDENCIES += mpconfigboard_common.h $(BOARD_DIR)/mpconfigboard.h $(QSTR_GENERATED_HEADERS)
# MicroPython feature configurations
MICROPY_ROM_TEXT_COMPRESSION ?= 1
# File containing description of content to be frozen into firmware.
FROZEN_MANIFEST ?= boards/manifest.py
# include py core make definitions
include $(TOP)/py/py.mk
GIT_SUBMODULES += lib/fsp
MCU_SERIES_UPPER = $(shell echo $(MCU_SERIES) | tr '[:lower:]' '[:upper:]')
CMSIS_MCU_LOWER = $(shell echo $(CMSIS_MCU) | tr '[:upper:]' '[:lower:]')
LD_DIR=boards
CMSIS_DIR=lib/cmsis/inc
HAL_DIR=lib/fsp
STARTUP_FILE ?= lib/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o
SYSTEM_FILE ?= lib/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o
# Select the cross compile prefix
CROSS_COMPILE ?= arm-none-eabi-
INC += -I.
INC += -I$(TOP)
INC += -I$(BUILD)
INC += -I$(TOP)/$(CMSIS_DIR)
INC += -I$(TOP)/$(HAL_DIR)
INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc
INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc/api
INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc/instances
INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include
#INC += -Ilwip_inc
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2))
INC += -Ira
endif
INC += -I$(BOARD_DIR)/ra_gen
INC += -I$(BOARD_DIR)/ra_cfg/fsp_cfg
INC += -I$(BOARD_DIR)/ra_cfg/fsp_cfg/bsp
INC += -Idebug
CFLAGS += -D$(CMSIS_MCU)
CFLAGS += -DRA_HAL_H='<$(CMSIS_MCU)_hal.h>'
# Basic Cortex-M flags
CFLAGS_CORTEX_M = -mthumb
# Select hardware floating-point support
SUPPORTS_HARDWARE_FP_SINGLE = 0
SUPPORTS_HARDWARE_FP_DOUBLE = 0
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),m4))
CFLAGS_CORTEX_M += -mfpu=fpv4-sp-d16 -mfloat-abi=hard
SUPPORTS_HARDWARE_FP_SINGLE = 1
endif
# Options for particular MCU series
CFLAGS_MCU_RA4M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
CFLAGS_MCU_RA4W1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
CFLAGS_MCU_RA6M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
CFLAGS_MCU_RA6M2 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
CFLAGS += $(INC) -Wall -Wpointer-arith -Werror -Wdouble-promotion -Wfloat-conversion -std=gnu99 -nostdlib $(CFLAGS_MOD) $(CFLAGS_EXTRA)
#CFLAGS += -D$(CMSIS_MCU)
CFLAGS += $(CFLAGS_MCU_$(CMSIS_MCU))
CFLAGS += $(COPT)
CFLAGS += -I$(BOARD_DIR)
# Configure floating point support
ifeq ($(MICROPY_FLOAT_IMPL),double)
CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_DOUBLE
else
ifeq ($(MICROPY_FLOAT_IMPL),none)
CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_NONE
else
CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_FLOAT
CFLAGS += -fsingle-precision-constant
endif
endif
LDFLAGS = -nostdlib -L $(LD_DIR) $(addprefix -T,$(LD_FILES)) -Map=$(@:.elf=.map) --cref
LDFLAGS += --defsym=_estack_reserve=8
LIBS += "$(shell $(CC) $(CFLAGS) -print-libgcc-file-name)"
# Remove uncalled code from the final image.
CFLAGS += -fdata-sections -ffunction-sections
LDFLAGS += --gc-sections
# Debugging/Optimization
ifeq ($(DEBUG), 1)
CFLAGS += -g -DPENDSV_DEBUG
#COPT = -Og
COPT = -Os
# Disable text compression in debug builds
MICROPY_ROM_TEXT_COMPRESSION = 0
else
COPT += -Os -DNDEBUG
endif
# Flags for optional C++ source code
CXXFLAGS += $(filter-out -Wmissing-prototypes -Wold-style-definition -std=gnu99,$(CFLAGS))
CXXFLAGS += $(CXXFLAGS_MOD)
ifneq ($(SRC_CXX)$(SRC_MOD_CXX),)
LIBSTDCPP_FILE_NAME = "$(shell $(CXX) $(CXXFLAGS) -print-file-name=libstdc++.a)"
LDFLAGS += -L"$(shell dirname $(LIBSTDCPP_FILE_NAME))"
endif
# Options for mpy-cross
MPY_CROSS_FLAGS += -march=armv7m
SHARED_SRC_C += $(addprefix shared/,\
libc/string0.c \
netutils/dhcpserver.c \
netutils/netutils.c \
netutils/trace.c \
readline/readline.c \
runtime/gchelper_native.c \
runtime/interrupt_char.c \
runtime/mpirq.c \
runtime/pyexec.c \
runtime/stdout_helpers.c \
runtime/sys_stdio_mphal.c \
timeutils/timeutils.c \
)
ifeq ($(MICROPY_FLOAT_IMPL),double)
LIBM_SRC_C += $(addprefix lib/libm_dbl/,\
__cos.c \
__expo2.c \
__fpclassify.c \
__rem_pio2.c \
__rem_pio2_large.c \
__signbit.c \
__sin.c \
__tan.c \
acos.c \
acosh.c \
asin.c \
asinh.c \
atan.c \
atan2.c \
atanh.c \
ceil.c \
cos.c \
cosh.c \
copysign.c \
erf.c \
exp.c \
expm1.c \
floor.c \
fmod.c \
frexp.c \
ldexp.c \
lgamma.c \
log.c \
log10.c \
log1p.c \
modf.c \
nearbyint.c \
pow.c \
rint.c \
round.c \
scalbn.c \
sin.c \
sinh.c \
tan.c \
tanh.c \
tgamma.c \
trunc.c \
)
ifeq ($(SUPPORTS_HARDWARE_FP_DOUBLE),1)
LIBM_SRC_C += lib/libm_dbl/thumb_vfp_sqrt.c
else
LIBM_SRC_C += lib/libm_dbl/sqrt.c
endif
else
LIBM_SRC_C += $(addprefix lib/libm/,\
math.c \
acoshf.c \
asinfacosf.c \
asinhf.c \
atan2f.c \
atanf.c \
atanhf.c \
ef_rem_pio2.c \
erf_lgamma.c \
fmodf.c \
kf_cos.c \
kf_rem_pio2.c \
kf_sin.c \
kf_tan.c \
log1pf.c \
nearbyintf.c \
roundf.c \
sf_cos.c \
sf_erf.c \
sf_frexp.c \
sf_ldexp.c \
sf_modf.c \
sf_sin.c \
sf_tan.c \
wf_lgamma.c \
wf_tgamma.c \
)
ifeq ($(SUPPORTS_HARDWARE_FP_SINGLE),1)
LIBM_SRC_C += lib/libm/thumb_vfp_sqrtf.c
else
LIBM_SRC_C += lib/libm/ef_sqrt.c
endif
endif
LIBM_O = $(addprefix $(BUILD)/, $(LIBM_SRC_C:.c=.o))
# Too many warnings in libm_dbl, disable for now.
ifeq ($(MICROPY_FLOAT_IMPL),double)
$(LIBM_O): CFLAGS := $(filter-out -Wdouble-promotion -Wfloat-conversion, $(CFLAGS))
endif
EXTMOD_SRC_C += $(addprefix extmod/,\
modonewire.c \
)
DRIVERS_SRC_C += $(addprefix drivers/,\
bus/softspi.c \
bus/softqspi.c \
memory/spiflash.c \
dht/dht.c \
)
SRC_C += \
boardctrl.c \
main.c \
ra_it.c \
mphalport.c \
mpthreadport.c \
irq.c \
pendsv.c \
systick.c \
softtimer.c \
powerctrl.c \
powerctrlboot.c \
pybthread.c \
factoryreset.c \
timer.c \
led.c \
uart.c \
gccollect.c \
help.c \
machine_adc.c \
machine_i2c.c \
machine_spi.c \
machine_timer.c \
machine_uart.c \
machine_pin.c \
machine_rtc.c \
modmachine.c \
modutime.c \
extint.c \
usrsw.c \
flash.c \
flashbdev.c \
storage.c \
fatfs_port.c \
$(BOARD_DIR)/src/hal_entry.c \
$(wildcard $(BOARD_DIR)/*.c)
SRC_C += $(addprefix $(BOARD_DIR)/ra_gen/,\
common_data.c \
hal_data.c \
main.c \
pin_data.c \
vector_data.c \
)
SRC_CXX += \
$(SRC_MOD_CXX)
SRC_O += \
$(STARTUP_FILE) \
$(SYSTEM_FILE)
SRC_O += \
shared/runtime/gchelper_m3.o
HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/board/$(BOARD_LOW)/,\
board_init.c \
board_leds.c \
)
HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/bsp/mcu/all/,\
bsp_clocks.c \
bsp_common.c \
bsp_delay.c \
bsp_group_irq.c \
bsp_guard.c \
bsp_io.c \
bsp_irq.c \
bsp_register_protection.c \
bsp_rom_registers.c \
bsp_sbrk.c \
bsp_security.c \
)
HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/,\
r_ioport/r_ioport.c \
)
ifeq ($(USE_FSP_LPM), 1)
CFLAGS += -DUSE_FSP_LPM
HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_lpm/r_lpm.c
endif
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1))
ifeq ($(USE_FSP_FLASH), 1)
CFLAGS += -DUSE_FSP_FLASH
HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_lp/r_flash_lp.c
endif
endif
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1 RA6M2))
ifeq ($(USE_FSP_FLASH), 1)
CFLAGS += -DUSE_FSP_FLASH
HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_hp/r_flash_hp.c
endif
endif
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2))
HAL_SRC_C += $(addprefix ra/,\
ra_adc.c \
ra_flash.c \
ra_gpio.c \
ra_i2c.c \
ra_icu.c \
ra_init.c \
ra_int.c \
ra_rtc.c \
ra_sci.c \
ra_spi.c \
ra_timer.c \
ra_utils.c \
)
endif
OBJ += $(PY_O)
OBJ += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o))
OBJ += $(LIBM_O)
OBJ += $(addprefix $(BUILD)/, $(SHARED_SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(EXTMOD_SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(HAL_SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_CXX:.cpp=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_O))
OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
OBJ += $(BUILD)/pins_$(BOARD).o
# This file contains performance critical functions so turn up the optimisation
# level. It doesn't add much to the code size and improves performance a bit.
# Don't use -O3 with this file because gcc tries to optimise memset in terms of itself.
$(BUILD)/shared/libc/string0.o: COPT += -O2
# We put several files into the first 16K section with the ISRs.
# If we compile these using -O0 then it won't fit. So if you really want these
# to be compiled with -O0, then edit boards/common.ld (in the .isr_vector section)
# and comment out the following lines.
$(BUILD)/$(OOFATFS_DIR)/ff.o: COPT += -Os
$(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os
$(PY_BUILD)/formatfloat.o: COPT += -Os
$(PY_BUILD)/parsenum.o: COPT += -Os
$(PY_BUILD)/mpprint.o: COPT += -Os
all: $(TOP)/lib/fsp/README.md $(BUILD)/firmware.hex
# For convenience, automatically fetch required submodules if they don't exist
$(TOP)/lib/fsp/README.md:
$(ECHO) "fsp submodule not found, fetching it now..."
(cd $(TOP) && git submodule update --init lib/fsp)
ifneq ($(FROZEN_MANIFEST)$(FROZEN_DIR),)
# To use frozen source modules, put your .py files in a subdirectory (eg scripts/)
# and then invoke make with FROZEN_DIR=scripts (be sure to build from scratch).
CFLAGS += -DMICROPY_MODULE_FROZEN_STR
endif
ifneq ($(FROZEN_MANIFEST)$(FROZEN_MPY_DIR),)
# To use frozen bytecode, put your .py files in a subdirectory (eg frozen/) and
# then invoke make with FROZEN_MPY_DIR=frozen (be sure to build from scratch).
CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool
CFLAGS += -DMICROPY_MODULE_FROZEN_MPY
endif
define GENERATE_ELF
$(ECHO) "LINK $(1)"
$(Q)$(LD) $(LDFLAGS) -o $(1) $(2) $(LDFLAGS_MOD) $(LIBS)
$(Q)$(SIZE) $(1)
endef
define GENERATE_BIN
$(ECHO) "GEN $(1)"
$(Q)$(OBJCOPY) -O binary $(addprefix -j ,$(3)) $(2) $(1)
endef
define GENERATE_HEX
$(ECHO) "GEN $(1)"
$(Q)$(OBJCOPY) -O ihex $(2) $(1)
endef
.PHONY:
# A board should specify TEXT0_ADDR if to use a different location than the
# default for the firmware memory location. A board can also optionally define
# TEXT1_ADDR to split the firmware into two sections; see below for details.
TEXT0_ADDR ?= 0x00000000
# No TEXT1_ADDR given so put all firmware at TEXT0_ADDR location
TEXT0_SECTIONS ?= .isr_vector .text .data
$(BUILD)/firmware.bin: $(BUILD)/firmware.elf
$(call GENERATE_BIN,$@,$^,$(TEXT0_SECTIONS))
$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
$(call GENERATE_HEX,$@,$^)
$(BUILD)/firmware.elf: $(OBJ)
$(call GENERATE_ELF,$@,$^)
MAKE_PINS = boards/make-pins.py
BOARD_PINS = $(BOARD_DIR)/pins.csv
PREFIX_FILE = boards/ra_pin_prefix.c
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1))
AF_FILE = boards/ra4m1_af.csv
endif
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4W1))
AF_FILE = boards/ra4w1_af.csv
endif
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1))
AF_FILE = boards/ra6m1_af.csv
endif
ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M2))
AF_FILE = boards/ra6m2_af.csv
endif
GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c
GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
GEN_PINS_AD_CONST = $(HEADER_BUILD)/pins_ad_const.h
GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h
#GEN_PINS_AF_DEFS = $(HEADER_BUILD)/pins_af_defs.h
GEN_PINS_AF_PY = $(BUILD)/pins_af.py
FILE2H = $(TOP)/tools/file2h.py
# List of sources for qstr extraction
SRC_QSTR += $(SRC_C) $(SRC_CXX) $(SRC_MOD) $(SHARED_SRC_C) $(EXTMOD_SRC_C)
# Making OBJ use an order-only depenedency on the generated pins.h file
# has the side effect of making the pins.h file before we actually compile
# any of the objects. The normal dependency generation will deal with the
# case when pins.h is modified. But when it doesn't exist, we don't know
# which source files might need it.
$(OBJ): | $(GEN_PINS_HDR)
# With conditional pins, we may need to regenerate qstrdefs.h when config
# options change.
$(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h
# Use a pattern rule here so that make will only call make-pins.py once to make
# both pins_$(BOARD).c and pins.h
.PRECIOUS: $(GEN_PINS_SRC)
$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(HEADER_BUILD)/%_af_defs.h $(BUILD)/%_qstr.h: $(BOARD_DIR)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD)
$(ECHO) "GEN $@"
$(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) --ad-const $(GEN_PINS_AD_CONST) --af-const $(GEN_PINS_AF_CONST) --af-py $(GEN_PINS_AF_PY) > $(GEN_PINS_SRC)
#$(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c
# $(call compile_c)
CMSIS_MCU_HDR = $(CMSIS_DIR)/$(CMSIS_MCU_LOWER).h
include $(TOP)/py/mkrules.mk

103
ports/renesas-ra/RA4M1_hal.h Normal file
View File

@ -0,0 +1,103 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef PORTS_RA_RA4M1_HAL_H_
#define PORTS_RA_RA4M1_HAL_H_
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
// #include "hal_data.h"
#include "bsp_api.h"
#include "common_data.h"
#define SCI_CH 0
#define SCI_BAUD 115200
#define UART_CH SCI_CH
#define UART_TxStr sci_tx_str
#define PCLK 48000000
#define RA_PRI_SYSTICK (0)
#define RA_PRI_UART (1)
#define RA_PRI_SDIO (4)
#define RA_PRI_DMA (5)
#define RA_PRI_FLASH (6)
#define RA_PRI_OTG_FS (6)
#define RA_PRI_OTG_HS (6)
#define RA_PRI_TIM5 (6)
#define RA_PRI_CAN (7)
#define RA_PRI_SPI (8)
#define RA_PRI_I2C (8)
#define RA_PRI_TIMX (13)
#define RA_PRI_EXTINT (14)
#define RA_PRI_PENDSV (15)
#define RA_PRI_RTC_WKUP (15)
#include "ra_config.h"
#include "ra_adc.h"
#include "ra_flash.h"
#include "ra_gpio.h"
#include "ra_i2c.h"
#include "ra_icu.h"
#include "ra_init.h"
#include "ra_int.h"
#include "ra_rtc.h"
#include "ra_sci.h"
#include "ra_spi.h"
#include "ra_timer.h"
#include "ra_utils.h"
typedef enum {
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
#define __IO volatile
#if defined(USE_DBG_PRINT)
#if !defined(DEBUG_CH)
#define DEBUG_CH SCI_CH
#endif
#if (DEBUG_CH == 0)
#define DEBUG_TX_PIN P411
#define DEBUG_RX_PIN P410
#endif
#if (DEBUG_CH == 1)
#define DEBUG_TX_PIN P401
#define DEBUG_RX_PIN P402
#endif
#if (DEBUG_CH == 9)
#define DEBUG_TX_PIN P203
#define DEBUG_RX_PIN P202
#endif
#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s)
#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c)
#else
#define DEBUG_TXSTR(s)
#define DEBUG_TXCH(c)
#endif
#endif /* PORTS_RA_RA4M1_HAL_H_ */

103
ports/renesas-ra/RA4W1_hal.h Normal file
View File

@ -0,0 +1,103 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef PORTS_RA_RA4W1_HAL_H_
#define PORTS_RA_RA4W1_HAL_H_
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
// #include "hal_data.h"
#include "bsp_api.h"
#include "common_data.h"
#define SCI_CH 0
#define SCI_BAUD 115200
#define UART_CH SCI_CH
#define UART_TxStr sci_tx_str
#define PCLK 48000000
#define RA_PRI_SYSTICK (0)
#define RA_PRI_UART (1)
#define RA_PRI_SDIO (4)
#define RA_PRI_DMA (5)
#define RA_PRI_FLASH (6)
#define RA_PRI_OTG_FS (6)
#define RA_PRI_OTG_HS (6)
#define RA_PRI_TIM5 (6)
#define RA_PRI_CAN (7)
#define RA_PRI_SPI (8)
#define RA_PRI_I2C (8)
#define RA_PRI_TIMX (13)
#define RA_PRI_EXTINT (14)
#define RA_PRI_PENDSV (15)
#define RA_PRI_RTC_WKUP (15)
#include "ra_config.h"
#include "ra_adc.h"
#include "ra_flash.h"
#include "ra_gpio.h"
#include "ra_i2c.h"
#include "ra_icu.h"
#include "ra_init.h"
#include "ra_int.h"
#include "ra_rtc.h"
#include "ra_sci.h"
#include "ra_spi.h"
#include "ra_timer.h"
#include "ra_utils.h"
typedef enum {
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
#define __IO volatile
#if defined(USE_DBG_PRINT)
#if !defined(DEBUG_CH)
#define DEBUG_CH SCI_CH
#endif
#if (DEBUG_CH == 0)
#define DEBUG_TX_PIN P411
#define DEBUG_RX_PIN P410
#endif
#if (DEBUG_CH == 1)
#define DEBUG_TX_PIN P401
#define DEBUG_RX_PIN P402
#endif
#if (DEBUG_CH == 9)
#define DEBUG_TX_PIN P203
#define DEBUG_RX_PIN P202
#endif
#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s)
#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c)
#else
#define DEBUG_TXSTR(s)
#define DEBUG_TXCH(c)
#endif
#endif /* PORTS_RA_RA4W1_HAL_H_ */

103
ports/renesas-ra/RA6M1_hal.h Normal file
View File

@ -0,0 +1,103 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef PORTS_RA_RA6M1_HAL_H_
#define PORTS_RA_RA6M1_HAL_H_
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
// #include "hal_data.h"
#include "bsp_api.h"
#include "common_data.h"
#define SCI_CH 0
#define SCI_BAUD 115200
#define UART_CH SCI_CH
#define UART_TxStr sci_tx_str
#define PCLK 120000000
#define RA_PRI_SYSTICK (0)
#define RA_PRI_UART (1)
#define RA_PRI_SDIO (4)
#define RA_PRI_DMA (5)
#define RA_PRI_FLASH (6)
#define RA_PRI_OTG_FS (6)
#define RA_PRI_OTG_HS (6)
#define RA_PRI_TIM5 (6)
#define RA_PRI_CAN (7)
#define RA_PRI_SPI (8)
#define RA_PRI_I2C (8)
#define RA_PRI_TIMX (13)
#define RA_PRI_EXTINT (14)
#define RA_PRI_PENDSV (15)
#define RA_PRI_RTC_WKUP (15)
#include "ra_config.h"
#include "ra_adc.h"
#include "ra_flash.h"
#include "ra_gpio.h"
#include "ra_i2c.h"
#include "ra_icu.h"
#include "ra_init.h"
#include "ra_int.h"
#include "ra_rtc.h"
#include "ra_sci.h"
#include "ra_spi.h"
#include "ra_timer.h"
#include "ra_utils.h"
typedef enum {
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
#define __IO volatile
#if defined(USE_DBG_PRINT)
#if !defined(DEBUG_CH)
#define DEBUG_CH SCI_CH
#endif
#if (DEBUG_CH == 0)
#define DEBUG_TX_PIN P411
#define DEBUG_RX_PIN P410
#endif
#if (DEBUG_CH == 1)
#define DEBUG_TX_PIN P401
#define DEBUG_RX_PIN P402
#endif
#if (DEBUG_CH == 9)
#define DEBUG_TX_PIN P203
#define DEBUG_RX_PIN P202
#endif
#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s)
#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c)
#else
#define DEBUG_TXSTR(s)
#define DEBUG_TXCH(c)
#endif
#endif /* PORTS_RA_RA6M1_HAL_H_ */

103
ports/renesas-ra/RA6M2_hal.h Normal file
View File

@ -0,0 +1,103 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef PORTS_RA_RA6M2_HAL_H_
#define PORTS_RA_RA6M2_HAL_H_
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
// #include "hal_data.h"
#include "bsp_api.h"
#include "common_data.h"
#define SCI_CH 0
#define SCI_BAUD 115200
#define UART_CH SCI_CH
#define UART_TxStr sci_tx_str
#define PCLK 120000000
#define RA_PRI_SYSTICK (0)
#define RA_PRI_UART (1)
#define RA_PRI_SDIO (4)
#define RA_PRI_DMA (5)
#define RA_PRI_FLASH (6)
#define RA_PRI_OTG_FS (6)
#define RA_PRI_OTG_HS (6)
#define RA_PRI_TIM5 (6)
#define RA_PRI_CAN (7)
#define RA_PRI_SPI (8)
#define RA_PRI_I2C (8)
#define RA_PRI_TIMX (13)
#define RA_PRI_EXTINT (14)
#define RA_PRI_PENDSV (15)
#define RA_PRI_RTC_WKUP (15)
#include "ra_config.h"
#include "ra_adc.h"
#include "ra_flash.h"
#include "ra_gpio.h"
#include "ra_i2c.h"
#include "ra_icu.h"
#include "ra_init.h"
#include "ra_int.h"
#include "ra_rtc.h"
#include "ra_sci.h"
#include "ra_spi.h"
#include "ra_timer.h"
#include "ra_utils.h"
typedef enum {
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
#define __IO volatile
#if defined(USE_DBG_PRINT)
#if !defined(DEBUG_CH)
#define DEBUG_CH SCI_CH
#endif
#if (DEBUG_CH == 0)
#define DEBUG_TX_PIN P411
#define DEBUG_RX_PIN P410
#endif
#if (DEBUG_CH == 1)
#define DEBUG_TX_PIN P401
#define DEBUG_RX_PIN P402
#endif
#if (DEBUG_CH == 9)
#define DEBUG_TX_PIN P203
#define DEBUG_RX_PIN P202
#endif
#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s)
#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c)
#else
#define DEBUG_TXSTR(s)
#define DEBUG_TXCH(c)
#endif
#endif /* PORTS_RA_RA6M2_HAL_H_ */

81
ports/renesas-ra/README.md Normal file
View File

@ -0,0 +1,81 @@
# The Renesas RA port
This is a port of MicroPython to the Renesas RA family of microcontrollers.
Currently supported features are:
- Filesystem on the internal flash using FatFs.
- `utime` module with sleep, time, and ticks functions.
- `uos` module with VFS support.
- `machine` module with the following classes: `Pin`, `ADC`, `I2C`, `SPI`,
`SoftI2C`, `SoftSPI`, `UART`, `RTC`
- sdcard driver if frozen driver is installed.
Currently supported board product names are:
- EK-RA6M2
- RA4M1 CLICKER
- EK-RA6M1
- EK-RA4M1
- EK-RA4W1
Please refer to the quick reference of `renesas-ra` port for more
information about the boards.
## Build instructions
* MicroPython cross-compier
The MicroPython cross-compiler must be built first, which will be
used to pre-compile (freeze) built-in Python code. THis cross-compiler
is built and run on the host machine, using:
$ make -C mpy-cross
This command should be executed from the root directory of this repository.
All other commands below should be executed from the ports/renesas-ra/ directory.
* Arm compiler
An `Arm compiler` is required for the build, along with the associated binary
utilities. The default compiler is `arm-none-eabi-gcc`, which is available for
Arch Linux and Windows hosts via https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads.
The compiler can be changed using the `CROSS_COMPILE` variable
when invoking `make`.
* Obtain submodules
First the submodules must be obtained using:
$ make submodules
* Build binary image `.hex`
Then to build for a given board subdirectory name, run:
$ make BOARD=RA6M2_EK clean
$ make BOARD=RA6M2_EK
The default board subdirectory name is RA6M2_EK (which is for EK-RA6M2 board)
but any of the names of the subdirectories in the `boards/` directory can be
passed as the argument to `BOARD=`; for example `RA4M1_CLICKER`, `RA4M1_EK`,
`RA4W1_EK` and `RA6M1_EK`.
The above command should produce binary images `firmware.hex` in the
build-RA6M2_EK/` subdirectory (or the equivalent directory for the board specified).
## Supported/Unsupprted funtions
Please refer to the `renesas-ra` quick reference.
## Known issues
### all boards
* machine.lightsleep(time_ms) and machine.deepsleep(time_ms) raise uncaught exceptions.
>>> machine.deepsleep(1000)
>>> Uncaught exception in ExtInt interrupt handler line 16
TypeError:
### RA4M1-CLICKER
* mpremote: mount command is not available due to limited memory resources.
### EK-RA4M1
* mpremote: mount command is not available due to limited memory resources.
### EK-RA4W1
* mpremote: "Execution: timeout waiting for remote" error happens when importing a file on /remote.

171
ports/renesas-ra/boardctrl.c Normal file
View File

@ -0,0 +1,171 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2013-2020 Damien P. George
* Copyright (c) 2022 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/runtime.h"
#include "py/mphal.h"
#include "shared/runtime/pyexec.h"
#include "boardctrl.h"
#include "led.h"
#include "usrsw.h"
STATIC void flash_error(int n) {
for (int i = 0; i < n; i++) {
led_state(RA_LED1, 1);
mp_hal_delay_ms(250);
led_state(RA_LED1, 0);
mp_hal_delay_ms(250);
}
}
#if !MICROPY_HW_USES_BOOTLOADER
STATIC uint update_reset_mode(uint reset_mode) {
#if MICROPY_HW_HAS_SWITCH
bool press_status;
if (switch_get()) {
press_status = true;
mp_printf(&mp_plat_print, "\nEntering select boot mode\n");
mp_printf(&mp_plat_print, "Normal: release switch after LED1 flashes 4 times or more.\n");
mp_printf(&mp_plat_print, "Safe: release switch after LED1 flashes 2 times.\n");
mp_printf(&mp_plat_print, "Factory filesystem: release switch after LED1 flashes 3 times.\n");
// For boards with only a single LED, we'll flash that LED the
// appropriate number of times, with a pause between each one
for (uint i = 0; i < 100; i++) {
led_state(RA_LED1, 1);
mp_hal_delay_ms(1000);
led_state(RA_LED1, 0);
for (uint i = 0; i < 50; i++) {
mp_hal_delay_ms(20);
if (!switch_get()) {
press_status = false;
break;
}
}
if (press_status == false) {
break;
}
++reset_mode;
}
if (reset_mode > BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM) {
reset_mode = BOARDCTRL_RESET_MODE_NORMAL;
}
#if 0 // if selected mode is displayed, LED1 flash is unnecessary.
// Flash the selected reset mode twice.
// We'll flash LED selected number of times, and wait for 2 secs, then flash again:
// BOARDCTRL_RESET_MODE_NORMAL = 1,
// BOARDCTRL_RESET_MODE_SAFE_MODE = 2,
// BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM = 3,
mp_hal_delay_ms(1000);
for (uint i = 0; i < 2; i++) {
for (uint j = 0; j < reset_mode; j++) {
led_state(RA_LED1, 1);
mp_hal_delay_ms(1000);
led_state(RA_LED1, 0);
mp_hal_delay_ms(1000);
}
mp_hal_delay_ms(2000);
}
#endif
if (reset_mode == BOARDCTRL_RESET_MODE_SAFE_MODE) {
mp_printf(&mp_plat_print, "\nBoot with safe mode\n");
} else if (reset_mode == BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM) {
mp_printf(&mp_plat_print, "\nBoot with factory filesystem mode\n");
} else {
mp_printf(&mp_plat_print, "\nBoot with Normal mode\n");
}
}
#endif
return reset_mode;
}
#endif
void boardctrl_before_soft_reset_loop(boardctrl_state_t *state) {
#if !MICROPY_HW_USES_BOOTLOADER
// Update the reset_mode via the default
// method which uses the board switch/button and LEDs.
state->reset_mode = update_reset_mode(BOARDCTRL_RESET_MODE_NORMAL);
#endif
}
void boardctrl_top_soft_reset_loop(boardctrl_state_t *state) {
}
int boardctrl_run_boot_py(boardctrl_state_t *state) {
bool run_boot_py = state->reset_mode != BOARDCTRL_RESET_MODE_SAFE_MODE;
if (run_boot_py) {
// Run boot.py, if it exists.
const char *boot_py = "boot.py";
int ret = pyexec_file_if_exists(boot_py);
// Take action based on the execution result.
if (ret & PYEXEC_FORCED_EXIT) {
return BOARDCTRL_GOTO_SOFT_RESET_EXIT;
}
if (!ret) {
// There was an error, prevent main.py from running and flash LEDs.
state->reset_mode = BOARDCTRL_RESET_MODE_SAFE_MODE;
flash_error(4);
}
}
return BOARDCTRL_CONTINUE;
}
int boardctrl_run_main_py(boardctrl_state_t *state) {
bool run_main_py = state->reset_mode != BOARDCTRL_RESET_MODE_SAFE_MODE
&& pyexec_mode_kind == PYEXEC_MODE_FRIENDLY_REPL;
if (run_main_py) {
// Run main.py (or what it was configured to be), if it exists.
const char *main_py;
if (MP_STATE_PORT(pyb_config_main) == MP_OBJ_NULL) {
main_py = "main.py";
} else {
main_py = mp_obj_str_get_str(MP_STATE_PORT(pyb_config_main));
}
int ret = pyexec_file_if_exists(main_py);
// Take action based on the execution result.
if (ret & PYEXEC_FORCED_EXIT) {
return BOARDCTRL_GOTO_SOFT_RESET_EXIT;
}
if (!ret) {
flash_error(3);
}
}
return BOARDCTRL_CONTINUE;
}
void boardctrl_start_soft_reset(boardctrl_state_t *state) {
state->log_soft_reset = true;
}
void boardctrl_end_soft_reset(boardctrl_state_t *state) {
// Set reset_mode to normal boot.
state->reset_mode = BOARDCTRL_RESET_MODE_NORMAL;
}

93
ports/renesas-ra/boardctrl.h Normal file
View File

@ -0,0 +1,93 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_RENESAS_RA_BOARDCTRL_H
#define MICROPY_INCLUDED_RENESAS_RA_BOARDCTRL_H
#include "py/mpconfig.h"
// Additional entries for use with pendsv_schedule_dispatch.
#ifndef MICROPY_BOARD_PENDSV_ENTRIES
#define MICROPY_BOARD_PENDSV_ENTRIES
#endif
#ifndef MICROPY_BOARD_STARTUP
#define MICROPY_BOARD_STARTUP powerctrl_check_enter_bootloader
#endif
#ifndef MICROPY_BOARD_EARLY_INIT
#define MICROPY_BOARD_EARLY_INIT()
#endif
#ifndef MICROPY_BOARD_BEFORE_SOFT_RESET_LOOP
#define MICROPY_BOARD_BEFORE_SOFT_RESET_LOOP boardctrl_before_soft_reset_loop
#endif
#ifndef MICROPY_BOARD_TOP_SOFT_RESET_LOOP
#define MICROPY_BOARD_TOP_SOFT_RESET_LOOP boardctrl_top_soft_reset_loop
#endif
#ifndef MICROPY_BOARD_RUN_BOOT_PY
#define MICROPY_BOARD_RUN_BOOT_PY boardctrl_run_boot_py
#endif
#ifndef MICROPY_BOARD_RUN_MAIN_PY
#define MICROPY_BOARD_RUN_MAIN_PY boardctrl_run_main_py
#endif
#ifndef MICROPY_BOARD_START_SOFT_RESET
#define MICROPY_BOARD_START_SOFT_RESET boardctrl_start_soft_reset
#endif
#ifndef MICROPY_BOARD_END_SOFT_RESET
#define MICROPY_BOARD_END_SOFT_RESET boardctrl_end_soft_reset
#endif
// Constants to return from boardctrl_run_boot_py, boardctrl_run_main_py.
enum {
BOARDCTRL_CONTINUE,
BOARDCTRL_GOTO_SOFT_RESET_EXIT,
};
// Constants for boardctrl_state_t.reset_mode.
enum {
BOARDCTRL_RESET_MODE_NORMAL = 1,
BOARDCTRL_RESET_MODE_SAFE_MODE = 2,
BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM = 3,
};
typedef struct _boardctrl_state_t {
uint8_t reset_mode;
bool log_soft_reset;
} boardctrl_state_t;
void boardctrl_before_soft_reset_loop(boardctrl_state_t *state);
void boardctrl_top_soft_reset_loop(boardctrl_state_t *state);
int boardctrl_run_boot_py(boardctrl_state_t *state);
int boardctrl_run_main_py(boardctrl_state_t *state);
void boardctrl_start_soft_reset(boardctrl_state_t *state);
void boardctrl_end_soft_reset(boardctrl_state_t *state);
#endif // MICROPY_INCLUDED_RENESAS_RA_BOARDCTRL_H

22
ports/renesas-ra/boards/RA4M1_CLICKER/board.json Normal file
View File

@ -0,0 +1,22 @@
{
"deploy": [
"../deploy.md"
],
"docs": "",
"features": [
"UART",
"SPI",
"I2C",
"ADC"
],
"id": "RA4M1-CLICKER",
"images": [
"ra4m1_clicker_board.jpg",
"ra4m1_clicker_pins.jpg"
],
"mcu": "RA4M1",
"product": "Mikroe RA4M1 Clicker",
"thumbnail": "",
"url": "https://www.mikroe.com/ra4m1-clicker",
"vendor": "MikroElektronika"
}

2
ports/renesas-ra/boards/RA4M1_CLICKER/manifest.py Normal file
View File

@ -0,0 +1,2 @@
# We do not want to include default frozen modules,
freeze("$(MPY_DIR)/drivers/sdcard", "sdcard.py")

59
ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.h Normal file
View File

@ -0,0 +1,59 @@
// MCU config
#define MICROPY_HW_BOARD_NAME "RA4M1_CLICKER"
#define MICROPY_HW_MCU_NAME "RA4M1"
#define MICROPY_HW_MCU_SYSCLK 48000000
#define MICROPY_HW_MCU_PCLK 48000000
// module config
#define MICROPY_EMIT_THUMB (0)
#define MICROPY_EMIT_INLINE_THUMB (0)
#define MICROPY_PY_BUILTINS_COMPLEX (0)
#define MICROPY_PY_GENERATOR_PEND_THROW (0)
#define MICROPY_PY_MATH (0)
#define MICROPY_PY_UHEAPQ (0)
#define MICROPY_PY_UTIMEQ (0)
#define MICROPY_PY_THREAD (0)
// peripheral config
#define MICROPY_HW_ENABLE_RTC (1)
#define MICROPY_HW_RTC_SOURCE (0) // 0: subclock, 1:LOCO
#define MICROPY_HW_ENABLE_ADC (1)
#define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
// board config
// UART
#define MICROPY_HW_UART0_TX (pin_P411) // MBTX0
#define MICROPY_HW_UART0_RX (pin_P410) // MBRX0
// #define MICROPY_HW_UART0_CTS (pin_P103) // Disable (Conflict with SSLA0)
#define MICROPY_HW_UART1_TX (pin_P401) // REPL
#define MICROPY_HW_UART1_RX (pin_P402) // REPL
#define MICROPY_HW_UART_REPL HW_UART_1
#define MICROPY_HW_UART_REPL_BAUD 115200
// I2C
// #define MICROPY_HW_I2C0_SCL (pin_P400) // Disable (Conflict with REPL)
// #define MICROPY_HW_I2C0_SDA (pin_P401) // Disable (Conflict with REPL)
#define MICROPY_HW_I2C1_SCL (pin_P205)
#define MICROPY_HW_I2C1_SDA (pin_P206)
// SPI
#define MICROPY_HW_SPI0_SSL (pin_P103)
#define MICROPY_HW_SPI0_RSPCK (pin_P102)
#define MICROPY_HW_SPI0_MISO (pin_P100)
#define MICROPY_HW_SPI0_MOSI (pin_P101)
// Switch
#define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_USRSW_PIN (pin_P304)
#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING)
#define MICROPY_HW_USRSW_PRESSED (0)
// LEDs
#define MICROPY_HW_LED1 (pin_P409)
#define MICROPY_HW_LED2 (pin_P408)
#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin)
#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin)
#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin)

9
ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk Normal file
View File

@ -0,0 +1,9 @@
CMSIS_MCU = RA4M1
MCU_SERIES = m4
LD_FILES = boards/RA4M1_CLICKER/ra4m1_clicker.ld
# MicroPython settings
MICROPY_VFS_FAT = 1
# Don't include default frozen modules because MCU is tight on flash space
FROZEN_MANIFEST ?= boards/RA4M1_CLICKER/manifest.py

65
ports/renesas-ra/boards/RA4M1_CLICKER/pins.csv Normal file
View File

@ -0,0 +1,65 @@
P000,P000
P012,P012
P013,P013
P014,P014
P100,P100
P101,P101
P102,P102
P103,P103
P107,P107
P108,P108
P109,P109
P110,P110
P112,P112
P201,P201
P205,P205
P206,P206
P300,P300
P301,P301
P302,P302
P304,P304
P400,P400
P401,P401
P402,P402
P407,P407
P408,P408
P409,P409
P410,P410
P411,P411
P501,P501
P502,P502
P914,P914
P915,P915
MBAN,P000
GPIOHD10,P012
GPIOHD9,P013
GPIOHD8,P014
MBMISO,P100
MBMOSI,P101
MBSCK,P102
MBSSL,P103
MBPWM,P107
SWDIO,P108
SWO,P109
TDI,P110
TSCAP,P112
MD,P201
MBSCLI,P205
MBSDA1,P206
SWCLK,P300
SW2,P301
MBINT,P302
SW1,P304
GPIOHD5,P400
GPIOHD4,P401
GPIOHD3,P402
MBRST,P407
LED2,P408
LED1,P409
MBRX0,P410
MBTX0,P411
GPIOHD7,P501
GPIOHD6,P502
USBDP,P914
USBDM,P915
1 P000 P000
2 P012 P012
3 P013 P013
4 P014 P014
5 P100 P100
6 P101 P101
7 P102 P102
8 P103 P103
9 P107 P107
10 P108 P108
11 P109 P109
12 P110 P110
13 P112 P112
14 P201 P201
15 P205 P205
16 P206 P206
17 P300 P300
18 P301 P301
19 P302 P302
20 P304 P304
21 P400 P400
22 P401 P401
23 P402 P402
24 P407 P407
25 P408 P408
26 P409 P409
27 P410 P410
28 P411 P411
29 P501 P501
30 P502 P502
31 P914 P914
32 P915 P915
33 MBAN P000
34 GPIOHD10 P012
35 GPIOHD9 P013
36 GPIOHD8 P014
37 MBMISO P100
38 MBMOSI P101
39 MBSCK P102
40 MBSSL P103
41 MBPWM P107
42 SWDIO P108
43 SWO P109
44 TDI P110
45 TSCAP P112
46 MD P201
47 MBSCLI P205
48 MBSDA1 P206
49 SWCLK P300
50 SW2 P301
51 MBINT P302
52 SW1 P304
53 GPIOHD5 P400
54 GPIOHD4 P401
55 GPIOHD3 P402
56 MBRST P407
57 LED2 P408
58 LED1 P409
59 MBRX0 P410
60 MBTX0 P411
61 GPIOHD7 P501
62 GPIOHD6 P502
63 USBDP P914
64 USBDM P915

298
ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker.ld Normal file
View File

@ -0,0 +1,298 @@
/*
Linker File for RA4M1 MCU
*/
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256KB */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* 32KB */
DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */
ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */
}
/* Library configurations */
/*GROUP(libgcc.a libc.a libm.a libnosys.a) */
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
_stext = .;
__ROM_Start = .;
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
* space because ROM registers are at address 0x400 and there is very little space
* in between. */
KEEP(*(.fixed_vectors*))
KEEP(*(.application_vectors*))
__Vectors_End = .;
__end__ = .;
/* ROM Registers start at address 0x00000400 */
. = __ROM_Start + 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = __ROM_Start + 0x500;
*(.text*)
KEEP(*(.version))
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
__usb_dev_descriptor_start_fs = .;
KEEP(*(.usb_device_desc_fs*))
__usb_cfg_descriptor_start_fs = .;
KEEP(*(.usb_config_desc_fs*))
__usb_interface_descriptor_start_fs = .;
KEEP(*(.usb_interface_desc_fs*))
__usb_descriptor_end_fs = .;
__usb_dev_descriptor_start_hs = .;
KEEP(*(.usb_device_desc_hs*))
__usb_cfg_descriptor_start_hs = .;
KEEP(*(.usb_config_desc_hs*))
__usb_interface_descriptor_start_hs = .;
KEEP(*(.usb_interface_desc_hs*))
__usb_descriptor_end_hs = .;
KEEP(*(.eh_frame*))
__ROM_End = .;
_etext = .;
} > FLASH = 0xFF
__Vectors_Size = __Vectors_End - __Vectors;
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
.fsp_dtc_vector_table (NOLOAD) :
{
. = ORIGIN(RAM);
*(.fsp_dtc_vector_table)
} > RAM
/* Initialized data section. */
.data :
{
_sidata = .;
_sdata = .;
__data_start__ = .;
*(vtable)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM AT > FLASH
.noinit (NOLOAD):
{
. = ALIGN(4);
__noinit_start = .;
KEEP(*(.noinit*))
__noinit_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (NOLOAD):
{
. = ALIGN(8);
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* Stacks are stored in this section. */
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
__StackLimit = .;
/* Main stack */
KEEP(*(.stack))
__StackTop = .;
/* Thread stacks */
KEEP(*(.stack*))
__StackTopAll = .;
_estack = .;
} > RAM
PROVIDE(__stack = __StackTopAll);
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
at run time for things such as ThreadX memory pool allocations. */
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
/* Data flash. */
.data_flash :
{
__Data_Flash_Start = .;
KEEP(*(.data_flash*))
__Data_Flash_End = .;
} > DATA_FLASH
.id_code :
{
__ID_Code_Start = .;
KEEP(*(.id_code*))
__ID_Code_End = .;
} > ID_CODE
}
/* produce a link error if there is not this amount of RAM for these sections */
/* _minimum_stack_size = 2K; */
/* _minimum_heap_size = 16K; */
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = __HeapBase; /* heap starts just after statically allocated memory */
_heap_end = __HeapLimit; /* tunable */

30
ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker_conf.h Normal file
View File

@ -0,0 +1,30 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef RA4M1_CLICKER_CONF_H
#define RA4M1_CLICKER_CONF_H
#define DEBUG_CH 0
#endif /* RA4M1_CLICKER_CONF_H */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
void bsp_init(void *p_args);
#endif /* BOARD_CFG_H_ */

49
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h Normal file
View File

@ -0,0 +1,49 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
#ifndef BSP_CFG_RTOS
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (2)
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (1)
#else
#define BSP_CFG_RTOS (0)
#endif
#endif
#undef RA_NOT_DEFINED
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
#define BSP_CFG_HEAP_BYTES (0x4980)
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
#define BSP_CFG_ASSERT (0)
#define BSP_CFG_ERROR_LOG (0)
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#endif /* BSP_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_CFG_H_
#define BSP_MCU_DEVICE_CFG_H_
#define BSP_CFG_MCU_PART_SERIES (4)
#endif /* BSP_MCU_DEVICE_CFG_H_ */

10
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h Normal file
View File

@ -0,0 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA4M1AB3CFM
#define BSP_ROM_SIZE_BYTES (262144)
#define BSP_RAM_SIZE_BYTES (32768)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
#define BSP_PACKAGE_LQFP
#define BSP_PACKAGE_PINS (64)
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

74
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h Normal file
View File

@ -0,0 +1,74 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
#define BSP_MCU_GROUP_RA4M1 (1)
#define BSP_LOCO_HZ (32768)
#define BSP_MOCO_HZ (8000000)
#define BSP_SUB_CLOCK_HZ (32768)
#if BSP_CFG_HOCO_FREQUENCY == 0
#define BSP_HOCO_HZ (24000000)
#elif BSP_CFG_HOCO_FREQUENCY == 2
#define BSP_HOCO_HZ (32000000)
#elif BSP_CFG_HOCO_FREQUENCY == 4
#define BSP_HOCO_HZ (48000000)
#elif BSP_CFG_HOCO_FREQUENCY == 5
#define BSP_HOCO_HZ (64000000)
#else
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
#define OFS_SEQ5 (1 << 28) | (1 << 30)
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
/*
ID Code
Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
*/
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
#else
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h Normal file
View File

@ -0,0 +1,6 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_LP_CFG_H_
#define R_FLASH_LP_CFG_H_
#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#endif /* R_FLASH_LP_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#endif /* R_IIC_MASTER_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_IOPORT_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h Normal file
View File

@ -0,0 +1,8 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

352
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/R7FA4M1AB3CFM.csv Normal file
View File

@ -0,0 +1,352 @@
"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities"
"AVCC0","56","ADC_AVCC0","","","","","",""
"AVSS0","57","ADC_AVSS0","","","","","",""
"P000","64","","","","Disabled","","","ADC0: AN00
CTSU0: TS21
IRQ0: IRQ06
OPAMP0: AMP+"
"P001","63","","","","Disabled","","","ADC0: AN01
CTSU0: TS22
IRQ0: IRQ07
OPAMP0: AMP-"
"P002","62","","","","Disabled","","","ADC0: AN02
IRQ0: IRQ02
OPAMP0: AMPO"
"P003","61","","","","Disabled","","","ADC0: AN03
OPAMP1: AMPO"
"P004","60","","","","Disabled","","","ADC0: AN04
IRQ0: IRQ03
OPAMP2: AMPO"
"P010","59","","","","Disabled","","","ADC: VREFH0
ADC0: AN05
CTSU0: TS30
OPAMP2: AMP-"
"P011","58","","","","Disabled","","","ADC: VREFL0
ADC0: AN06
CTSU0: TS31
IRQ0: IRQ15
OPAMP2: AMP+"
"P012","55","","","","Disabled","","","ADC: VREFH
ADC0: AN07
OPAMP1: AMP-"
"P013","54","","","","Disabled","","","ADC: VREFL
ADC0: AN08
OPAMP1: AMP+"
"P014","53","","","","Disabled","","","ADC0: AN09
DAC120: DA"
"P015","52","","","","Disabled","","","ADC0: AN10
CTSU0: TS28
IRQ0: IRQ07"
"P100","48","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ADC0: AN22
AGT0: AGTIO
CMP0: CMPIN0
GPT5: GTIOCB
IIC1: SCL
IRQ0: IRQ02
KINT0: KRM0
POEG0: GTETRG
SCI0: RXD_MISO
SCI0: SCL
SCI1: SCK
SLCDC0: VL1
SPI0: MISO"
"P101","47","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ADC0: AN21
AGT0: AGTEE
CMP0: CMPREF0
GPT5: GTIOCA
IIC1: SDA
IRQ0: IRQ01
KINT0: KRM1
POEG1: GTETRG
SCI0: SDA
SCI0: TXD_MOSI
SCI1: CTS_RTS_SS
SLCDC0: VL2
SPI0: MOSI"
"P102","46","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG
ADC0: AN20
AGT0: AGTO
CAN0: CRX
CMP0: CMPIN1
GPT2: GTIOCB
KINT0: KRM2
OPS0: GTOWLO
SCI0: SCK
SCI2: SDA
SCI2: TXD_MOSI
SLCDC0: VL3
SPI0: RSPCK"
"P103","45","","","","Disabled","","","ADC0: AN19
CAN0: CTX
CMP0: CMPREF1
GPT2: GTIOCA
KINT0: KRM3
OPS0: GTOWUP
SCI0: CTS_RTS_SS
SLCDC0: VL4
SPI0: SSL0"
"P104","44","","","","Disabled","","","CTSU0: TS13
GPT1: GTIOCB
IRQ0: IRQ01
KINT0: KRM4
POEG1: GTETRG
SCI0: RXD_MISO
SCI0: SCL
SLCDC0: COM0
SPI0: SSL1"
"P105","43","","","","Disabled","","","CTSU0: TS34
GPT1: GTIOCA
IRQ0: IRQ00
KINT0: KRM5
POEG0: GTETRG
SLCDC0: COM1
SPI0: SSL2"
"P106","42","","","","Disabled","","","GPT0: GTIOCB
KINT0: KRM6
SLCDC0: COM2
SPI0: SSL3"
"P107","41","","","","Disabled","","","GPT0: GTIOCA
KINT0: KRM7
SLCDC0: COM3"
"P108","33","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO
DEBUG0: TMS
GPT0: GTIOCB
OPS0: GTOULO
SCI9: CTS_RTS_SS
SPI1: SSL0"
"P109","34","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN0: CTX
CGC0: CLKOUT
CTSU0: TS10
DEBUG0: SWO
DEBUG0: TDO
GPT1: GTIOCA
OPS0: GTOVUP
SCI1: SCK
SCI9: SDA
SCI9: TXD_MOSI
SLCDC0: SEG23
SPI1: MOSI"
"P110","35","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","CAN0: CRX
CMP0: VCOUT
DEBUG0: TDI
GPT1: GTIOCB
IRQ0: IRQ03
OPS0: GTOVLO
SCI2: CTS_RTS_SS
SCI9: RXD_MISO
SCI9: SCL
SLCDC0: SEG24
SPI1: MISO"
"P111","36","","","","Disabled","","","CTSU0: TS12
GPT3: GTIOCA
IRQ0: IRQ04
SCI2: SCK
SCI9: SCK
SLCDC0: CAPH
SPI1: RSPCK"
"P112","37","","","","Disabled","","","CTSU0: TSCAP
GPT3: GTIOCB
SCI1: SCK
SCI2: SDA
SCI2: TXD_MOSI
SLCDC0: CAPL
SPI1: SSL0"
"P113","38","","","","Disabled","","","CTSU0: TS27
GPT2: GTIOCA
SLCDC0: COM4
SLCDC0: SEG00"
"P200","27","","","","Disabled","","","IRQ0: NMI"
"P201","26","","","","Disabled","","",""
"P204","24","","","","Disabled","","","AGT1: AGTIO
CAC0: CACREF
CTSU0: TS00
GPT4: GTIOCB
IIC0: SCL
OPS0: GTIW
SCI0: SCK
SCI9: SCK
SLCDC0: SEG14
SPI1: RSPCK
USBFS0: OVRCURB"
"P205","23","","","","Disabled","","","AGT1: AGTO
CGC0: CLKOUT
CTSU0: TSCAP
GPT4: GTIOCA
IIC1: SCL
IRQ0: IRQ01
OPS0: GTIV
SCI0: SDA
SCI0: TXD_MOSI
SCI9: CTS_RTS_SS
SLCDC0: SEG13
SPI1: SSL0
USBFS0: OVRCURA"
"P206","22","","","","Disabled","","","CTSU0: TS01
IIC1: SDA
IRQ0: IRQ00
OPS0: GTIU
SCI0: RXD_MISO
SCI0: SCL
SLCDC0: SEG12
SPI1: SSL1
USBFS0: VBUSEN"
"P212","10","","","","Disabled","","","AGT1: AGTEE
CGC0: EXTAL
GPT0: GTIOCB
IRQ0: IRQ03
POEG1: GTETRG
SCI1: RXD_MISO
SCI1: SCL"
"P213","9","","","","Disabled","","","CGC0: XTAL
GPT0: GTIOCA
IRQ0: IRQ02
POEG0: GTETRG
SCI1: SDA
SCI1: TXD_MOSI"
"P214","7","","","","Disabled","","","CGC0: XCOUT"
"P215","6","","","","Disabled","","","CGC0: XCIN"
"P300","32","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK
DEBUG0: TCK
GPT0: GTIOCA
OPS0: GTOUUP
SPI1: SSL1"
"P301","31","GPIO","","IRQ6","Input mode","","None","AGT0: AGTIO
CTSU0: TS09
GPT4: GTIOCB
IRQ0: IRQ06
OPS0: GTOULO
SCI2: RXD_MISO
SCI2: SCL
SCI9: CTS_RTS_SS
SLCDC0: COM5
SLCDC0: SEG01
SPI1: SSL2"
"P302","30","GPIO","","IRQ5","Input mode","","None","CTSU0: TS08
GPT4: GTIOCA
IRQ0: IRQ05
OPS0: GTOUUP
SCI2: SDA
SCI2: TXD_MOSI
SLCDC0: COM6
SLCDC0: SEG02
SPI1: SSL3"
"P303","29","","","","Disabled","","","CTSU0: TS02
GPT7: GTIOCB
SLCDC0: COM7
SLCDC0: SEG03"
"P304","28","GPIO","","IRQ9","Input mode","","None","CTSU0: TS11
GPT7: GTIOCA
IRQ0: IRQ09
SLCDC0: SEG20"
"P400","1","","","","Disabled","","","AGT1: AGTIO
CAC0: CACREF
CTSU0: TS20
GPT6: GTIOCA
IIC0: SCL
IRQ0: IRQ00
SCI0: SCK
SCI1: SCK
SLCDC0: SEG04
SSI: AUDIO_CLK"
"P401","2","SCI1_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CAN0: CTX
CTSU0: TS19
GPT6: GTIOCB
IIC0: SDA
IRQ0: IRQ05
POEG0: GTETRG
SCI0: CTS_RTS_SS
SCI1: SDA
SCI1: TXD_MOSI
SLCDC0: SEG05"
"P402","3","SCI1_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO
AGT1: AGTIO
CAN0: CRX
CTSU0: TS18
IRQ0: IRQ04
RTC0: RTCIC0
SCI1: RXD_MISO
SCI1: SCL
SLCDC0: SEG06"
"P407","16","","","","Disabled","","","ADC0: ADTRG
AGT0: AGTIO
CTSU0: TS03
IIC0: SDA
RTC0: RTCOUT
SCI0: CTS_RTS_SS
SLCDC0: SEG11
SPI1: SSL3
USBFS0: VBUS"
"P408","15","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","CTSU0: TS04
GPT5: GTIOCB
IIC0: SCL
IRQ0: IRQ07
OPS0: GTOWLO
SCI1: CTS_RTS_SS
SCI9: RXD_MISO
SCI9: SCL
SLCDC0: SEG10
USBFS0: ID"
"P409","14","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","CTSU0: TS05
GPT5: GTIOCA
IRQ0: IRQ06
OPS0: GTOWUP
SCI9: SDA
SCI9: TXD_MOSI
SLCDC0: SEG09
USBFS0: EXICEN"
"P410","13","SCI0_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOB
CTSU0: TS06
GPT6: GTIOCB
IRQ0: IRQ05
OPS0: GTOVLO
SCI0: RXD_MISO
SCI0: SCL
SLCDC0: SEG08
SPI0: MISO"
"P411","12","SCI0_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOA
CTSU0: TS07
GPT6: GTIOCA
IRQ0: IRQ04
OPS0: GTOVUP
SCI0: SDA
SCI0: TXD_MOSI
SLCDC0: SEG07
SPI0: MOSI"
"P500","49","","","","Disabled","","","ADC0: AN16
AGT0: AGTOA
CMP0: CMPREF1
GPT2: GTIOCA
OPS0: GTIU
SLCDC0: SEG34
USBFS0: VBUSEN"
"P501","50","","","","Disabled","","","ADC0: AN17
AGT0: AGTOB
CMP0: CMPIN1
GPT2: GTIOCB
IRQ0: IRQ11
OPS0: GTIV
SCI1: SDA
SCI1: TXD_MOSI
SLCDC0: SEG35
USBFS0: OVRCURA"
"P502","51","","","","Disabled","","","ADC0: AN18
CMP0: CMPREF0
GPT3: GTIOCB
IRQ0: IRQ12
OPS0: GTIW
SCI1: RXD_MISO
SCI1: SCL
SLCDC0: SEG36
USBFS0: OVRCURB"
"P914","19","","","","Disabled","","","USBFS0: USBDP"
"P915","18","","","","Disabled","","","USBFS0: USBDM"
"RES","25","","","","","","",""
"VBAT","4","","","","","","",""
"VCC","11","","","","","","",""
"VCC","39","","","","","","",""
"VCCUSB","20","USBFS0_VCCUSB","","","","","",""
"VCCUSBLDO","21","USBFS0_VCCUSBLDO","","","","","",""
"VCL","5","","","","","","",""
"VSS","8","","","","","","",""
"VSS","40","","","","","","",""
"VSSUSB","17","USBFS0_VSSUSB","","","","","",""
1 Name Pin Function Drive Capacity IRQ Mode Output type Pull up Port Capabilities
2 AVCC0 56 ADC_AVCC0
3 AVSS0 57 ADC_AVSS0
4 P000 64 Disabled ADC0: AN00 CTSU0: TS21 IRQ0: IRQ06 OPAMP0: AMP+
5 P001 63 Disabled ADC0: AN01 CTSU0: TS22 IRQ0: IRQ07 OPAMP0: AMP-
6 P002 62 Disabled ADC0: AN02 IRQ0: IRQ02 OPAMP0: AMPO
7 P003 61 Disabled ADC0: AN03 OPAMP1: AMPO
8 P004 60 Disabled ADC0: AN04 IRQ0: IRQ03 OPAMP2: AMPO
9 P010 59 Disabled ADC: VREFH0 ADC0: AN05 CTSU0: TS30 OPAMP2: AMP-
10 P011 58 Disabled ADC: VREFL0 ADC0: AN06 CTSU0: TS31 IRQ0: IRQ15 OPAMP2: AMP+
11 P012 55 Disabled ADC: VREFH ADC0: AN07 OPAMP1: AMP-
12 P013 54 Disabled ADC: VREFL ADC0: AN08 OPAMP1: AMP+
13 P014 53 Disabled ADC0: AN09 DAC120: DA
14 P015 52 Disabled ADC0: AN10 CTSU0: TS28 IRQ0: IRQ07
15 P100 48 SPI0_MISO Low None Peripheral mode CMOS None ADC0: AN22 AGT0: AGTIO CMP0: CMPIN0 GPT5: GTIOCB IIC1: SCL IRQ0: IRQ02 KINT0: KRM0 POEG0: GTETRG SCI0: RXD_MISO SCI0: SCL SCI1: SCK SLCDC0: VL1 SPI0: MISO
16 P101 47 SPI0_MOSI Low None Peripheral mode CMOS None ADC0: AN21 AGT0: AGTEE CMP0: CMPREF0 GPT5: GTIOCA IIC1: SDA IRQ0: IRQ01 KINT0: KRM1 POEG1: GTETRG SCI0: SDA SCI0: TXD_MOSI SCI1: CTS_RTS_SS SLCDC0: VL2 SPI0: MOSI
17 P102 46 SPI0_RSPCK Low Peripheral mode CMOS None ADC0: ADTRG ADC0: AN20 AGT0: AGTO CAN0: CRX CMP0: CMPIN1 GPT2: GTIOCB KINT0: KRM2 OPS0: GTOWLO SCI0: SCK SCI2: SDA SCI2: TXD_MOSI SLCDC0: VL3 SPI0: RSPCK
18 P103 45 Disabled ADC0: AN19 CAN0: CTX CMP0: CMPREF1 GPT2: GTIOCA KINT0: KRM3 OPS0: GTOWUP SCI0: CTS_RTS_SS SLCDC0: VL4 SPI0: SSL0
19 P104 44 Disabled CTSU0: TS13 GPT1: GTIOCB IRQ0: IRQ01 KINT0: KRM4 POEG1: GTETRG SCI0: RXD_MISO SCI0: SCL SLCDC0: COM0 SPI0: SSL1
20 P105 43 Disabled CTSU0: TS34 GPT1: GTIOCA IRQ0: IRQ00 KINT0: KRM5 POEG0: GTETRG SLCDC0: COM1 SPI0: SSL2
21 P106 42 Disabled GPT0: GTIOCB KINT0: KRM6 SLCDC0: COM2 SPI0: SSL3
22 P107 41 Disabled GPT0: GTIOCA KINT0: KRM7 SLCDC0: COM3
23 P108 33 DEBUG0_TMS Low Peripheral mode CMOS None DEBUG0: SWDIO DEBUG0: TMS GPT0: GTIOCB OPS0: GTOULO SCI9: CTS_RTS_SS SPI1: SSL0
24 P109 34 DEBUG0_TDO Low Peripheral mode CMOS None CAN0: CTX CGC0: CLKOUT CTSU0: TS10 DEBUG0: SWO DEBUG0: TDO GPT1: GTIOCA OPS0: GTOVUP SCI1: SCK SCI9: SDA SCI9: TXD_MOSI SLCDC0: SEG23 SPI1: MOSI
25 P110 35 DEBUG0_TDI Low None Peripheral mode CMOS None CAN0: CRX CMP0: VCOUT DEBUG0: TDI GPT1: GTIOCB IRQ0: IRQ03 OPS0: GTOVLO SCI2: CTS_RTS_SS SCI9: RXD_MISO SCI9: SCL SLCDC0: SEG24 SPI1: MISO
26 P111 36 Disabled CTSU0: TS12 GPT3: GTIOCA IRQ0: IRQ04 SCI2: SCK SCI9: SCK SLCDC0: CAPH SPI1: RSPCK
27 P112 37 Disabled CTSU0: TSCAP GPT3: GTIOCB SCI1: SCK SCI2: SDA SCI2: TXD_MOSI SLCDC0: CAPL SPI1: SSL0
28 P113 38 Disabled CTSU0: TS27 GPT2: GTIOCA SLCDC0: COM4 SLCDC0: SEG00
29 P200 27 Disabled IRQ0: NMI
30 P201 26 Disabled
31 P204 24 Disabled AGT1: AGTIO CAC0: CACREF CTSU0: TS00 GPT4: GTIOCB IIC0: SCL OPS0: GTIW SCI0: SCK SCI9: SCK SLCDC0: SEG14 SPI1: RSPCK USBFS0: OVRCURB
32 P205 23 Disabled AGT1: AGTO CGC0: CLKOUT CTSU0: TSCAP GPT4: GTIOCA IIC1: SCL IRQ0: IRQ01 OPS0: GTIV SCI0: SDA SCI0: TXD_MOSI SCI9: CTS_RTS_SS SLCDC0: SEG13 SPI1: SSL0 USBFS0: OVRCURA
33 P206 22 Disabled CTSU0: TS01 IIC1: SDA IRQ0: IRQ00 OPS0: GTIU SCI0: RXD_MISO SCI0: SCL SLCDC0: SEG12 SPI1: SSL1 USBFS0: VBUSEN
34 P212 10 Disabled AGT1: AGTEE CGC0: EXTAL GPT0: GTIOCB IRQ0: IRQ03 POEG1: GTETRG SCI1: RXD_MISO SCI1: SCL
35 P213 9 Disabled CGC0: XTAL GPT0: GTIOCA IRQ0: IRQ02 POEG0: GTETRG SCI1: SDA SCI1: TXD_MOSI
36 P214 7 Disabled CGC0: XCOUT
37 P215 6 Disabled CGC0: XCIN
38 P300 32 DEBUG0_TCK Low Peripheral mode CMOS None DEBUG0: SWCLK DEBUG0: TCK GPT0: GTIOCA OPS0: GTOUUP SPI1: SSL1
39 P301 31 GPIO IRQ6 Input mode None AGT0: AGTIO CTSU0: TS09 GPT4: GTIOCB IRQ0: IRQ06 OPS0: GTOULO SCI2: RXD_MISO SCI2: SCL SCI9: CTS_RTS_SS SLCDC0: COM5 SLCDC0: SEG01 SPI1: SSL2
40 P302 30 GPIO IRQ5 Input mode None CTSU0: TS08 GPT4: GTIOCA IRQ0: IRQ05 OPS0: GTOUUP SCI2: SDA SCI2: TXD_MOSI SLCDC0: COM6 SLCDC0: SEG02 SPI1: SSL3
41 P303 29 Disabled CTSU0: TS02 GPT7: GTIOCB SLCDC0: COM7 SLCDC0: SEG03
42 P304 28 GPIO IRQ9 Input mode None CTSU0: TS11 GPT7: GTIOCA IRQ0: IRQ09 SLCDC0: SEG20
43 P400 1 Disabled AGT1: AGTIO CAC0: CACREF CTSU0: TS20 GPT6: GTIOCA IIC0: SCL IRQ0: IRQ00 SCI0: SCK SCI1: SCK SLCDC0: SEG04 SSI: AUDIO_CLK
44 P401 2 SCI1_TXD_MOSI Low None Peripheral mode CMOS None CAN0: CTX CTSU0: TS19 GPT6: GTIOCB IIC0: SDA IRQ0: IRQ05 POEG0: GTETRG SCI0: CTS_RTS_SS SCI1: SDA SCI1: TXD_MOSI SLCDC0: SEG05
45 P402 3 SCI1_RXD_MISO Low None Peripheral mode CMOS None AGT0: AGTIO AGT1: AGTIO CAN0: CRX CTSU0: TS18 IRQ0: IRQ04 RTC0: RTCIC0 SCI1: RXD_MISO SCI1: SCL SLCDC0: SEG06
46 P407 16 Disabled ADC0: ADTRG AGT0: AGTIO CTSU0: TS03 IIC0: SDA RTC0: RTCOUT SCI0: CTS_RTS_SS SLCDC0: SEG11 SPI1: SSL3 USBFS0: VBUS
47 P408 15 GPIO Low None Output mode (Initial Low) CMOS None CTSU0: TS04 GPT5: GTIOCB IIC0: SCL IRQ0: IRQ07 OPS0: GTOWLO SCI1: CTS_RTS_SS SCI9: RXD_MISO SCI9: SCL SLCDC0: SEG10 USBFS0: ID
48 P409 14 GPIO Low None Output mode (Initial Low) CMOS None CTSU0: TS05 GPT5: GTIOCA IRQ0: IRQ06 OPS0: GTOWUP SCI9: SDA SCI9: TXD_MOSI SLCDC0: SEG09 USBFS0: EXICEN
49 P410 13 SCI0_RXD_MISO Low None Peripheral mode CMOS None AGT1: AGTOB CTSU0: TS06 GPT6: GTIOCB IRQ0: IRQ05 OPS0: GTOVLO SCI0: RXD_MISO SCI0: SCL SLCDC0: SEG08 SPI0: MISO
50 P411 12 SCI0_TXD_MOSI Low None Peripheral mode CMOS None AGT1: AGTOA CTSU0: TS07 GPT6: GTIOCA IRQ0: IRQ04 OPS0: GTOVUP SCI0: SDA SCI0: TXD_MOSI SLCDC0: SEG07 SPI0: MOSI
51 P500 49 Disabled ADC0: AN16 AGT0: AGTOA CMP0: CMPREF1 GPT2: GTIOCA OPS0: GTIU SLCDC0: SEG34 USBFS0: VBUSEN
52 P501 50 Disabled ADC0: AN17 AGT0: AGTOB CMP0: CMPIN1 GPT2: GTIOCB IRQ0: IRQ11 OPS0: GTIV SCI1: SDA SCI1: TXD_MOSI SLCDC0: SEG35 USBFS0: OVRCURA
53 P502 51 Disabled ADC0: AN18 CMP0: CMPREF0 GPT3: GTIOCB IRQ0: IRQ12 OPS0: GTIW SCI1: RXD_MISO SCI1: SCL SLCDC0: SEG36 USBFS0: OVRCURB
54 P914 19 Disabled USBFS0: USBDP
55 P915 18 Disabled USBFS0: USBDM
56 RES 25
57 VBAT 4
58 VCC 11
59 VCC 39
60 VCCUSB 20 USBFS0_VCCUSB
61 VCCUSBLDO 21 USBFS0_VCCUSBLDO
62 VCL 5
63 VSS 8
64 VSS 40
65 VSSUSB 17 USBFS0_VSSUSB

21
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h Normal file
View File

@ -0,0 +1,21 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
#endif /* BSP_CLOCK_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_pin_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef BSP_PIN_CFG_H_
#define BSP_PIN_CFG_H_
#include "bsp_api.h"
#include "r_ioport_api.h"
extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CFM.pincfg */
#endif /* BSP_PIN_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c Normal file
View File

@ -0,0 +1,7 @@
/* generated common source file - do not edit */
#include "common_data.h"
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
void g_common_init(void) {
}

16
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h Normal file
View File

@ -0,0 +1,16 @@
/* generated common header file - do not edit */
#ifndef COMMON_DATA_H_
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

487
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c Normal file
View File

@ -0,0 +1,487 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
icu_instance_ctrl_t g_external_irq9_ctrl;
const external_irq_cfg_t g_external_irq9_cfg =
{ .channel = 9,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ9)
.irq = VECTOR_NUMBER_ICU_IRQ9,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq9 =
{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu };
icu_instance_ctrl_t g_external_irq6_ctrl;
const external_irq_cfg_t g_external_irq6_cfg =
{ .channel = 6,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ6)
.irq = VECTOR_NUMBER_ICU_IRQ6,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq6 =
{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu };
iic_master_instance_ctrl_t g_i2c_master1_ctrl;
const iic_master_extended_cfg_t g_i2c_master1_extend =
{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT,
/* Actual calculated bitrate: 99272. Actual calculated duty cycle: 49%. */ .clock_settings.brl_value = 27,
.clock_settings.brh_value = 26, .clock_settings.cks_value = 2, };
const i2c_master_cfg_t g_i2c_master1_cfg =
{ .channel = 1, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.p_callback = callback_iic,
.p_context = NULL,
#if defined(VECTOR_NUMBER_IIC1_RXI)
.rxi_irq = VECTOR_NUMBER_IIC1_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC1_TXI)
.txi_irq = VECTOR_NUMBER_IIC1_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC1_TEI)
.tei_irq = VECTOR_NUMBER_IIC1_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_IIC1_ERI)
.eri_irq = VECTOR_NUMBER_IIC1_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.ipl = (12),
.p_extend = &g_i2c_master1_extend, };
/* Instance structure to use this module. */
const i2c_master_instance_t g_i2c_master1 =
{ .p_ctrl = &g_i2c_master1_ctrl, .p_cfg = &g_i2c_master1_cfg, .p_api = &g_i2c_master_on_iic };
adc_instance_ctrl_t g_adc0_ctrl;
const adc_extended_cfg_t g_adc0_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc0_cfg =
{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc0_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc0 =
{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
lpm_instance_ctrl_t g_lpm0_ctrl;
const lpm_cfg_t g_lpm0_cfg =
{ .low_power_mode = LPM_MODE_SLEEP,
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
.snooze_end_sources = (lpm_snooze_end_t)0,
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
.output_port_enable = 0,
#endif
#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY
.io_port_state = 0,
.power_supply_state = 0,
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
#endif
.p_extend = NULL, };
const lpm_instance_t g_lpm0 =
{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
dtc_instance_ctrl_t g_transfer1_ctrl;
transfer_info_t g_transfer1_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer1_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
const transfer_cfg_t g_transfer1_cfg =
{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer1 =
{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer0_ctrl;
transfer_info_t g_transfer0_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer0_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
const transfer_cfg_t g_transfer0_cfg =
{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer0 =
{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi0_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi0_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 12000000. */ .spbr = 1,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi0_cfg =
{ .channel = 0,
#if defined(VECTOR_NUMBER_SPI0_RXI)
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TXI)
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TEI)
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_ERI)
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi0_P_TRANSFER_TX,
.p_transfer_rx = g_spi0_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi0_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi0 =
{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
icu_instance_ctrl_t g_external_irq5_ctrl;
const external_irq_cfg_t g_external_irq5_cfg =
{ .channel = 5,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ5)
.irq = VECTOR_NUMBER_ICU_IRQ5,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq5 =
{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu };
agt_instance_ctrl_t g_timer0_ctrl;
const agt_extended_cfg_t g_timer0_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer0_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer0_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer0 =
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
flash_lp_instance_ctrl_t g_flash0_ctrl;
const flash_cfg_t g_flash0_cfg =
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_FCU_FRDYI)
.irq = VECTOR_NUMBER_FCU_FRDYI,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const flash_instance_t g_flash0 =
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp };
rtc_instance_ctrl_t g_rtc0_ctrl;
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
.adjustment_value = 0, };
const rtc_cfg_t g_rtc0_cfg =
{ .clock_source = RTC_CLOCK_SOURCE_SUBCLK, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
NULL,
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
#if defined(VECTOR_NUMBER_RTC_ALARM)
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
#else
.alarm_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_PERIOD)
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
#else
.periodic_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_CARRY)
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
#else
.carry_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const rtc_instance_t g_rtc0 =
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
sci_uart_instance_ctrl_t g_uart1_ctrl;
baud_setting_t g_uart1_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart1_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart1_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart1_cfg =
{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart1_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI1_RXI)
.rxi_irq = VECTOR_NUMBER_SCI1_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TXI)
.txi_irq = VECTOR_NUMBER_SCI1_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TEI)
.tei_irq = VECTOR_NUMBER_SCI1_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_ERI)
.eri_irq = VECTOR_NUMBER_SCI1_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart1 =
{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart0_ctrl;
baud_setting_t g_uart0_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart0_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart0_cfg =
{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart0_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI0_RXI)
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TXI)
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TEI)
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_ERI)
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart0 =
{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci };
void g_hal_init(void) {
g_common_init();
}

175
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h Normal file
View File

@ -0,0 +1,175 @@
/* generated HAL header file - do not edit */
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_iic_master.h"
#include "r_i2c_master_api.h"
#include "r_adc.h"
#include "r_adc_api.h"
#include "r_lpm.h"
#include "r_lpm_api.h"
#include "r_dtc.h"
#include "r_transfer_api.h"
#include "r_spi.h"
#include "r_agt.h"
#include "r_timer_api.h"
#include "r_flash_lp.h"
#include "r_flash_api.h"
#include "r_rtc.h"
#include "r_rtc_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq9;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq9_ctrl;
extern const external_irq_cfg_t g_external_irq9_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq6;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq6_ctrl;
extern const external_irq_cfg_t g_external_irq6_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/* I2C Master on IIC Instance. */
extern const i2c_master_instance_t g_i2c_master1;
/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */
extern iic_master_instance_ctrl_t g_i2c_master1_ctrl;
extern const i2c_master_cfg_t g_i2c_master1_cfg;
#ifndef callback_iic
void callback_iic(i2c_master_callback_args_t *p_args);
#endif
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc0;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc0_ctrl;
extern const adc_cfg_t g_adc0_cfg;
extern const adc_channel_cfg_t g_adc0_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/** lpm Instance */
extern const lpm_instance_t g_lpm0;
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
extern lpm_instance_ctrl_t g_lpm0_ctrl;
extern const lpm_cfg_t g_lpm0_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer1;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer1_ctrl;
extern const transfer_cfg_t g_transfer1_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer0;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer0_ctrl;
extern const transfer_cfg_t g_transfer0_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi0;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi0_ctrl;
extern const spi_cfg_t g_spi0_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer0)
#define g_spi0_P_TRANSFER_TX (NULL)
#else
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
#endif
#if (RA_NOT_DEFINED == g_transfer1)
#define g_spi0_P_TRANSFER_RX (NULL)
#else
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
#endif
#undef RA_NOT_DEFINED
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq5;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq5_ctrl;
extern const external_irq_cfg_t g_external_irq5_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer0;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer0_ctrl;
extern const timer_cfg_t g_timer0_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/* Flash on Flash LP Instance. */
extern const flash_instance_t g_flash0;
/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */
extern flash_lp_instance_ctrl_t g_flash0_ctrl;
extern const flash_cfg_t g_flash0_cfg;
#ifndef NULL
void NULL(flash_callback_args_t *p_args);
#endif
/* RTC Instance. */
extern const rtc_instance_t g_rtc0;
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
extern rtc_instance_ctrl_t g_rtc0_ctrl;
extern const rtc_cfg_t g_rtc0_cfg;
#ifndef NULL
void NULL(rtc_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart1;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart1_ctrl;
extern const uart_cfg_t g_uart1_cfg;
extern const sci_uart_extended_cfg_t g_uart1_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart0;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart0_ctrl;
extern const uart_cfg_t g_uart0_cfg;
extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

6
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/main.c Normal file
View File

@ -0,0 +1,6 @@
/* generated main source file - do not edit */
#include "hal_data.h"
int main(void) {
hal_entry();
return 0;
}

73
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c Normal file
View File

@ -0,0 +1,73 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_08,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_03_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_03_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_03_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_03_PIN_04,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_04_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_08,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
};

57
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c Normal file
View File

@ -0,0 +1,57 @@
/* generated vector source file - do not edit */
#include "bsp_api.h"
/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
#if VECTOR_DATA_IRQ_COUNT > 0
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
{
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */
[2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */
[3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */
[4] = sci_uart_rxi_isr, /* SCI1 RXI (Received data full) */
[5] = sci_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */
[6] = sci_uart_tei_isr, /* SCI1 TEI (Transmit end) */
[7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */
[8] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[9] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[10] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[11] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[12] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */
[13] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[14] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[15] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[16] = spi_eri_isr, /* SPI0 ERI (Error) */
[17] = iic_master_rxi_isr, /* IIC1 RXI (Receive data full) */
[18] = iic_master_txi_isr, /* IIC1 TXI (Transmit data empty) */
[19] = iic_master_tei_isr, /* IIC1 TEI (Transmit end) */
[20] = iic_master_eri_isr, /* IIC1 ERI (Transfer error) */
[21] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */
[22] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
[0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */
[1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */
[2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */
[3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */
[4] = BSP_PRV_IELS_ENUM(EVENT_SCI1_RXI), /* SCI1 RXI (Received data full) */
[5] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TXI), /* SCI1 TXI (Transmit data empty) */
[6] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TEI), /* SCI1 TEI (Transmit end) */
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */
[8] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[9] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[10] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[11] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[12] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */
[13] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[14] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[15] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[16] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
[17] = BSP_PRV_IELS_ENUM(EVENT_IIC1_RXI), /* IIC1 RXI (Receive data full) */
[18] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TXI), /* IIC1 TXI (Transmit data empty) */
[19] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TEI), /* IIC1 TEI (Transmit end) */
[20] = BSP_PRV_IELS_ENUM(EVENT_IIC1_ERI), /* IIC1 ERI (Transfer error) */
[21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */
[22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */
};
#endif

87
ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h Normal file
View File

@ -0,0 +1,87 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (23)
#endif
/* ISR prototypes */
void sci_uart_rxi_isr(void);
void sci_uart_txi_isr(void);
void sci_uart_tei_isr(void);
void sci_uart_eri_isr(void);
void rtc_alarm_periodic_isr(void);
void rtc_carry_isr(void);
void agt_int_isr(void);
void r_icu_isr(void);
void spi_rxi_isr(void);
void spi_txi_isr(void);
void spi_tei_isr(void);
void spi_eri_isr(void);
void iic_master_rxi_isr(void);
void iic_master_txi_isr(void);
void iic_master_tei_isr(void);
void iic_master_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */
#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)8) /* RTC ALARM (Alarm interrupt) */
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)9) /* RTC PERIOD (Periodic interrupt) */
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)10) /* RTC CARRY (Carry interrupt) */
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)11) /* AGT0 INT (AGT interrupt) */
#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)12) /* ICU IRQ5 (External pin interrupt 5) */
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)13) /* SPI0 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)14) /* SPI0 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)15) /* SPI0 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)16) /* SPI0 ERI (Error) */
#define VECTOR_NUMBER_IIC1_RXI ((IRQn_Type)17) /* IIC1 RXI (Receive data full) */
#define VECTOR_NUMBER_IIC1_TXI ((IRQn_Type)18) /* IIC1 TXI (Transmit data empty) */
#define VECTOR_NUMBER_IIC1_TEI ((IRQn_Type)19) /* IIC1 TEI (Transmit end) */
#define VECTOR_NUMBER_IIC1_ERI ((IRQn_Type)20) /* IIC1 ERI (Transfer error) */
#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)21) /* ICU IRQ6 (External pin interrupt 6) */
#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)22) /* ICU IRQ9 (External pin interrupt 9) */
typedef enum IRQn
{
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */
SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */
SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */
SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */
SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */
SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */
SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */
SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */
RTC_ALARM_IRQn = 8, /* RTC ALARM (Alarm interrupt) */
RTC_PERIOD_IRQn = 9, /* RTC PERIOD (Periodic interrupt) */
RTC_CARRY_IRQn = 10, /* RTC CARRY (Carry interrupt) */
AGT0_INT_IRQn = 11, /* AGT0 INT (AGT interrupt) */
ICU_IRQ5_IRQn = 12, /* ICU IRQ5 (External pin interrupt 5) */
SPI0_RXI_IRQn = 13, /* SPI0 RXI (Receive buffer full) */
SPI0_TXI_IRQn = 14, /* SPI0 TXI (Transmit buffer empty) */
SPI0_TEI_IRQn = 15, /* SPI0 TEI (Transmission complete event) */
SPI0_ERI_IRQn = 16, /* SPI0 ERI (Error) */
IIC1_RXI_IRQn = 17, /* IIC1 RXI (Receive data full) */
IIC1_TXI_IRQn = 18, /* IIC1 TXI (Transmit data empty) */
IIC1_TEI_IRQn = 19, /* IIC1 TEI (Transmit end) */
IIC1_ERI_IRQn = 20, /* IIC1 ERI (Transfer error) */
ICU_IRQ6_IRQn = 21, /* ICU IRQ6 (External pin interrupt 6) */
ICU_IRQ9_IRQn = 22, /* ICU IRQ9 (External pin interrupt 9) */
} IRQn_Type;
#endif /* VECTOR_DATA_H */

58
ports/renesas-ra/boards/RA4M1_CLICKER/src/hal_entry.c Normal file
View File

@ -0,0 +1,58 @@
#include "hal_data.h"
FSP_CPP_HEADER
void R_BSP_WarmStart(bsp_warm_start_event_t event);
FSP_CPP_FOOTER
void ra_main(uint32_t reset_mode);
/*******************************************************************************************************************//**
* main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function
* is called by main() when no RTOS is used.
**********************************************************************************************************************/
void hal_entry(void) {
/* TODO: add your own code here */
ra_main(1);
#if BSP_TZ_SECURE_BUILD
/* Enter non-secure code */
R_BSP_NonSecureEnter();
#endif
}
/*******************************************************************************************************************//**
* This function is called at various points during the startup process. This implementation uses the event that is
* called right before main() to set up the pins.
*
* @param[in] event Where at in the start up process the code is currently at
**********************************************************************************************************************/
void R_BSP_WarmStart(bsp_warm_start_event_t event) {
if (BSP_WARM_START_RESET == event) {
#if BSP_FEATURE_FLASH_LP_VERSION != 0
/* Enable reading from data flash. */
R_FACI_LP->DFLCTL = 1U;
/* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
* C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
#endif
}
if (BSP_WARM_START_POST_C == event) {
/* C runtime environment and system clocks are setup. */
/* Configure pins. */
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
}
}
#if BSP_TZ_SECURE_BUILD
BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable();
/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */
BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() {
}
#endif

21
ports/renesas-ra/boards/RA4M1_EK/board.json Normal file
View File

@ -0,0 +1,21 @@
{
"deploy": [
"../deploy.md"
],
"docs": "",
"features": [
"UART",
"SPI",
"I2C",
"ADC"
],
"id": "EK-RA4M1",
"images": [
"ek_ra4m1_board.jpg"
],
"mcu": "RA4M1",
"product": "EK-RA4M1",
"thumbnail": "",
"url": "https://www.renesas.com/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group",
"vendor": "Renesas Electronics"
}

2
ports/renesas-ra/boards/RA4M1_EK/manifest.py Normal file
View File

@ -0,0 +1,2 @@
# We do not want to include default frozen modules,
freeze("$(MPY_DIR)/drivers/sdcard", "sdcard.py")

70
ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.h Normal file
View File

@ -0,0 +1,70 @@
// MCU config
#define MICROPY_HW_BOARD_NAME "RA4M1_EK"
#define MICROPY_HW_MCU_NAME "RA4M1"
#define MICROPY_HW_MCU_SYSCLK 48000000
#define MICROPY_HW_MCU_PCLK 48000000
// module config
#define MICROPY_EMIT_THUMB (0)
#define MICROPY_EMIT_INLINE_THUMB (0)
#define MICROPY_PY_BUILTINS_COMPLEX (0)
#define MICROPY_PY_GENERATOR_PEND_THROW (0)
#define MICROPY_PY_MATH (0)
#define MICROPY_PY_UHEAPQ (0)
#define MICROPY_PY_UTIMEQ (0)
#define MICROPY_PY_THREAD (0)
// peripheral config
#define MICROPY_HW_ENABLE_RTC (1)
#define MICROPY_HW_RTC_SOURCE (0) // 0: subclock, 1:LOCO
#define MICROPY_HW_ENABLE_ADC (1)
#define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
// board config
// UART
#define MICROPY_HW_UART0_TX (pin_P411) // REPL
#define MICROPY_HW_UART0_RX (pin_P410) // REPL
#define MICROPY_HW_UART1_TX (pin_P401) // PMOD B
#define MICROPY_HW_UART1_RX (pin_P402) // PMOD B
#define MICROPY_HW_UART1_CTS (pin_P403) // PMOD B
#define MICROPY_HW_UART2_TX (pin_P302)
#define MICROPY_HW_UART2_RX (pin_P301)
#define MICROPY_HW_UART2_CTS (pin_P203) // (Conflict with SPI1)
// #define MICROPY_HW_UART9_TX (pin_P602) // Disable (vector not registered)
// #define MICROPY_HW_UART9_RX (pin_P601) // Disable (vector not registered)
// #define MICROPY_HW_UART9_CTS (pin_P603) // Disable (vector not registered)
#define MICROPY_HW_UART_REPL HW_UART_0
#define MICROPY_HW_UART_REPL_BAUD 115200
// I2C (not supported)
// #define MICROPY_HW_I2C0_SCL (pin_P204) // Conflict with SPI1
// #define MICROPY_HW_I2C0_SDA (pin_P407) // Conflict with USB_VBUS
// #define MICROPY_HW_I2C0_SCL (pin_P400) // Conflict wiht PMOD B (GPIO)
// #define MICROPY_HW_I2C0_SDA (pin_P401) // Conflict with PMOD B (TXD1)
// #define MICROPY_HW_I2C1_SCL (pin_P100) // Conflict with PMOD A (MISOA_A)
// #define MICROPY_HW_I2C1_SDA (pin_P101) // Conflict with PMOD A (MOSIA_A)
// SPI
#define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD A
#define MICROPY_HW_SPI0_RSPCK (pin_P102) // PMOD A
#define MICROPY_HW_SPI0_MISO (pin_P100) // PMOD A
#define MICROPY_HW_SPI0_MOSI (pin_P101) // PMOD A
#define MICROPY_HW_SPI1_SSL (pin_P206) // Use SSLB1 due to SSLB0 is used for TSCAP
// #define MICROPY_HW_SPI1_RSPCK (pin_P204) // Disable (vector not registered)
// #define MICROPY_HW_SPI1_MISO (pin_P202) // Disable (vector not registered)
// #define MICROPY_HW_SPI1_MOSI (pin_P203) // Disable (vector not registered)
// Switch
#define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_USRSW_PIN (pin_P105)
#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING)
#define MICROPY_HW_USRSW_PRESSED (0)
// LEDs
#define MICROPY_HW_LED1 (pin_P106)
#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin)
#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin)
#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin)

9
ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.mk Normal file
View File

@ -0,0 +1,9 @@
CMSIS_MCU = RA4M1
MCU_SERIES = m4
LD_FILES = boards/RA4M1_EK/ra4m1_ek.ld
# MicroPython settings
MICROPY_VFS_FAT = 1
# Don't include default frozen modules because MCU is tight on flash space
FROZEN_MANIFEST ?= boards/RA4M1_EK/manifest.py

104
ports/renesas-ra/boards/RA4M1_EK/pins.csv Normal file
View File

@ -0,0 +1,104 @@
P000,P000
P001,P001
P002,P002
P003,P003
P004,P004
P005,P005
P006,P006
P007,P007
P008,P008
P010,P010
P011,P011
P012,P012
P013,P013
P014,P014
P015,P015
P100,P100
P101,P101
P102,P102
P103,P103
P104,P104
P105,P105
P106,P106
P107,P107
P108,P108
P109,P109
P110,P110
P111,P111
P112,P112
P113,P113
P114,P114
P115,P115
P200,P200
P201,P201
P202,P202
P203,P203
P204,P204
P205,P205
P206,P206
P212,P212
P213,P213
P214,P214
P215,P215
P300,P300
P301,P301
P302,P302
P303,P303
P304,P304
P400,P400
P401,P401
P402,P402
P403,P403
P404,P404
P405,P405
P406,P406
P407,P407
P408,P408
P409,P409
P410,P410
P411,P411
P412,P412
P413,P413
P414,P414
P415,P415
P500,P500
P501,P501
P502,P502
P503,P503
P504,P504
P505,P505
P600,P601
P601,P601
P602,P602
P603,P603
P608,P608
P609,P609
P610,P610
P808,P808
P809,P809
P708,P708
P914,P914
P915,P915
MBAN,P000
MBMISO,P100
MBMOSI,P101
MBSCK,P102
MBSSL,P103
MBPWM,P107
SWDIO,P108
SWO,P109
TDI,P110
TSCAP,P112
MD,P201
MBSCLI,P205
MBSDA1,P206
SWCLK,P300
MBINT,P302
SW1,P105
MBRST,P407
LED1,P106
MBRX0,P410
MBTX0,P411
USBDP,P914
USBDM,P915
1 P000 P000
2 P001 P001
3 P002 P002
4 P003 P003
5 P004 P004
6 P005 P005
7 P006 P006
8 P007 P007
9 P008 P008
10 P010 P010
11 P011 P011
12 P012 P012
13 P013 P013
14 P014 P014
15 P015 P015
16 P100 P100
17 P101 P101
18 P102 P102
19 P103 P103
20 P104 P104
21 P105 P105
22 P106 P106
23 P107 P107
24 P108 P108
25 P109 P109
26 P110 P110
27 P111 P111
28 P112 P112
29 P113 P113
30 P114 P114
31 P115 P115
32 P200 P200
33 P201 P201
34 P202 P202
35 P203 P203
36 P204 P204
37 P205 P205
38 P206 P206
39 P212 P212
40 P213 P213
41 P214 P214
42 P215 P215
43 P300 P300
44 P301 P301
45 P302 P302
46 P303 P303
47 P304 P304
48 P400 P400
49 P401 P401
50 P402 P402
51 P403 P403
52 P404 P404
53 P405 P405
54 P406 P406
55 P407 P407
56 P408 P408
57 P409 P409
58 P410 P410
59 P411 P411
60 P412 P412
61 P413 P413
62 P414 P414
63 P415 P415
64 P500 P500
65 P501 P501
66 P502 P502
67 P503 P503
68 P504 P504
69 P505 P505
70 P600 P601
71 P601 P601
72 P602 P602
73 P603 P603
74 P608 P608
75 P609 P609
76 P610 P610
77 P808 P808
78 P809 P809
79 P708 P708
80 P914 P914
81 P915 P915
82 MBAN P000
83 MBMISO P100
84 MBMOSI P101
85 MBSCK P102
86 MBSSL P103
87 MBPWM P107
88 SWDIO P108
89 SWO P109
90 TDI P110
91 TSCAP P112
92 MD P201
93 MBSCLI P205
94 MBSDA1 P206
95 SWCLK P300
96 MBINT P302
97 SW1 P105
98 MBRST P407
99 LED1 P106
100 MBRX0 P410
101 MBTX0 P411
102 USBDP P914
103 USBDM P915

298
ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek.ld Normal file
View File

@ -0,0 +1,298 @@
/*
Linker File for RA4M1 MCU
*/
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256KB */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* 32KB */
DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */
ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */
}
/* Library configurations */
/*GROUP(libgcc.a libc.a libm.a libnosys.a) */
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
_stext = .;
__ROM_Start = .;
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
* space because ROM registers are at address 0x400 and there is very little space
* in between. */
KEEP(*(.fixed_vectors*))
KEEP(*(.application_vectors*))
__Vectors_End = .;
__end__ = .;
/* ROM Registers start at address 0x00000400 */
. = __ROM_Start + 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = __ROM_Start + 0x500;
*(.text*)
KEEP(*(.version))
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
__usb_dev_descriptor_start_fs = .;
KEEP(*(.usb_device_desc_fs*))
__usb_cfg_descriptor_start_fs = .;
KEEP(*(.usb_config_desc_fs*))
__usb_interface_descriptor_start_fs = .;
KEEP(*(.usb_interface_desc_fs*))
__usb_descriptor_end_fs = .;
__usb_dev_descriptor_start_hs = .;
KEEP(*(.usb_device_desc_hs*))
__usb_cfg_descriptor_start_hs = .;
KEEP(*(.usb_config_desc_hs*))
__usb_interface_descriptor_start_hs = .;
KEEP(*(.usb_interface_desc_hs*))
__usb_descriptor_end_hs = .;
KEEP(*(.eh_frame*))
__ROM_End = .;
_etext = .;
} > FLASH = 0xFF
__Vectors_Size = __Vectors_End - __Vectors;
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
.fsp_dtc_vector_table (NOLOAD) :
{
. = ORIGIN(RAM);
*(.fsp_dtc_vector_table)
} > RAM
/* Initialized data section. */
.data :
{
_sidata = .;
_sdata = .;
__data_start__ = .;
*(vtable)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM AT > FLASH
.noinit (NOLOAD):
{
. = ALIGN(4);
__noinit_start = .;
KEEP(*(.noinit*))
__noinit_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (NOLOAD):
{
. = ALIGN(8);
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* Stacks are stored in this section. */
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
__StackLimit = .;
/* Main stack */
KEEP(*(.stack))
__StackTop = .;
/* Thread stacks */
KEEP(*(.stack*))
__StackTopAll = .;
_estack = .;
} > RAM
PROVIDE(__stack = __StackTopAll);
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
at run time for things such as ThreadX memory pool allocations. */
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
/* Data flash. */
.data_flash :
{
__Data_Flash_Start = .;
KEEP(*(.data_flash*))
__Data_Flash_End = .;
} > DATA_FLASH
.id_code :
{
__ID_Code_Start = .;
KEEP(*(.id_code*))
__ID_Code_End = .;
} > ID_CODE
}
/* produce a link error if there is not this amount of RAM for these sections */
/* _minimum_stack_size = 2K; */
/* _minimum_heap_size = 16K; */
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = __HeapBase; /* heap starts just after statically allocated memory */
_heap_end = __HeapLimit; /* tunable */

30
ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek_conf.h Normal file
View File

@ -0,0 +1,30 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef RA4M1_EK_CONF_H
#define RA4M1_EK_CONF_H
#define DEBUG_CH 0
#endif /* RA4M1_EK_CONF_H */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
#include "../../../ra/board/ra4m1_ek/board.h"
#endif /* BOARD_CFG_H_ */

49
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h Normal file
View File

@ -0,0 +1,49 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
#ifndef BSP_CFG_RTOS
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (2)
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (1)
#else
#define BSP_CFG_RTOS (0)
#endif
#endif
#undef RA_NOT_DEFINED
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
#define BSP_CFG_HEAP_BYTES (0x4980)
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
#define BSP_CFG_ASSERT (0)
#define BSP_CFG_ERROR_LOG (0)
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#endif /* BSP_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_CFG_H_
#define BSP_MCU_DEVICE_CFG_H_
#define BSP_CFG_MCU_PART_SERIES (4)
#endif /* BSP_MCU_DEVICE_CFG_H_ */

10
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h Normal file
View File

@ -0,0 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA4M1AB3CFP
#define BSP_ROM_SIZE_BYTES (262144)
#define BSP_RAM_SIZE_BYTES (32768)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
#define BSP_PACKAGE_LQFP
#define BSP_PACKAGE_PINS (100)
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

74
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h Normal file
View File

@ -0,0 +1,74 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
#define BSP_MCU_GROUP_RA4M1 (1)
#define BSP_LOCO_HZ (32768)
#define BSP_MOCO_HZ (8000000)
#define BSP_SUB_CLOCK_HZ (32768)
#if BSP_CFG_HOCO_FREQUENCY == 0
#define BSP_HOCO_HZ (24000000)
#elif BSP_CFG_HOCO_FREQUENCY == 2
#define BSP_HOCO_HZ (32000000)
#elif BSP_CFG_HOCO_FREQUENCY == 4
#define BSP_HOCO_HZ (48000000)
#elif BSP_CFG_HOCO_FREQUENCY == 5
#define BSP_HOCO_HZ (64000000)
#else
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
#define OFS_SEQ5 (1 << 28) | (1 << 30)
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
/*
ID Code
Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
*/
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
#else
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h Normal file
View File

@ -0,0 +1,6 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_LP_CFG_H_
#define R_FLASH_LP_CFG_H_
#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#endif /* R_FLASH_LP_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_IOPORT_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h Normal file
View File

@ -0,0 +1,8 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

450
ports/renesas-ra/boards/RA4M1_EK/ra_gen/RA4M1-EK.csv Normal file
View File

@ -0,0 +1,450 @@
"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities"
"AVCC0","88","ADC_AVCC0","","","","","",""
"AVSS0","89","ADC_AVSS0","","","","","",""
"P000","100","ADC0_AN00","","","Analog mode","","","ADC0: AN00
CTSU0: TS21
IRQ0: IRQ06
OPAMP0: AMP+"
"P001","99","","","","Disabled","","","ADC0: AN01
CTSU0: TS22
IRQ0: IRQ07
OPAMP0: AMP-"
"P002","98","","","","Disabled","","","ADC0: AN02
IRQ0: IRQ02
OPAMP0: AMPO"
"P003","97","","","","Disabled","","","ADC0: AN03
OPAMP1: AMPO"
"P004","96","","","","Disabled","","","ADC0: AN04
IRQ0: IRQ03
OPAMP2: AMPO"
"P005","95","","","","Disabled","","","ADC0: AN11
IRQ0: IRQ10
OPAMP3: AMP+"
"P006","94","","","","Disabled","","","ADC0: AN12
OPAMP3: AMP-"
"P007","93","","","","Disabled","","","ADC0: AN13
OPAMP3: AMPO"
"P008","92","","","","Disabled","","","ADC0: AN14"
"P010","91","","","","Disabled","","","ADC: VREFH0
ADC0: AN05
CTSU0: TS30
OPAMP2: AMP-"
"P011","90","","","","Disabled","","","ADC: VREFL0
ADC0: AN06
CTSU0: TS31
IRQ0: IRQ15
OPAMP2: AMP+"
"P012","87","","","","Disabled","","","ADC: VREFH
ADC0: AN07
OPAMP1: AMP-"
"P013","86","","","","Disabled","","","ADC: VREFL
ADC0: AN08
OPAMP1: AMP+"
"P014","85","","","","Disabled","","","ADC0: AN09
DAC120: DA"
"P015","84","","","","Disabled","","","ADC0: AN10
CTSU0: TS28
IRQ0: IRQ07"
"P100","75","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ADC0: AN22
AGT0: AGTIO
CMP0: CMPIN0
GPT5: GTIOCB
IIC1: SCL
IRQ0: IRQ02
KINT0: KRM0
POEG0: GTETRG
SCI0: RXD_MISO
SCI0: SCL
SCI1: SCK
SLCDC0: VL1
SPI0: MISO"
"P101","74","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ADC0: AN21
AGT0: AGTEE
CMP0: CMPREF0
GPT5: GTIOCA
IIC1: SDA
IRQ0: IRQ01
KINT0: KRM1
POEG1: GTETRG
SCI0: SDA
SCI0: TXD_MOSI
SCI1: CTS_RTS_SS
SLCDC0: VL2
SPI0: MOSI"
"P102","73","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG
ADC0: AN20
AGT0: AGTO
CAN0: CRX
CMP0: CMPIN1
GPT2: GTIOCB
KINT0: KRM2
OPS0: GTOWLO
SCI0: SCK
SCI2: SDA
SCI2: TXD_MOSI
SLCDC0: VL3
SPI0: RSPCK"
"P103","72","SPI0_SSL0","Low","","Peripheral mode","CMOS","None","ADC0: AN19
CAN0: CTX
CMP0: CMPREF1
GPT2: GTIOCA
KINT0: KRM3
OPS0: GTOWUP
SCI0: CTS_RTS_SS
SLCDC0: VL4
SPI0: SSL0"
"P104","71","","","","Disabled","","","CTSU0: TS13
GPT1: GTIOCB
IRQ0: IRQ01
KINT0: KRM4
POEG1: GTETRG
SCI0: RXD_MISO
SCI0: SCL
SLCDC0: COM0
SPI0: SSL1"
"P105","70","GPIO","","IRQ0","Input mode","","None","CTSU0: TS34
GPT1: GTIOCA
IRQ0: IRQ00
KINT0: KRM5
POEG0: GTETRG
SLCDC0: COM1
SPI0: SSL2"
"P106","69","GPIO","Low","","Output mode (Initial Low)","CMOS","None","GPT0: GTIOCB
KINT0: KRM6
SLCDC0: COM2
SPI0: SSL3"
"P107","68","","","","Disabled","","","GPT0: GTIOCA
KINT0: KRM7
SLCDC0: COM3"
"P108","51","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO
DEBUG0: TMS
GPT0: GTIOCB
OPS0: GTOULO
SCI9: CTS_RTS_SS
SPI1: SSL0"
"P109","52","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN0: CTX
CGC0: CLKOUT
CTSU0: TS10
DEBUG0: SWO
DEBUG0: TDO
GPT1: GTIOCA
OPS0: GTOVUP
SCI1: SCK
SCI9: SDA
SCI9: TXD_MOSI
SLCDC0: SEG23
SPI1: MOSI"
"P110","53","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","CAN0: CRX
CMP0: VCOUT
DEBUG0: TDI
GPT1: GTIOCB
IRQ0: IRQ03
OPS0: GTOVLO
SCI2: CTS_RTS_SS
SCI9: RXD_MISO
SCI9: SCL
SLCDC0: SEG24
SPI1: MISO"
"P111","54","","","","Disabled","","","CTSU0: TS12
GPT3: GTIOCA
IRQ0: IRQ04
SCI2: SCK
SCI9: SCK
SLCDC0: CAPH
SPI1: RSPCK"
"P112","55","","","","Disabled","","","CTSU0: TSCAP
GPT3: GTIOCB
SCI1: SCK
SCI2: SDA
SCI2: TXD_MOSI
SLCDC0: CAPL
SPI1: SSL0
SSI0: SSISCK"
"P113","56","","","","Disabled","","","CTSU0: TS27
GPT2: GTIOCA
SLCDC0: COM4
SLCDC0: SEG00
SSI0: SSIWS"
"P114","57","","","","Disabled","","","CTSU0: TS29
GPT2: GTIOCB
SLCDC0: SEG25
SSI0: SSIRXD"
"P115","58","CTSU0_TS35","Low","","Peripheral mode","CMOS","None","CTSU0: TS35
GPT4: GTIOCA
SLCDC0: SEG26
SSI0: SSITXD"
"P200","40","","","","Disabled","","","IRQ0: NMI"
"P201","39","","","","Disabled","","",""
"P202","35","","","","Disabled","","","GPT5: GTIOCB
SCI2: SCK
SCI9: RXD_MISO
SCI9: SCL
SLCDC0: SEG16
SPI1: MISO"
"P203","34","","","","Disabled","","","CTSU0: TSCAP
GPT5: GTIOCA
SCI2: CTS_RTS_SS
SCI9: SDA
SCI9: TXD_MOSI
SLCDC0: SEG15
SPI1: MOSI"
"P204","33","","","","Disabled","","","AGT1: AGTIO
CAC0: CACREF
CTSU0: TS00
GPT4: GTIOCB
IIC0: SCL
OPS0: GTIW
SCI0: SCK
SCI9: SCK
SLCDC0: SEG14
SPI1: RSPCK
USBFS0: OVRCURB"
"P205","32","CTSU0_TSCAP","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO
CGC0: CLKOUT
CTSU0: TSCAP
GPT4: GTIOCA
IIC1: SCL
IRQ0: IRQ01
OPS0: GTIV
SCI0: SDA
SCI0: TXD_MOSI
SCI9: CTS_RTS_SS
SLCDC0: SEG13
SPI1: SSL0
USBFS0: OVRCURA"
"P206","31","","","","Disabled","","","CTSU0: TS01
IIC1: SDA
IRQ0: IRQ00
OPS0: GTIU
SCI0: RXD_MISO
SCI0: SCL
SLCDC0: SEG12
SPI1: SSL1
USBFS0: VBUSEN"
"P212","14","","","","Disabled","","","AGT1: AGTEE
CGC0: EXTAL
GPT0: GTIOCB
IRQ0: IRQ03
POEG1: GTETRG
SCI1: RXD_MISO
SCI1: SCL"
"P213","13","","","","Disabled","","","CGC0: XTAL
GPT0: GTIOCA
IRQ0: IRQ02
POEG0: GTETRG
SCI1: SDA
SCI1: TXD_MOSI"
"P214","11","","","","Disabled","","","CGC0: XCOUT"
"P215","10","","","","Disabled","","","CGC0: XCIN"
"P300","50","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK
DEBUG0: TCK
GPT0: GTIOCA
OPS0: GTOUUP
SPI1: SSL1"
"P301","49","SCI2_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO
CTSU0: TS09
GPT4: GTIOCB
IRQ0: IRQ06
OPS0: GTOULO
SCI2: RXD_MISO
SCI2: SCL
SCI9: CTS_RTS_SS
SLCDC0: COM5
SLCDC0: SEG01
SPI1: SSL2"
"P302","48","SCI2_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CTSU0: TS08
GPT4: GTIOCA
IRQ0: IRQ05
OPS0: GTOUUP
SCI2: SDA
SCI2: TXD_MOSI
SLCDC0: COM6
SLCDC0: SEG02
SPI1: SSL3"
"P303","47","","","","Disabled","","","CTSU0: TS02
GPT7: GTIOCB
SLCDC0: COM7
SLCDC0: SEG03"
"P304","44","","","","Disabled","","","CTSU0: TS11
GPT7: GTIOCA
IRQ0: IRQ09
SLCDC0: SEG20"
"P305","43","","","","Disabled","","","IRQ0: IRQ08
SLCDC0: SEG19"
"P306","42","","","","Disabled","","","SLCDC0: SEG18"
"P307","41","","","","Disabled","","","SLCDC0: SEG17"
"P400","1","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","AGT1: AGTIO
CAC0: CACREF
CTSU0: TS20
GPT6: GTIOCA
IIC0: SCL
IRQ0: IRQ00
SCI0: SCK
SCI1: SCK
SLCDC0: SEG04
SSI: AUDIO_CLK"
"P401","2","SCI1_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CAN0: CTX
CTSU0: TS19
GPT6: GTIOCB
IIC0: SDA
IRQ0: IRQ05
POEG0: GTETRG
SCI0: CTS_RTS_SS
SCI1: SDA
SCI1: TXD_MOSI
SLCDC0: SEG05"
"P402","3","SCI1_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO
AGT1: AGTIO
CAN0: CRX
CTSU0: TS18
IRQ0: IRQ04
RTC0: RTCIC0
SCI1: RXD_MISO
SCI1: SCL
SLCDC0: SEG06"
"P403","4","GPIO","Low","","Output mode (Initial Low)","CMOS","None","AGT0: AGTIO
AGT1: AGTIO
CTSU0: TS17
GPT3: GTIOCA
RTC0: RTCIC1
SCI1: CTS_RTS_SS
SSI0: SSISCK"
"P404","5","","","","Disabled","","","GPT3: GTIOCB
RTC0: RTCIC2
SSI0: SSIWS"
"P405","6","","","","Disabled","","","GPT1: GTIOCA
SSI0: SSITXD"
"P406","7","","","","Disabled","","","GPT1: GTIOCB
SSI0: SSIRXD"
"P407","25","USBFS0_VBUS","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG
AGT0: AGTIO
CTSU0: TS03
IIC0: SDA
RTC0: RTCOUT
SCI0: CTS_RTS_SS
SLCDC0: SEG11
SPI1: SSL3
USBFS0: VBUS"
"P408","24","","","","Disabled","","","CTSU0: TS04
GPT5: GTIOCB
IIC0: SCL
IRQ0: IRQ07
OPS0: GTOWLO
SCI1: CTS_RTS_SS
SCI9: RXD_MISO
SCI9: SCL
SLCDC0: SEG10
USBFS0: ID"
"P409","23","","","","Disabled","","","CTSU0: TS05
GPT5: GTIOCA
IRQ0: IRQ06
OPS0: GTOWUP
SCI9: SDA
SCI9: TXD_MOSI
SLCDC0: SEG09
USBFS0: EXICEN"
"P410","22","SCI0_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOB
CTSU0: TS06
GPT6: GTIOCB
IRQ0: IRQ05
OPS0: GTOVLO
SCI0: RXD_MISO
SCI0: SCL
SLCDC0: SEG08
SPI0: MISO"
"P411","21","SCI0_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOA
CTSU0: TS07
GPT6: GTIOCA
IRQ0: IRQ04
OPS0: GTOVUP
SCI0: SDA
SCI0: TXD_MOSI
SLCDC0: SEG07
SPI0: MOSI"
"P412","20","","","","Disabled","","","SCI0: SCK
SPI0: RSPCK"
"P413","19","","","","Disabled","","","SCI0: CTS_RTS_SS
SPI0: SSL0"
"P414","18","","","","Disabled","","","GPT0: GTIOCB
IRQ0: IRQ09
SPI0: SSL1"
"P415","17","","","","Disabled","","","GPT0: GTIOCA
IRQ0: IRQ08
SPI0: SSL2"
"P500","76","","","","Disabled","","","ADC0: AN16
AGT0: AGTOA
CMP0: CMPREF1
GPT2: GTIOCA
OPS0: GTIU
SLCDC0: SEG34
USBFS0: VBUSEN"
"P501","77","","","","Disabled","","","ADC0: AN17
AGT0: AGTOB
CMP0: CMPIN1
GPT2: GTIOCB
IRQ0: IRQ11
OPS0: GTIV
SCI1: SDA
SCI1: TXD_MOSI
SLCDC0: SEG35
USBFS0: OVRCURA"
"P502","78","","","","Disabled","","","ADC0: AN18
CMP0: CMPREF0
GPT3: GTIOCB
IRQ0: IRQ12
OPS0: GTIW
SCI1: RXD_MISO
SCI1: SCL
SLCDC0: SEG36
USBFS0: OVRCURB"
"P503","79","","","","Disabled","","","ADC0: AN23
CMP0: CMPIN0
SCI1: SCK
SLCDC0: SEG37
USBFS0: EXICEN"
"P504","80","","","","Disabled","","","ADC0: AN24
SCI1: CTS_RTS_SS
USBFS0: ID"
"P505","81","","","","Disabled","","","ADC0: AN25
IRQ0: IRQ14"
"P600","67","","","","Disabled","","","GPT6: GTIOCB
SCI9: SCK
SLCDC0: SEG33"
"P601","66","","","","Disabled","","","GPT6: GTIOCA
SCI9: RXD_MISO
SCI9: SCL
SLCDC0: SEG32"
"P602","65","","","","Disabled","","","GPT7: GTIOCB
SCI9: SDA
SCI9: TXD_MOSI
SLCDC0: SEG31"
"P603","64","","","","Disabled","","","GPT7: GTIOCA
SCI9: CTS_RTS_SS
SLCDC0: SEG30"
"P608","59","","","","Disabled","","","GPT4: GTIOCB
SLCDC0: SEG27"
"P609","60","","","","Disabled","","","GPT5: GTIOCA
SLCDC0: SEG28"
"P610","61","","","","Disabled","","","GPT5: GTIOCB
SLCDC0: SEG29"
"P708","16","","","","Disabled","","","SCI1: RXD_MISO
SCI1: SCL
SPI0: SSL3"
"P808","45","","","","Disabled","","","SLCDC0: SEG21"
"P809","46","","","","Disabled","","","SLCDC0: SEG22"
"P914","28","USBFS0_USBDP","","","Peripheral mode","","","USBFS0: USBDP"
"P915","27","USBFS0_USBDM","","","Peripheral mode","","","USBFS0: USBDM"
"RES","38","","","","","","",""
"VBAT","8","","","","","","",""
"VCC","15","","","","","","",""
"VCC","37","","","","","","",""
"VCC","82","","","","","","",""
"VCC","62","","","","","","",""
"VCCUSB","29","USBFS0_VCCUSB","","","","","",""
"VCCUSBLDO","30","USBFS0_VCCUSBLDO","","","","","",""
"VCL","9","","","","","","",""
"VSS","12","","","","","","",""
"VSS","36","","","","","","",""
"VSS","83","","","","","","",""
"VSS","63","","","","","","",""
"VSSUSB","26","USBFS0_VSSUSB","","","","","",""
1 Name Pin Function Drive Capacity IRQ Mode Output type Pull up Port Capabilities
2 AVCC0 88 ADC_AVCC0
3 AVSS0 89 ADC_AVSS0
4 P000 100 ADC0_AN00 Analog mode ADC0: AN00 CTSU0: TS21 IRQ0: IRQ06 OPAMP0: AMP+
5 P001 99 Disabled ADC0: AN01 CTSU0: TS22 IRQ0: IRQ07 OPAMP0: AMP-
6 P002 98 Disabled ADC0: AN02 IRQ0: IRQ02 OPAMP0: AMPO
7 P003 97 Disabled ADC0: AN03 OPAMP1: AMPO
8 P004 96 Disabled ADC0: AN04 IRQ0: IRQ03 OPAMP2: AMPO
9 P005 95 Disabled ADC0: AN11 IRQ0: IRQ10 OPAMP3: AMP+
10 P006 94 Disabled ADC0: AN12 OPAMP3: AMP-
11 P007 93 Disabled ADC0: AN13 OPAMP3: AMPO
12 P008 92 Disabled ADC0: AN14
13 P010 91 Disabled ADC: VREFH0 ADC0: AN05 CTSU0: TS30 OPAMP2: AMP-
14 P011 90 Disabled ADC: VREFL0 ADC0: AN06 CTSU0: TS31 IRQ0: IRQ15 OPAMP2: AMP+
15 P012 87 Disabled ADC: VREFH ADC0: AN07 OPAMP1: AMP-
16 P013 86 Disabled ADC: VREFL ADC0: AN08 OPAMP1: AMP+
17 P014 85 Disabled ADC0: AN09 DAC120: DA
18 P015 84 Disabled ADC0: AN10 CTSU0: TS28 IRQ0: IRQ07
19 P100 75 SPI0_MISO Low None Peripheral mode CMOS None ADC0: AN22 AGT0: AGTIO CMP0: CMPIN0 GPT5: GTIOCB IIC1: SCL IRQ0: IRQ02 KINT0: KRM0 POEG0: GTETRG SCI0: RXD_MISO SCI0: SCL SCI1: SCK SLCDC0: VL1 SPI0: MISO
20 P101 74 SPI0_MOSI Low None Peripheral mode CMOS None ADC0: AN21 AGT0: AGTEE CMP0: CMPREF0 GPT5: GTIOCA IIC1: SDA IRQ0: IRQ01 KINT0: KRM1 POEG1: GTETRG SCI0: SDA SCI0: TXD_MOSI SCI1: CTS_RTS_SS SLCDC0: VL2 SPI0: MOSI
21 P102 73 SPI0_RSPCK Low Peripheral mode CMOS None ADC0: ADTRG ADC0: AN20 AGT0: AGTO CAN0: CRX CMP0: CMPIN1 GPT2: GTIOCB KINT0: KRM2 OPS0: GTOWLO SCI0: SCK SCI2: SDA SCI2: TXD_MOSI SLCDC0: VL3 SPI0: RSPCK
22 P103 72 SPI0_SSL0 Low Peripheral mode CMOS None ADC0: AN19 CAN0: CTX CMP0: CMPREF1 GPT2: GTIOCA KINT0: KRM3 OPS0: GTOWUP SCI0: CTS_RTS_SS SLCDC0: VL4 SPI0: SSL0
23 P104 71 Disabled CTSU0: TS13 GPT1: GTIOCB IRQ0: IRQ01 KINT0: KRM4 POEG1: GTETRG SCI0: RXD_MISO SCI0: SCL SLCDC0: COM0 SPI0: SSL1
24 P105 70 GPIO IRQ0 Input mode None CTSU0: TS34 GPT1: GTIOCA IRQ0: IRQ00 KINT0: KRM5 POEG0: GTETRG SLCDC0: COM1 SPI0: SSL2
25 P106 69 GPIO Low Output mode (Initial Low) CMOS None GPT0: GTIOCB KINT0: KRM6 SLCDC0: COM2 SPI0: SSL3
26 P107 68 Disabled GPT0: GTIOCA KINT0: KRM7 SLCDC0: COM3
27 P108 51 DEBUG0_TMS Low Peripheral mode CMOS None DEBUG0: SWDIO DEBUG0: TMS GPT0: GTIOCB OPS0: GTOULO SCI9: CTS_RTS_SS SPI1: SSL0
28 P109 52 DEBUG0_TDO Low Peripheral mode CMOS None CAN0: CTX CGC0: CLKOUT CTSU0: TS10 DEBUG0: SWO DEBUG0: TDO GPT1: GTIOCA OPS0: GTOVUP SCI1: SCK SCI9: SDA SCI9: TXD_MOSI SLCDC0: SEG23 SPI1: MOSI
29 P110 53 DEBUG0_TDI Low None Peripheral mode CMOS None CAN0: CRX CMP0: VCOUT DEBUG0: TDI GPT1: GTIOCB IRQ0: IRQ03 OPS0: GTOVLO SCI2: CTS_RTS_SS SCI9: RXD_MISO SCI9: SCL SLCDC0: SEG24 SPI1: MISO
30 P111 54 Disabled CTSU0: TS12 GPT3: GTIOCA IRQ0: IRQ04 SCI2: SCK SCI9: SCK SLCDC0: CAPH SPI1: RSPCK
31 P112 55 Disabled CTSU0: TSCAP GPT3: GTIOCB SCI1: SCK SCI2: SDA SCI2: TXD_MOSI SLCDC0: CAPL SPI1: SSL0 SSI0: SSISCK
32 P113 56 Disabled CTSU0: TS27 GPT2: GTIOCA SLCDC0: COM4 SLCDC0: SEG00 SSI0: SSIWS
33 P114 57 Disabled CTSU0: TS29 GPT2: GTIOCB SLCDC0: SEG25 SSI0: SSIRXD
34 P115 58 CTSU0_TS35 Low Peripheral mode CMOS None CTSU0: TS35 GPT4: GTIOCA SLCDC0: SEG26 SSI0: SSITXD
35 P200 40 Disabled IRQ0: NMI
36 P201 39 Disabled
37 P202 35 Disabled GPT5: GTIOCB SCI2: SCK SCI9: RXD_MISO SCI9: SCL SLCDC0: SEG16 SPI1: MISO
38 P203 34 Disabled CTSU0: TSCAP GPT5: GTIOCA SCI2: CTS_RTS_SS SCI9: SDA SCI9: TXD_MOSI SLCDC0: SEG15 SPI1: MOSI
39 P204 33 Disabled AGT1: AGTIO CAC0: CACREF CTSU0: TS00 GPT4: GTIOCB IIC0: SCL OPS0: GTIW SCI0: SCK SCI9: SCK SLCDC0: SEG14 SPI1: RSPCK USBFS0: OVRCURB
40 P205 32 CTSU0_TSCAP Low None Peripheral mode CMOS None AGT1: AGTO CGC0: CLKOUT CTSU0: TSCAP GPT4: GTIOCA IIC1: SCL IRQ0: IRQ01 OPS0: GTIV SCI0: SDA SCI0: TXD_MOSI SCI9: CTS_RTS_SS SLCDC0: SEG13 SPI1: SSL0 USBFS0: OVRCURA
41 P206 31 Disabled CTSU0: TS01 IIC1: SDA IRQ0: IRQ00 OPS0: GTIU SCI0: RXD_MISO SCI0: SCL SLCDC0: SEG12 SPI1: SSL1 USBFS0: VBUSEN
42 P212 14 Disabled AGT1: AGTEE CGC0: EXTAL GPT0: GTIOCB IRQ0: IRQ03 POEG1: GTETRG SCI1: RXD_MISO SCI1: SCL
43 P213 13 Disabled CGC0: XTAL GPT0: GTIOCA IRQ0: IRQ02 POEG0: GTETRG SCI1: SDA SCI1: TXD_MOSI
44 P214 11 Disabled CGC0: XCOUT
45 P215 10 Disabled CGC0: XCIN
46 P300 50 DEBUG0_TCK Low Peripheral mode CMOS None DEBUG0: SWCLK DEBUG0: TCK GPT0: GTIOCA OPS0: GTOUUP SPI1: SSL1
47 P301 49 SCI2_RXD_MISO Low None Peripheral mode CMOS None AGT0: AGTIO CTSU0: TS09 GPT4: GTIOCB IRQ0: IRQ06 OPS0: GTOULO SCI2: RXD_MISO SCI2: SCL SCI9: CTS_RTS_SS SLCDC0: COM5 SLCDC0: SEG01 SPI1: SSL2
48 P302 48 SCI2_TXD_MOSI Low None Peripheral mode CMOS None CTSU0: TS08 GPT4: GTIOCA IRQ0: IRQ05 OPS0: GTOUUP SCI2: SDA SCI2: TXD_MOSI SLCDC0: COM6 SLCDC0: SEG02 SPI1: SSL3
49 P303 47 Disabled CTSU0: TS02 GPT7: GTIOCB SLCDC0: COM7 SLCDC0: SEG03
50 P304 44 Disabled CTSU0: TS11 GPT7: GTIOCA IRQ0: IRQ09 SLCDC0: SEG20
51 P305 43 Disabled IRQ0: IRQ08 SLCDC0: SEG19
52 P306 42 Disabled SLCDC0: SEG18
53 P307 41 Disabled SLCDC0: SEG17
54 P400 1 GPIO Low None Output mode (Initial Low) CMOS None AGT1: AGTIO CAC0: CACREF CTSU0: TS20 GPT6: GTIOCA IIC0: SCL IRQ0: IRQ00 SCI0: SCK SCI1: SCK SLCDC0: SEG04 SSI: AUDIO_CLK
55 P401 2 SCI1_TXD_MOSI Low None Peripheral mode CMOS None CAN0: CTX CTSU0: TS19 GPT6: GTIOCB IIC0: SDA IRQ0: IRQ05 POEG0: GTETRG SCI0: CTS_RTS_SS SCI1: SDA SCI1: TXD_MOSI SLCDC0: SEG05
56 P402 3 SCI1_RXD_MISO Low None Peripheral mode CMOS None AGT0: AGTIO AGT1: AGTIO CAN0: CRX CTSU0: TS18 IRQ0: IRQ04 RTC0: RTCIC0 SCI1: RXD_MISO SCI1: SCL SLCDC0: SEG06
57 P403 4 GPIO Low Output mode (Initial Low) CMOS None AGT0: AGTIO AGT1: AGTIO CTSU0: TS17 GPT3: GTIOCA RTC0: RTCIC1 SCI1: CTS_RTS_SS SSI0: SSISCK
58 P404 5 Disabled GPT3: GTIOCB RTC0: RTCIC2 SSI0: SSIWS
59 P405 6 Disabled GPT1: GTIOCA SSI0: SSITXD
60 P406 7 Disabled GPT1: GTIOCB SSI0: SSIRXD
61 P407 25 USBFS0_VBUS Low Peripheral mode CMOS None ADC0: ADTRG AGT0: AGTIO CTSU0: TS03 IIC0: SDA RTC0: RTCOUT SCI0: CTS_RTS_SS SLCDC0: SEG11 SPI1: SSL3 USBFS0: VBUS
62 P408 24 Disabled CTSU0: TS04 GPT5: GTIOCB IIC0: SCL IRQ0: IRQ07 OPS0: GTOWLO SCI1: CTS_RTS_SS SCI9: RXD_MISO SCI9: SCL SLCDC0: SEG10 USBFS0: ID
63 P409 23 Disabled CTSU0: TS05 GPT5: GTIOCA IRQ0: IRQ06 OPS0: GTOWUP SCI9: SDA SCI9: TXD_MOSI SLCDC0: SEG09 USBFS0: EXICEN
64 P410 22 SCI0_RXD_MISO Low None Peripheral mode CMOS None AGT1: AGTOB CTSU0: TS06 GPT6: GTIOCB IRQ0: IRQ05 OPS0: GTOVLO SCI0: RXD_MISO SCI0: SCL SLCDC0: SEG08 SPI0: MISO
65 P411 21 SCI0_TXD_MOSI Low None Peripheral mode CMOS None AGT1: AGTOA CTSU0: TS07 GPT6: GTIOCA IRQ0: IRQ04 OPS0: GTOVUP SCI0: SDA SCI0: TXD_MOSI SLCDC0: SEG07 SPI0: MOSI
66 P412 20 Disabled SCI0: SCK SPI0: RSPCK
67 P413 19 Disabled SCI0: CTS_RTS_SS SPI0: SSL0
68 P414 18 Disabled GPT0: GTIOCB IRQ0: IRQ09 SPI0: SSL1
69 P415 17 Disabled GPT0: GTIOCA IRQ0: IRQ08 SPI0: SSL2
70 P500 76 Disabled ADC0: AN16 AGT0: AGTOA CMP0: CMPREF1 GPT2: GTIOCA OPS0: GTIU SLCDC0: SEG34 USBFS0: VBUSEN
71 P501 77 Disabled ADC0: AN17 AGT0: AGTOB CMP0: CMPIN1 GPT2: GTIOCB IRQ0: IRQ11 OPS0: GTIV SCI1: SDA SCI1: TXD_MOSI SLCDC0: SEG35 USBFS0: OVRCURA
72 P502 78 Disabled ADC0: AN18 CMP0: CMPREF0 GPT3: GTIOCB IRQ0: IRQ12 OPS0: GTIW SCI1: RXD_MISO SCI1: SCL SLCDC0: SEG36 USBFS0: OVRCURB
73 P503 79 Disabled ADC0: AN23 CMP0: CMPIN0 SCI1: SCK SLCDC0: SEG37 USBFS0: EXICEN
74 P504 80 Disabled ADC0: AN24 SCI1: CTS_RTS_SS USBFS0: ID
75 P505 81 Disabled ADC0: AN25 IRQ0: IRQ14
76 P600 67 Disabled GPT6: GTIOCB SCI9: SCK SLCDC0: SEG33
77 P601 66 Disabled GPT6: GTIOCA SCI9: RXD_MISO SCI9: SCL SLCDC0: SEG32
78 P602 65 Disabled GPT7: GTIOCB SCI9: SDA SCI9: TXD_MOSI SLCDC0: SEG31
79 P603 64 Disabled GPT7: GTIOCA SCI9: CTS_RTS_SS SLCDC0: SEG30
80 P608 59 Disabled GPT4: GTIOCB SLCDC0: SEG27
81 P609 60 Disabled GPT5: GTIOCA SLCDC0: SEG28
82 P610 61 Disabled GPT5: GTIOCB SLCDC0: SEG29
83 P708 16 Disabled SCI1: RXD_MISO SCI1: SCL SPI0: SSL3
84 P808 45 Disabled SLCDC0: SEG21
85 P809 46 Disabled SLCDC0: SEG22
86 P914 28 USBFS0_USBDP Peripheral mode USBFS0: USBDP
87 P915 27 USBFS0_USBDM Peripheral mode USBFS0: USBDM
88 RES 38
89 VBAT 8
90 VCC 15
91 VCC 37
92 VCC 82
93 VCC 62
94 VCCUSB 29 USBFS0_VCCUSB
95 VCCUSBLDO 30 USBFS0_VCCUSBLDO
96 VCL 9
97 VSS 12
98 VSS 36
99 VSS 83
100 VSS 63
101 VSSUSB 26 USBFS0_VSSUSB

21
ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_clock_cfg.h Normal file
View File

@ -0,0 +1,21 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
#endif /* BSP_CLOCK_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_pin_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef BSP_PIN_CFG_H_
#define BSP_PIN_CFG_H_
#include "bsp_api.h"
#include "r_ioport_api.h"
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */
#endif /* BSP_PIN_CFG_H_ */

7
ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.c Normal file
View File

@ -0,0 +1,7 @@
/* generated common source file - do not edit */
#include "common_data.h"
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
void g_common_init(void) {
}

16
ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.h Normal file
View File

@ -0,0 +1,16 @@
/* generated common header file - do not edit */
#ifndef COMMON_DATA_H_
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

471
ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.c Normal file
View File

@ -0,0 +1,471 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
adc_instance_ctrl_t g_adc0_ctrl;
const adc_extended_cfg_t g_adc0_cfg_extend =
{ .add_average_count = ADC_ADD_OFF,
.clearing = ADC_CLEAR_AFTER_READ_ON,
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
const adc_cfg_t g_adc0_cfg =
{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment =
(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
#else
.scan_end_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
#else
.scan_end_b_irq = FSP_INVALID_VECTOR,
#endif
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
const adc_channel_cfg_t g_adc0_channel_cfg =
{ .scan_mask = 0,
.scan_mask_group_b = 0,
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
.add_mask = 0,
.sample_hold_mask = 0,
.sample_hold_states = 24, };
/* Instance structure to use this module. */
const adc_instance_t g_adc0 =
{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
lpm_instance_ctrl_t g_lpm0_ctrl;
const lpm_cfg_t g_lpm0_cfg =
{ .low_power_mode = LPM_MODE_SLEEP,
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
.snooze_end_sources = (lpm_snooze_end_t)0,
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
.output_port_enable = 0,
#endif
#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY
.io_port_state = 0,
.power_supply_state = 0,
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
#endif
.p_extend = NULL, };
const lpm_instance_t g_lpm0 =
{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
dtc_instance_ctrl_t g_transfer1_ctrl;
transfer_info_t g_transfer1_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer1_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
const transfer_cfg_t g_transfer1_cfg =
{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer1 =
{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
dtc_instance_ctrl_t g_transfer0_ctrl;
transfer_info_t g_transfer0_info =
{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
.irq = TRANSFER_IRQ_END,
.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
.size = TRANSFER_SIZE_2_BYTE,
.mode = TRANSFER_MODE_NORMAL,
.p_dest = (void *)NULL,
.p_src = (void const *)NULL,
.num_blocks = 0,
.length = 0, };
const dtc_extended_cfg_t g_transfer0_cfg_extend =
{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
const transfer_cfg_t g_transfer0_cfg =
{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
/* Instance structure to use this module. */
const transfer_instance_t g_transfer0 =
{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
spi_instance_ctrl_t g_spi0_ctrl;
/** SPI extended configuration for SPI HAL driver */
const spi_extended_cfg_t g_spi0_ext_cfg =
{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
.ssl_polarity = SPI_SSLP_LOW,
.ssl_select = SPI_SSL_SELECT_SSL0,
.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
.parity = SPI_PARITY_MODE_DISABLE,
.byte_swap = SPI_BYTE_SWAP_DISABLE,
.spck_div =
{
/* Actual calculated bitrate: 12000000. */ .spbr = 1,
.brdv = 0
},
.spck_delay = SPI_DELAY_COUNT_1,
.ssl_negation_delay = SPI_DELAY_COUNT_1,
.next_access_delay = SPI_DELAY_COUNT_1 };
/** SPI configuration for SPI HAL driver */
const spi_cfg_t g_spi0_cfg =
{ .channel = 0,
#if defined(VECTOR_NUMBER_SPI0_RXI)
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TXI)
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_TEI)
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SPI0_ERI)
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
.operating_mode = SPI_MODE_MASTER,
.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
.clk_polarity = SPI_CLK_POLARITY_LOW,
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
.bit_order = SPI_BIT_ORDER_MSB_FIRST,
.p_transfer_tx = g_spi0_P_TRANSFER_TX,
.p_transfer_rx = g_spi0_P_TRANSFER_RX,
.p_callback = spi_callback,
.p_context = NULL,
.p_extend = (void *)&g_spi0_ext_cfg, };
/* Instance structure to use this module. */
const spi_instance_t g_spi0 =
{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
icu_instance_ctrl_t g_external_irq0_ctrl;
const external_irq_cfg_t g_external_irq0_cfg =
{ .channel = 0,
.trigger = EXTERNAL_IRQ_TRIG_RISING,
.filter_enable = false,
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
.p_callback = callback_icu,
.p_context = NULL,
.p_extend = NULL,
.ipl = (12),
#if defined(VECTOR_NUMBER_ICU_IRQ0)
.irq = VECTOR_NUMBER_ICU_IRQ0,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const external_irq_instance_t g_external_irq0 =
{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
agt_instance_ctrl_t g_timer0_ctrl;
const agt_extended_cfg_t g_timer0_extend =
{ .count_source = AGT_CLOCK_PCLKB,
.agto = AGT_PIN_CFG_DISABLED,
.agtoa = AGT_PIN_CFG_DISABLED,
.agtob = AGT_PIN_CFG_DISABLED,
.measurement_mode = AGT_MEASURE_DISABLED,
.agtio_filter = AGT_AGTIO_FILTER_NONE,
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
const timer_cfg_t g_timer0_cfg =
{ .mode = TIMER_MODE_PERIODIC,
/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
/** If NULL then do not add & */
#if defined(NULL)
.p_context = NULL,
#else
.p_context = &NULL,
#endif
.p_extend = &g_timer0_extend,
.cycle_end_ipl = (5),
#if defined(VECTOR_NUMBER_AGT0_INT)
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
#else
.cycle_end_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const timer_instance_t g_timer0 =
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
flash_lp_instance_ctrl_t g_flash0_ctrl;
const flash_cfg_t g_flash0_cfg =
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED),
#if defined(VECTOR_NUMBER_FCU_FRDYI)
.irq = VECTOR_NUMBER_FCU_FRDYI,
#else
.irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const flash_instance_t g_flash0 =
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp };
rtc_instance_ctrl_t g_rtc0_ctrl;
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
.adjustment_value = 0, };
const rtc_cfg_t g_rtc0_cfg =
{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
NULL,
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
#if defined(VECTOR_NUMBER_RTC_ALARM)
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
#else
.alarm_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_PERIOD)
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
#else
.periodic_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_RTC_CARRY)
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
#else
.carry_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const rtc_instance_t g_rtc0 =
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
sci_uart_instance_ctrl_t g_uart2_ctrl;
baud_setting_t g_uart2_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart2_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart2_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart2_cfg =
{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart2_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI2_RXI)
.rxi_irq = VECTOR_NUMBER_SCI2_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_TXI)
.txi_irq = VECTOR_NUMBER_SCI2_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_TEI)
.tei_irq = VECTOR_NUMBER_SCI2_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI2_ERI)
.eri_irq = VECTOR_NUMBER_SCI2_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart2 =
{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart1_ctrl;
baud_setting_t g_uart1_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart1_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart1_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart1_cfg =
{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart1_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI1_RXI)
.rxi_irq = VECTOR_NUMBER_SCI1_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TXI)
.txi_irq = VECTOR_NUMBER_SCI1_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_TEI)
.tei_irq = VECTOR_NUMBER_SCI1_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI1_ERI)
.eri_irq = VECTOR_NUMBER_SCI1_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart1 =
{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci };
sci_uart_instance_ctrl_t g_uart0_ctrl;
baud_setting_t g_uart0_baud_setting =
{
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
{ .clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart0_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart0_cfg =
{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
user_uart_callback,
.p_context = NULL, .p_extend = &g_uart0_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI0_RXI)
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TXI)
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TEI)
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_ERI)
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart0 =
{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci };
void g_hal_init(void) {
g_common_init();
}

154
ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.h Normal file
View File

@ -0,0 +1,154 @@
/* generated HAL header file - do not edit */
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_adc.h"
#include "r_adc_api.h"
#include "r_lpm.h"
#include "r_lpm_api.h"
#include "r_dtc.h"
#include "r_transfer_api.h"
#include "r_spi.h"
#include "r_icu.h"
#include "r_external_irq_api.h"
#include "r_agt.h"
#include "r_timer_api.h"
#include "r_flash_lp.h"
#include "r_flash_api.h"
#include "r_rtc.h"
#include "r_rtc_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** ADC on ADC Instance. */
extern const adc_instance_t g_adc0;
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
extern adc_instance_ctrl_t g_adc0_ctrl;
extern const adc_cfg_t g_adc0_cfg;
extern const adc_channel_cfg_t g_adc0_channel_cfg;
#ifndef NULL
void NULL(adc_callback_args_t *p_args);
#endif
/** lpm Instance */
extern const lpm_instance_t g_lpm0;
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
extern lpm_instance_ctrl_t g_lpm0_ctrl;
extern const lpm_cfg_t g_lpm0_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer1;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer1_ctrl;
extern const transfer_cfg_t g_transfer1_cfg;
/* Transfer on DTC Instance. */
extern const transfer_instance_t g_transfer0;
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
extern dtc_instance_ctrl_t g_transfer0_ctrl;
extern const transfer_cfg_t g_transfer0_cfg;
/** SPI on SPI Instance. */
extern const spi_instance_t g_spi0;
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
extern spi_instance_ctrl_t g_spi0_ctrl;
extern const spi_cfg_t g_spi0_cfg;
/** Callback used by SPI Instance. */
#ifndef spi_callback
void spi_callback(spi_callback_args_t *p_args);
#endif
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == g_transfer0)
#define g_spi0_P_TRANSFER_TX (NULL)
#else
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
#endif
#if (RA_NOT_DEFINED == g_transfer1)
#define g_spi0_P_TRANSFER_RX (NULL)
#else
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
#endif
#undef RA_NOT_DEFINED
/** External IRQ on ICU Instance. */
extern const external_irq_instance_t g_external_irq0;
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
extern icu_instance_ctrl_t g_external_irq0_ctrl;
extern const external_irq_cfg_t g_external_irq0_cfg;
#ifndef callback_icu
void callback_icu(external_irq_callback_args_t *p_args);
#endif
/** AGT Timer Instance */
extern const timer_instance_t g_timer0;
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
extern agt_instance_ctrl_t g_timer0_ctrl;
extern const timer_cfg_t g_timer0_cfg;
#ifndef callback_agt
void callback_agt(timer_callback_args_t *p_args);
#endif
/* Flash on Flash LP Instance. */
extern const flash_instance_t g_flash0;
/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */
extern flash_lp_instance_ctrl_t g_flash0_ctrl;
extern const flash_cfg_t g_flash0_cfg;
#ifndef NULL
void NULL(flash_callback_args_t *p_args);
#endif
/* RTC Instance. */
extern const rtc_instance_t g_rtc0;
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
extern rtc_instance_ctrl_t g_rtc0_ctrl;
extern const rtc_cfg_t g_rtc0_cfg;
#ifndef NULL
void NULL(rtc_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart2;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart2_ctrl;
extern const uart_cfg_t g_uart2_cfg;
extern const sci_uart_extended_cfg_t g_uart2_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart1;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart1_ctrl;
extern const uart_cfg_t g_uart1_cfg;
extern const sci_uart_extended_cfg_t g_uart1_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart0;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart0_ctrl;
extern const uart_cfg_t g_uart0_cfg;
extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t *p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

6
ports/renesas-ra/boards/RA4M1_EK/ra_gen/main.c Normal file
View File

@ -0,0 +1,6 @@
/* generated main source file - do not edit */
#include "hal_data.h"
int main(void) {
hal_entry();
return 0;
}

105
ports/renesas-ra/boards/RA4M1_EK/ra_gen/pin_data.c Normal file
View File

@ -0,0 +1,105 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_00_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE),
},
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI),
},
{
.pin = BSP_IO_PORT_01_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT),
},
{
.pin = BSP_IO_PORT_01_PIN_06,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_01_PIN_08,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_01_PIN_15,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_02_PIN_05,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU),
},
{
.pin = BSP_IO_PORT_03_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG),
},
{
.pin = BSP_IO_PORT_03_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_03_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_00,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_01,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_02,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9),
},
{
.pin = BSP_IO_PORT_04_PIN_03,
.pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW),
},
{
.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
{
.pin = BSP_IO_PORT_04_PIN_10,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_04_PIN_11,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8),
},
{
.pin = BSP_IO_PORT_09_PIN_14,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
{
.pin = BSP_IO_PORT_09_PIN_15,
.pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS),
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
};

53
ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.c Normal file
View File

@ -0,0 +1,53 @@
/* generated vector source file - do not edit */
#include "bsp_api.h"
/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
#if VECTOR_DATA_IRQ_COUNT > 0
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
{
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */
[2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */
[3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */
[4] = sci_uart_rxi_isr, /* SCI1 RXI (Received data full) */
[5] = sci_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */
[6] = sci_uart_tei_isr, /* SCI1 TEI (Transmit end) */
[7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */
[8] = sci_uart_rxi_isr, /* SCI2 RXI (Received data full) */
[9] = sci_uart_txi_isr, /* SCI2 TXI (Transmit data empty) */
[10] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */
[11] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
[16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */
[17] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
[18] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
[19] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
[20] = spi_eri_isr, /* SPI0 ERI (Error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
[0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */
[1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */
[2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */
[3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */
[4] = BSP_PRV_IELS_ENUM(EVENT_SCI1_RXI), /* SCI1 RXI (Received data full) */
[5] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TXI), /* SCI1 TXI (Transmit data empty) */
[6] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TEI), /* SCI1 TEI (Transmit end) */
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */
[8] = BSP_PRV_IELS_ENUM(EVENT_SCI2_RXI), /* SCI2 RXI (Received data full) */
[9] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TXI), /* SCI2 TXI (Transmit data empty) */
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
[16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */
[17] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
[18] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
[19] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
[20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
};
#endif

79
ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.h Normal file
View File

@ -0,0 +1,79 @@
/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (21)
#endif
/* ISR prototypes */
void sci_uart_rxi_isr(void);
void sci_uart_txi_isr(void);
void sci_uart_tei_isr(void);
void sci_uart_eri_isr(void);
void rtc_alarm_periodic_isr(void);
void rtc_carry_isr(void);
void agt_int_isr(void);
void r_icu_isr(void);
void spi_rxi_isr(void);
void spi_txi_isr(void);
void spi_tei_isr(void);
void spi_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */
#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */
#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */
#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */
#define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)8) /* SCI2 RXI (Received data full) */
#define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)11) /* SCI2 ERI (Receive error) */
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)20) /* SPI0 ERI (Error) */
typedef enum IRQn
{
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */
SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */
SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */
SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */
SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */
SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */
SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */
SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */
SCI2_RXI_IRQn = 8, /* SCI2 RXI (Received data full) */
SCI2_TXI_IRQn = 9, /* SCI2 TXI (Transmit data empty) */
SCI2_TEI_IRQn = 10, /* SCI2 TEI (Transmit end) */
SCI2_ERI_IRQn = 11, /* SCI2 ERI (Receive error) */
RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */
RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */
RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */
AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */
ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */
SPI0_RXI_IRQn = 17, /* SPI0 RXI (Receive buffer full) */
SPI0_TXI_IRQn = 18, /* SPI0 TXI (Transmit buffer empty) */
SPI0_TEI_IRQn = 19, /* SPI0 TEI (Transmission complete event) */
SPI0_ERI_IRQn = 20, /* SPI0 ERI (Error) */
} IRQn_Type;
#endif /* VECTOR_DATA_H */

58
ports/renesas-ra/boards/RA4M1_EK/src/hal_entry.c Normal file
View File

@ -0,0 +1,58 @@
#include "hal_data.h"
FSP_CPP_HEADER
void R_BSP_WarmStart(bsp_warm_start_event_t event);
FSP_CPP_FOOTER
void ra_main(uint32_t reset_mode);
/*******************************************************************************************************************//**
* main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function
* is called by main() when no RTOS is used.
**********************************************************************************************************************/
void hal_entry(void) {
/* TODO: add your own code here */
ra_main(1);
#if BSP_TZ_SECURE_BUILD
/* Enter non-secure code */
R_BSP_NonSecureEnter();
#endif
}
/*******************************************************************************************************************//**
* This function is called at various points during the startup process. This implementation uses the event that is
* called right before main() to set up the pins.
*
* @param[in] event Where at in the start up process the code is currently at
**********************************************************************************************************************/
void R_BSP_WarmStart(bsp_warm_start_event_t event) {
if (BSP_WARM_START_RESET == event) {
#if BSP_FEATURE_FLASH_LP_VERSION != 0
/* Enable reading from data flash. */
R_FACI_LP->DFLCTL = 1U;
/* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
* C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
#endif
}
if (BSP_WARM_START_POST_C == event) {
/* C runtime environment and system clocks are setup. */
/* Configure pins. */
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
}
}
#if BSP_TZ_SECURE_BUILD
BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable();
/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */
BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() {
}
#endif

21
ports/renesas-ra/boards/RA4W1_EK/board.json Normal file
View File

@ -0,0 +1,21 @@
{
"deploy": [
"../deploy.md"
],
"docs": "",
"features": [
"UART",
"SPI",
"I2C",
"ADC"
],
"id": "EK-RA4W1",
"images": [
"ek_ra4w1_board.jpg"
],
"mcu": "RA4W1",
"product": "EK-RA4W1",
"thumbnail": "",
"url": "https://www.renesas.com/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4w1-evaluation-kit-ra4w1-mcu-group",
"vendor": "Renesas Electronics"
}

70
ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.h Normal file
View File

@ -0,0 +1,70 @@
// MCU config
#define MICROPY_HW_BOARD_NAME "RA4W1_EK"
#define MICROPY_HW_MCU_NAME "RA4W1"
#define MICROPY_HW_MCU_SYSCLK 48000000
#define MICROPY_HW_MCU_PCLK 48000000
// module config
#define MICROPY_EMIT_THUMB (1)
#define MICROPY_EMIT_INLINE_THUMB (1)
#define MICROPY_PY_BUILTINS_COMPLEX (1)
#define MICROPY_PY_GENERATOR_PEND_THROW (1)
#define MICROPY_PY_MATH (1)
#define MICROPY_PY_UHEAPQ (1)
#define MICROPY_PY_UTIMEQ (1)
#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only
// peripheral config
#define MICROPY_HW_ENABLE_RTC (1)
#define MICROPY_HW_RTC_SOURCE (1) // 0: subclock, 1: LOCO (32.768khz)
#define MICROPY_HW_ENABLE_ADC (1)
#define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
// board config
// UART
// #define MICROPY_HW_UART0_TX (pin_P101) // Disable (Conflict with PMOD)
// #define MICROPY_HW_UART0_RX (pin_P100) // Disable (Conflict with PMOD)
// #define MICROPY_HW_UART0_CTS (pin_P103) // Disable (Conflict with PMOD)
#define MICROPY_HW_UART1_TX (pin_P213)
#define MICROPY_HW_UART1_RX (pin_P212)
// #define MICROPY_HW_UART1_CTS (pin_P101) // Disable (Conflict with PMOD)
#define MICROPY_HW_UART4_TX (pin_P205) // REPL
#define MICROPY_HW_UART4_RX (pin_P206) // REPL
// #define MICROPY_HW_UART4_CTS (pin_P407) // Conflict with PMOD1-IO1
#define MICROPY_HW_UART9_TX (pin_P109)
#define MICROPY_HW_UART9_RX (pin_P110)
// #define MICROPY_HW_UART9_CTS (pin_P108) // NC
#define MICROPY_HW_UART_REPL HW_UART_4
#define MICROPY_HW_UART_REPL_BAUD 115200
// I2C
#define MICROPY_HW_I2C0_SCL (pin_P204) // Note that conflict with PMOD IO0
#define MICROPY_HW_I2C0_SDA (pin_P407) // Note that conflict with PMOD IO1
// #define MICROPY_HW_I2C1_SCL (pin_P100) // Disable (Conflict with SPI0)
// #define MICROPY_HW_I2C1_SDA (pin_P101) // Disable (Conflict with SPI0)
// SPI
#define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD
#define MICROPY_HW_SPI0_RSPCK (pin_P102) // PMOD
#define MICROPY_HW_SPI0_MISO (pin_P100) // PMOD
#define MICROPY_HW_SPI0_MOSI (pin_P101) // PMOD
// #define MICROPY_HW_SPI1_SSL (pin_P108) // Disable (vector not registered)
// #define MICROPY_HW_SPI1_RSPCK (pin_P111) // Disable (vector not registered)
// #define MICROPY_HW_SPI1_MISO (pin_P110) // Disable (vector not registered)
// #define MICROPY_HW_SPI1_MOSI (pin_P109) // Disable (vector not registered)
// Switch
#define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_USRSW_PIN (pin_P402)
#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING)
#define MICROPY_HW_USRSW_PRESSED (0)
// LEDs
#define MICROPY_HW_LED1 (pin_P106)
#define MICROPY_HW_LED2 (pin_P404)
#define MICROPY_HW_LED_ON(pin) mp_hal_pin_low(pin)
#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_high(pin)
#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin)

6
ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.mk Normal file
View File

@ -0,0 +1,6 @@
CMSIS_MCU = RA4W1
MCU_SERIES = m4
LD_FILES = boards/RA4W1_EK/ra4w1_ek.ld
# MicroPython settings
MICROPY_VFS_FAT = 1

67
ports/renesas-ra/boards/RA4W1_EK/pins.csv Normal file
View File

@ -0,0 +1,67 @@
P004,P004
P010,P010
P011,P011
P014,P014
P015,P015
P100,P100
P101,P101
P102,P102
P103,P103
P104,P104
P105,P105
P106,P106
P107,P107
P108,P108
P109,P109
P110,P110
P111,P111
P200,P200
P201,P201
P204,P204
P205,P205
P206,P206
P212,P212
P213,P213
P214,P214
P215,P215
P300,P300
P402,P402
P404,P404
P407,P407
P409,P409
P414,P414
P501,P501
P914,P914
P915,P915
A0,P004
A1,P014
A2,P015
A3,P501
A4,P101
A5,P100
SDA1,P101
SCL1,P100
SCK,P204
SDA,P407
D13,P102
D12,P100
D11,P101
D10,P103
D9,P104
D8,P106
D7,P212
D6,P213
D5,P414
D4,P409
D3,P105
D2,P111
D1,P109
D0,P110
SWDIO,P108
SWO,P109
TDI,P110
MD,P201
SWCLK,P300
SW1,P402
LED1,P106
LED2,P404
1 P004 P004
2 P010 P010
3 P011 P011
4 P014 P014
5 P015 P015
6 P100 P100
7 P101 P101
8 P102 P102
9 P103 P103
10 P104 P104
11 P105 P105
12 P106 P106
13 P107 P107
14 P108 P108
15 P109 P109
16 P110 P110
17 P111 P111
18 P200 P200
19 P201 P201
20 P204 P204
21 P205 P205
22 P206 P206
23 P212 P212
24 P213 P213
25 P214 P214
26 P215 P215
27 P300 P300
28 P402 P402
29 P404 P404
30 P407 P407
31 P409 P409
32 P414 P414
33 P501 P501
34 P914 P914
35 P915 P915
36 A0 P004
37 A1 P014
38 A2 P015
39 A3 P501
40 A4 P101
41 A5 P100
42 SDA1 P101
43 SCL1 P100
44 SCK P204
45 SDA P407
46 D13 P102
47 D12 P100
48 D11 P101
49 D10 P103
50 D9 P104
51 D8 P106
52 D7 P212
53 D6 P213
54 D5 P414
55 D4 P409
56 D3 P105
57 D2 P111
58 D1 P109
59 D0 P110
60 SWDIO P108
61 SWO P109
62 TDI P110
63 MD P201
64 SWCLK P300
65 SW1 P402
66 LED1 P106
67 LED2 P404

298
ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek.ld Normal file
View File

@ -0,0 +1,298 @@
/*
Linker File for RA4W1 MCU
*/
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512KB */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 /* 96KB */
DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */
ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */
}
/* Library configurations */
/*GROUP(libgcc.a libc.a libm.a libnosys.a) */
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
_stext = .;
__ROM_Start = .;
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
* space because ROM registers are at address 0x400 and there is very little space
* in between. */
KEEP(*(.fixed_vectors*))
KEEP(*(.application_vectors*))
__Vectors_End = .;
__end__ = .;
/* ROM Registers start at address 0x00000400 */
. = __ROM_Start + 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = __ROM_Start + 0x500;
*(.text*)
KEEP(*(.version))
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
__usb_dev_descriptor_start_fs = .;
KEEP(*(.usb_device_desc_fs*))
__usb_cfg_descriptor_start_fs = .;
KEEP(*(.usb_config_desc_fs*))
__usb_interface_descriptor_start_fs = .;
KEEP(*(.usb_interface_desc_fs*))
__usb_descriptor_end_fs = .;
__usb_dev_descriptor_start_hs = .;
KEEP(*(.usb_device_desc_hs*))
__usb_cfg_descriptor_start_hs = .;
KEEP(*(.usb_config_desc_hs*))
__usb_interface_descriptor_start_hs = .;
KEEP(*(.usb_interface_desc_hs*))
__usb_descriptor_end_hs = .;
KEEP(*(.eh_frame*))
__ROM_End = .;
_etext = .;
} > FLASH = 0xFF
__Vectors_Size = __Vectors_End - __Vectors;
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
.fsp_dtc_vector_table (NOLOAD) :
{
. = ORIGIN(RAM);
*(.fsp_dtc_vector_table)
} > RAM
/* Initialized data section. */
.data :
{
_sidata = .;
_sdata = .;
__data_start__ = .;
*(vtable)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM AT > FLASH
.noinit (NOLOAD):
{
. = ALIGN(4);
__noinit_start = .;
KEEP(*(.noinit*))
__noinit_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (NOLOAD):
{
. = ALIGN(8);
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* Stacks are stored in this section. */
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
__StackLimit = .;
/* Main stack */
KEEP(*(.stack))
__StackTop = .;
/* Thread stacks */
KEEP(*(.stack*))
__StackTopAll = .;
_estack = .;
} > RAM
PROVIDE(__stack = __StackTopAll);
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
at run time for things such as ThreadX memory pool allocations. */
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
/* Data flash. */
.data_flash :
{
__Data_Flash_Start = .;
KEEP(*(.data_flash*))
__Data_Flash_End = .;
} > DATA_FLASH
.id_code :
{
__ID_Code_Start = .;
KEEP(*(.id_code*))
__ID_Code_End = .;
} > ID_CODE
}
/* produce a link error if there is not this amount of RAM for these sections */
/* _minimum_stack_size = 2K; */
/* _minimum_heap_size = 16K; */
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = __HeapBase; /* heap starts just after statically allocated memory */
_heap_end = __HeapLimit; /* tunable */

30
ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek_conf.h Normal file
View File

@ -0,0 +1,30 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Renesas Electronics Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef RA4M1_EK_CONF_H
#define RA4M1_EK_CONF_H
#define DEBUG_CH 0
#endif /* RA4M1_EK_CONF_H */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
#include "../../../ra/board/ra4w1_ek/board.h"
#endif /* BOARD_CFG_H_ */

49
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h Normal file
View File

@ -0,0 +1,49 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
#ifndef BSP_CFG_RTOS
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (2)
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (1)
#else
#define BSP_CFG_RTOS (0)
#endif
#endif
#undef RA_NOT_DEFINED
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x4000)
#define BSP_CFG_HEAP_BYTES (0xf000)
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
#define BSP_CFG_ASSERT (0)
#define BSP_CFG_ERROR_LOG (0)
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#endif /* BSP_CFG_H_ */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_CFG_H_
#define BSP_MCU_DEVICE_CFG_H_
#define BSP_CFG_MCU_PART_SERIES (4)
#endif /* BSP_MCU_DEVICE_CFG_H_ */

10
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h Normal file
View File

@ -0,0 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA4W1AD2CNG
#define BSP_ROM_SIZE_BYTES (524288)
#define BSP_RAM_SIZE_BYTES (98304)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
#define BSP_PACKAGE_QFN
#define BSP_PACKAGE_PINS (56)
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

74
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h Normal file
View File

@ -0,0 +1,74 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
#define BSP_MCU_GROUP_RA4W1 (1)
#define BSP_LOCO_HZ (32768)
#define BSP_MOCO_HZ (8000000)
#define BSP_SUB_CLOCK_HZ (32768)
#if BSP_CFG_HOCO_FREQUENCY == 0
#define BSP_HOCO_HZ (24000000)
#elif BSP_CFG_HOCO_FREQUENCY == 2
#define BSP_HOCO_HZ (32000000)
#elif BSP_CFG_HOCO_FREQUENCY == 4
#define BSP_HOCO_HZ (48000000)
#elif BSP_CFG_HOCO_FREQUENCY == 5
#define BSP_HOCO_HZ (64000000)
#else
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
#define BSP_MCU_VBATT_SUPPORT (1)
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
#define OFS_SEQ5 (1 << 28) | (1 << 30)
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
/*
ID Code
Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
*/
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
#else
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_ADC_CFG_H_
#define R_ADC_CFG_H_
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ADC_CFG_H_ */

7
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_AGT_CFG_H_
#define R_AGT_CFG_H_
#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
#endif /* R_AGT_CFG_H_ */

6
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h Normal file
View File

@ -0,0 +1,6 @@
/* generated configuration header file - do not edit */
#ifndef R_DTC_CFG_H_
#define R_DTC_CFG_H_
#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
#endif /* R_DTC_CFG_H_ */

7
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_FLASH_LP_CFG_H_
#define R_FLASH_LP_CFG_H_
#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1)
#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0)
#endif /* R_FLASH_LP_CFG_H_ */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_ICU_CFG_H_
#define R_ICU_CFG_H_
#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_ICU_CFG_H_ */

7
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#endif /* R_IIC_MASTER_CFG_H_ */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_IOPORT_CFG_H_ */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_LPM_CFG_H_
#define R_LPM_CFG_H_
#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_LPM_CFG_H_ */

5
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h Normal file
View File

@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef R_RTC_CFG_H_
#define R_RTC_CFG_H_
#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_RTC_CFG_H_ */

8
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h Normal file
View File

@ -0,0 +1,8 @@
/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

7
ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h Normal file
View File

@ -0,0 +1,7 @@
/* generated configuration header file - do not edit */
#ifndef R_SPI_CFG_H_
#define R_SPI_CFG_H_
#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SPI_DTC_SUPPORT_ENABLE (1)
#define SPI_TRANSMIT_FROM_RXI_ISR (0)
#endif /* R_SPI_CFG_H_ */

257
ports/renesas-ra/boards/RA4W1_EK/ra_gen/RA4W1-EK.csv Normal file
View File

@ -0,0 +1,257 @@
"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities"
"ANT","30","RADIO0_ANT","","","","","",""
"AVCC0","35","ANALOG0_AVCC0","","","","","",""
"AVDDRF","39","RADIO0_AVDDRF","","","","","",""
"AVSS0","36","ANALOG0_AVSS0","","","","","",""
"FBIN","45","RADIO0_FBIN","","","","","",""
"LX","41","RADIO0_LX","","","","","",""
"P004","40","","","","Disabled","","","ADC0: AN04
ICU0: IRQ03
OPAMP2: AMPO"
"P010","38","","","","Disabled","","","ADC0: AN05
CTSU0: TS30
ICU0: IRQ14
OPAMP2: AMP-"
"P011","37","","","","Disabled","","","ADC0: AN06
CTSU0: TS31
ICU0: IRQ15
OPAMP2: AMP+"
"P014","32","","","","Disabled","","","ADC0: AN09
DAC0: DA"
"P015","31","","","","Disabled","","","ADC0: AN10
CTSU0: TS28
ICU0: IRQ07"
"P100","27","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPIN
AGT0: AGTIO
BUS_ASYNCH0: D00
GPT_POEG0: GTETRG
GPT5: GTIOCB
ICU0: IRQ02
IIC1: SCL
KINT0: KRM0
SCI0: RXD
SCI0: SCL
SCI1: SCK
SLCDC0: VL1
SPI0: MISO"
"P101","26","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPREF
AGT0: AGTEE
BUS_ASYNCH0: D01
GPT_POEG1: GTETRG
GPT5: GTIOCA
ICU0: IRQ01
IIC1: SDA
KINT0: KRM1
SCI0: SDA
SCI0: TXD
SCI1: CTS
SLCDC0: VL2
SPI0: MOSI"
"P102","25","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ACMPLP1: CMPIN
ADC0: ADTRG
ADC0: AN20
AGT0: AGTO
BUS_ASYNCH0: D02
CAN0: CRX
GPT_OPS0: GTOWLO
GPT2: GTIOCB
KINT0: KRM2
SCI0: SCK
SLCDC0: VL3
SPI0: RSPCK"
"P103","24","GPIO","Low","","Output mode (Initial High)","CMOS","","ACMPLP1: CMPREF
ADC0: AN19
BUS_ASYNCH0: D03
CAN0: CTX
GPT_OPS0: GTOWUP
GPT2: GTIOCA
KINT0: KRM3
SCI0: CTS
SLCDC0: VL4
SPI0: SSL0"
"P104","23","","","","Disabled","","","BUS_ASYNCH0: D04
CTSU0: TS13
GPT_POEG1: GTETRG
GPT1: GTIOCB
ICU0: IRQ01
KINT0: KRM4
SCI0: RXD
SCI0: SCL
SLCDC0: COM0
SPI0: SSL1"
"P105","22","","","","Disabled","","","BUS_ASYNCH0: D05
CTSU0: TS34
GPT_POEG0: GTETRG
GPT1: GTIOCA
ICU0: IRQ00
KINT0: KRM5
SLCDC0: COM1
SPI0: SSL2"
"P106","21","GPIO","Low","","Output mode (Initial High)","CMOS","","BUS_ASYNCH0: D06
GPT8: GTIOCB
KINT0: KRM6
SLCDC0: COM2
SPI0: SSL3"
"P107","20","","","","Disabled","","","BUS_ASYNCH0: D07
GPT8: GTIOCA
KINT0: KRM7
SLCDC0: COM3"
"P108","14","","","","Disabled","","","DEBUG0: SWDIO
DEBUG0: TMS
GPT_OPS0: GTOULO
GPT0: GTIOCB
SCI9: CTS
SPI1: SSL0"
"P109","15","SCI9_TXD","Low","","Peripheral mode","CMOS","None","CAN0: CTX
CGC0: CLKOUT
CTSU0: TS10
DEBUG0: TDO
DEBUG0: TRACESWO
GPT_OPS0: GTOVUP
GPT1: GTIOCA
SCI1: SCK
SCI9: SDA
SCI9: TXD
SLCDC0: SEG52
SPI1: MOSI"
"P110","16","SCI9_RXD","Low","None","Peripheral mode","CMOS","None","ACMP(0-1): VCOUT
CAN0: CRX
DEBUG0: TDI
GPT_OPS0: GTOVLO
GPT1: GTIOCB
ICU0: IRQ03
SCI9: RXD
SCI9: SCL
SLCDC0: SEG53
SPI1: MISO"
"P111","17","GPIO","Low","None","Output mode (Initial High)","CMOS","","BUS_ASYNCH0: A05
CTSU0: TS12
GPT3: GTIOCA
ICU0: IRQ04
SCI9: SCK
SLCDC0: CAPH
SPI1: RSPCK"
"P200","12","","","","Disabled","","","ICU0: NMI"
"P201","11","","","","Disabled","","","SYSTEM0: MD
SYSTEM0: VCC
SYSTEM0: VCC
SYSTEM0: VCC
SYSTEM0: VCC
SYSTEM0: VCC
SYSTEM0: VCC
SYSTEM0: VCC"
"P204","9","GPIO","Low","","Output mode (Initial High)","CMOS","","AGT1: AGTIO
BUS_ASYNCH0: A18
CAC0: CACREF
CTSU0: TS00
GPT_OPS0: GTIW
GPT4: GTIOCB
IIC0: SCL
SCI4: SCK
SCI9: SCK
SDHI0: DAT4
SLCDC0: SEG23
SPI1: RSPCK
USB_FS0: OVRCURB"
"P205","8","SCI4_TXD","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO
BUS_ASYNCH0: A16
CGC0: CLKOUT
CTSU0: TSCAP
GPT_OPS0: GTIV
GPT4: GTIOCA
ICU0: IRQ01
IIC1: SCL
SCI4: SDA
SCI4: TXD
SCI9: CTS
SDHI0: DAT3
SLCDC0: SEG20
SPI1: SSL0
USB_FS0: OVRCURA"
"P206","7","SCI4_RXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: WAIT
CTSU0: TS01
GPT_OPS0: GTIU
ICU0: IRQ00
IIC1: SDA
SCI4: RXD
SCI4: SCL
SDHI0: DAT2
SLCDC0: SEG12
SPI1: SSL1
USB_FS0: VBUSEN"
"P212","53","SCI1_RXD","","None","Peripheral mode","CMOS","None","AGT1: AGTEE
CGC0: EXTAL
GPT_POEG1: GTETRG
GPT0: GTIOCB
ICU0: IRQ03
SCI1: RXD
SCI1: SCL"
"P213","52","SCI1_TXD","","None","Peripheral mode","CMOS","None","CGC0: XTAL
GPT_POEG0: GTETRG
GPT0: GTIOCA
ICU0: IRQ02
SCI1: SDA
SCI1: TXD"
"P214","50","","","","Disabled","","","CGC0: XCOUT"
"P215","49","","","","Disabled","","","CGC0: XCIN"
"P300","13","","","","Disabled","","","DEBUG0: SWCLK
DEBUG0: TCK
GPT_OPS0: GTOUUP
GPT0: GTIOCA
SPI1: SSL1"
"P305","","","","","Disabled","","",""
"P402","44","IRQ0_IRQ04","","IRQ04","IRQ mode","","None","AGT0: AGTIO
AGT1: AGTIO
CAN0: CRX
CTSU0: TS18
ICU0: IRQ04
RTC0: RTCIC0
SCI1: RXD
SCI1: SCL
SLCDC0: SEG06"
"P404","46","GPIO","Low","","Output mode (Initial High)","CMOS","","GPT3: GTIOCB
RTC0: RTCIC2
SSI0: SSIWS"
"P407","1","","","","Disabled","","","ADC0: ADTRG
AGT0: AGTIO
CTSU0: TS03
IIC0: SDA
RTC0: RTCOUT
SCI4: CTS
SLCDC0: SEG11
SPI1: SSL3
USBFS0: VBUS"
"P409","56","","","","Disabled","","","GPT_OPS0: GTOWUP
GPT5: GTIOCA
ICU0: IRQ06
SLCDC0: SEG09"
"P414","55","","","","Disabled","","","GPT0: GTIOCB
ICU0: IRQ09
SDHI0: WP
SPI0: SSL1"
"P501","29","","","","Disabled","","","ACMPLP1: CMPIN
ADC0: AN17
AGT0: AGTOB
GPT_OPS0: GTIV
GPT2: GTIOCB
ICU0: IRQ11
QSPI0: QSSL
SLCDC0: SEG49
USB_FS0: OVRCURA"
"P914","4","","","","Disabled","","","USB_FS0: DP"
"P915","3","","","","Disabled","","","USB_FS0: DM"
"Q1","34","RADIO0_Q1","","","","","",""
"Q2","33","RADIO0_Q2","","","","","",""
"RES#","10","SYSTEM0_RES","","","","","",""
"TEST0","28","RADIO0_TEST0","","","","","",""
"VBATT","47","SYSTEM0_VBATT","","","","","",""
"VCC","18","SYSTEM0_VCC","","","","","",""
"VCC","54","SYSTEM0_VCC","","","","","",""
"VCCUSB","5","USBFS0_VCC","","","","","",""
"VCCUSBLDO","6","USBFS0_VCCLDO","","","","","",""
"VCL","48","SYSTEM0_VCL","","","","","",""
"VDDDIG","43","RADIO0_VDDDIG","","","","","",""
"VDDRF","42","RADIO0_VDDRF","","","","","",""
"VSS","19","SYSTEM0_VSS","","","","","",""
"VSS","51","SYSTEM0_VSS","","","","","",""
"VSSUSB","2","USBFS0_VSS","","","","","",""
1 Name Pin Function Drive Capacity IRQ Mode Output type Pull up Port Capabilities
2 ANT 30 RADIO0_ANT
3 AVCC0 35 ANALOG0_AVCC0
4 AVDDRF 39 RADIO0_AVDDRF
5 AVSS0 36 ANALOG0_AVSS0
6 FBIN 45 RADIO0_FBIN
7 LX 41 RADIO0_LX
8 P004 40 Disabled ADC0: AN04 ICU0: IRQ03 OPAMP2: AMPO
9 P010 38 Disabled ADC0: AN05 CTSU0: TS30 ICU0: IRQ14 OPAMP2: AMP-
10 P011 37 Disabled ADC0: AN06 CTSU0: TS31 ICU0: IRQ15 OPAMP2: AMP+
11 P014 32 Disabled ADC0: AN09 DAC0: DA
12 P015 31 Disabled ADC0: AN10 CTSU0: TS28 ICU0: IRQ07
13 P100 27 SPI0_MISO Low None Peripheral mode CMOS None ACMPLP0: CMPIN AGT0: AGTIO BUS_ASYNCH0: D00 GPT_POEG0: GTETRG GPT5: GTIOCB ICU0: IRQ02 IIC1: SCL KINT0: KRM0 SCI0: RXD SCI0: SCL SCI1: SCK SLCDC0: VL1 SPI0: MISO
14 P101 26 SPI0_MOSI Low None Peripheral mode CMOS None ACMPLP0: CMPREF AGT0: AGTEE BUS_ASYNCH0: D01 GPT_POEG1: GTETRG GPT5: GTIOCA ICU0: IRQ01 IIC1: SDA KINT0: KRM1 SCI0: SDA SCI0: TXD SCI1: CTS SLCDC0: VL2 SPI0: MOSI
15 P102 25 SPI0_RSPCK Low Peripheral mode CMOS None ACMPLP1: CMPIN ADC0: ADTRG ADC0: AN20 AGT0: AGTO BUS_ASYNCH0: D02 CAN0: CRX GPT_OPS0: GTOWLO GPT2: GTIOCB KINT0: KRM2 SCI0: SCK SLCDC0: VL3 SPI0: RSPCK
16 P103 24 GPIO Low Output mode (Initial High) CMOS ACMPLP1: CMPREF ADC0: AN19 BUS_ASYNCH0: D03 CAN0: CTX GPT_OPS0: GTOWUP GPT2: GTIOCA KINT0: KRM3 SCI0: CTS SLCDC0: VL4 SPI0: SSL0
17 P104 23 Disabled BUS_ASYNCH0: D04 CTSU0: TS13 GPT_POEG1: GTETRG GPT1: GTIOCB ICU0: IRQ01 KINT0: KRM4 SCI0: RXD SCI0: SCL SLCDC0: COM0 SPI0: SSL1
18 P105 22 Disabled BUS_ASYNCH0: D05 CTSU0: TS34 GPT_POEG0: GTETRG GPT1: GTIOCA ICU0: IRQ00 KINT0: KRM5 SLCDC0: COM1 SPI0: SSL2
19 P106 21 GPIO Low Output mode (Initial High) CMOS BUS_ASYNCH0: D06 GPT8: GTIOCB KINT0: KRM6 SLCDC0: COM2 SPI0: SSL3
20 P107 20 Disabled BUS_ASYNCH0: D07 GPT8: GTIOCA KINT0: KRM7 SLCDC0: COM3
21 P108 14 Disabled DEBUG0: SWDIO DEBUG0: TMS GPT_OPS0: GTOULO GPT0: GTIOCB SCI9: CTS SPI1: SSL0
22 P109 15 SCI9_TXD Low Peripheral mode CMOS None CAN0: CTX CGC0: CLKOUT CTSU0: TS10 DEBUG0: TDO DEBUG0: TRACESWO GPT_OPS0: GTOVUP GPT1: GTIOCA SCI1: SCK SCI9: SDA SCI9: TXD SLCDC0: SEG52 SPI1: MOSI
23 P110 16 SCI9_RXD Low None Peripheral mode CMOS None ACMP(0-1): VCOUT CAN0: CRX DEBUG0: TDI GPT_OPS0: GTOVLO GPT1: GTIOCB ICU0: IRQ03 SCI9: RXD SCI9: SCL SLCDC0: SEG53 SPI1: MISO
24 P111 17 GPIO Low None Output mode (Initial High) CMOS BUS_ASYNCH0: A05 CTSU0: TS12 GPT3: GTIOCA ICU0: IRQ04 SCI9: SCK SLCDC0: CAPH SPI1: RSPCK
25 P200 12 Disabled ICU0: NMI
26 P201 11 Disabled SYSTEM0: MD SYSTEM0: VCC SYSTEM0: VCC SYSTEM0: VCC SYSTEM0: VCC SYSTEM0: VCC SYSTEM0: VCC SYSTEM0: VCC
27 P204 9 GPIO Low Output mode (Initial High) CMOS AGT1: AGTIO BUS_ASYNCH0: A18 CAC0: CACREF CTSU0: TS00 GPT_OPS0: GTIW GPT4: GTIOCB IIC0: SCL SCI4: SCK SCI9: SCK SDHI0: DAT4 SLCDC0: SEG23 SPI1: RSPCK USB_FS0: OVRCURB
28 P205 8 SCI4_TXD Low None Peripheral mode CMOS None AGT1: AGTO BUS_ASYNCH0: A16 CGC0: CLKOUT CTSU0: TSCAP GPT_OPS0: GTIV GPT4: GTIOCA ICU0: IRQ01 IIC1: SCL SCI4: SDA SCI4: TXD SCI9: CTS SDHI0: DAT3 SLCDC0: SEG20 SPI1: SSL0 USB_FS0: OVRCURA
29 P206 7 SCI4_RXD Low None Peripheral mode CMOS None BUS_ASYNCH0: WAIT CTSU0: TS01 GPT_OPS0: GTIU ICU0: IRQ00 IIC1: SDA SCI4: RXD SCI4: SCL SDHI0: DAT2 SLCDC0: SEG12 SPI1: SSL1 USB_FS0: VBUSEN
30 P212 53 SCI1_RXD None Peripheral mode CMOS None AGT1: AGTEE CGC0: EXTAL GPT_POEG1: GTETRG GPT0: GTIOCB ICU0: IRQ03 SCI1: RXD SCI1: SCL
31 P213 52 SCI1_TXD None Peripheral mode CMOS None CGC0: XTAL GPT_POEG0: GTETRG GPT0: GTIOCA ICU0: IRQ02 SCI1: SDA SCI1: TXD
32 P214 50 Disabled CGC0: XCOUT
33 P215 49 Disabled CGC0: XCIN
34 P300 13 Disabled DEBUG0: SWCLK DEBUG0: TCK GPT_OPS0: GTOUUP GPT0: GTIOCA SPI1: SSL1
35 P305 Disabled
36 P402 44 IRQ0_IRQ04 IRQ04 IRQ mode None AGT0: AGTIO AGT1: AGTIO CAN0: CRX CTSU0: TS18 ICU0: IRQ04 RTC0: RTCIC0 SCI1: RXD SCI1: SCL SLCDC0: SEG06
37 P404 46 GPIO Low Output mode (Initial High) CMOS GPT3: GTIOCB RTC0: RTCIC2 SSI0: SSIWS
38 P407 1 Disabled ADC0: ADTRG AGT0: AGTIO CTSU0: TS03 IIC0: SDA RTC0: RTCOUT SCI4: CTS SLCDC0: SEG11 SPI1: SSL3 USBFS0: VBUS
39 P409 56 Disabled GPT_OPS0: GTOWUP GPT5: GTIOCA ICU0: IRQ06 SLCDC0: SEG09
40 P414 55 Disabled GPT0: GTIOCB ICU0: IRQ09 SDHI0: WP SPI0: SSL1
41 P501 29 Disabled ACMPLP1: CMPIN ADC0: AN17 AGT0: AGTOB GPT_OPS0: GTIV GPT2: GTIOCB ICU0: IRQ11 QSPI0: QSSL SLCDC0: SEG49 USB_FS0: OVRCURA
42 P914 4 Disabled USB_FS0: DP
43 P915 3 Disabled USB_FS0: DM
44 Q1 34 RADIO0_Q1
45 Q2 33 RADIO0_Q2
46 RES# 10 SYSTEM0_RES
47 TEST0 28 RADIO0_TEST0
48 VBATT 47 SYSTEM0_VBATT
49 VCC 18 SYSTEM0_VCC
50 VCC 54 SYSTEM0_VCC
51 VCCUSB 5 USBFS0_VCC
52 VCCUSBLDO 6 USBFS0_VCCLDO
53 VCL 48 SYSTEM0_VCL
54 VDDDIG 43 RADIO0_VDDDIG
55 VDDRF 42 RADIO0_VDDRF
56 VSS 19 SYSTEM0_VSS
57 VSS 51 SYSTEM0_VSS
58 VSSUSB 2 USBFS0_VSS

Some files were not shown because too many files have changed in this diff Show More