The nxp_driver v2.10 allows for/requires some changes to the code:
- Remove some part of pwm_backlog.*, which is provided by the lib now.
- Change eth.c: the newer versions have additional parameters of the
library versions.
- Change sdcard.c: use TransferBlocking instead of TransferNonblocking.
- Add some support for the MIMXRT1176 device.
- Set the clocks for UART, I2C, Timer.
- Integrate the I2S module and fix a rebase error.
- Use blocking transfer only for SPI. It's faster and interferes less with
other modules.
- Use the clock_config.c files of library v2.8.5. The mimxrt files keeps
the clock_config.c files from Verson 2.8.5. With clock_config.c from
v2.10, the boards do not work. Refactoring of the clock set-up is on the
to-do list.
- Enable expiry timers for UART, I2C and SPI, avoiding a stall in library
code.
- The clock_config.* files are moved from the board-specific directories to
the boards directory and given a MCU related name.
That caused Ethernet to lock up at high data rates after ~200MByte data
average in a row. Tested now with data bursts up to 10 GByte and overall
data rates of ~8MByte/s at the Eth100 port.
Sometimes frames could not be sent immediately because the controller was
still busy with previous frames. Then, an error was returned to lwip.
This fix adds a limited number of retries for this busy state, waiting
100µs before the next attempt. Typically the transmit succeeds now at the
second attempt.
Second change: Reset the controller for a clean state after soft reset.
The Pin config setting by IOMUXC_SetPinConfig() is supplied by a
bit pattern. That pattern is specific for a MCU family. In preparation
for supporting the MIMXRT117x family, the constant bit pattern is
replaced by a function call, such that the bit pattern is created
at a single place. The code for this functions was taken from
machine_pin.c.
Note: A working port for the MIMXRT1176 exists already.
Just another choice for the PHY interface.
Added: Keyword option phy_clock=LAN.IN or LAN.OUT
to define the source of the 50MHZ clock for the PHY
interface. The RMII clock is not enabled if it
is generated by a PYH board. Constants:
LAN.IN The clock is provided by the PHY board.
LAN.OUT The clock is provided by the MCU board.
The default is LAN.OUT or the value set in mpconfigboard.h, which
is currently set to IN only for the SEEED ARCH MIX board. Usage etc:
lan = LAN(phy_type=LAN.PHY_DP83848, phy_clock=LAN.IN)
The initial problem with a wrong ICMP checksum was caused by
the test code setting a checksum and the HW taking that probably as
the start value and ending up with 0xffff. With a checksum field of 0
set by the test code the HW creates the proper checksum.
Useful for boards without a PHY interface, where that has to be
attached. Like the Seed ARCH MIX board or Vision SOM. Phy drivers
supported so far are:
- KSZ8081
- DP83825
- LAN8720
More to come. Usage e.g.:
lan = LAN(phy_type=LAN.PHY_LAN8720, phy_addr=1)
The default values are those set in mpconfigboard.h.
This commit implements 10/100 Mbit Ethernet support in the mimxrt port.
The following boards are configured without ETH network:
- MIMXRT1010_EVK
- Teensy 4.0
The following boards are configured with ETH network:
- MIMXRT1020_EVK
- MIMXRT1050_EVK
- MIMXRT1060_EVK
- MIMXRT1064_EVK
- Teensy 4.1
Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK.
Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working.
Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not
tested lacking suitable boards.
Tested functions are:
- ping works bothway
- simple UDP transfer works bothway
- ntptime works
- the ftp server works
- secure socker works
- telnet and webrepl works
The MAC address is 0x02 plus 5 bytes from the manifacturing info field,
which can be considered as unique per device.
Some boards do not wire the RESET and INT pin of the PHY transceiver. For
operation, these are not required. If they are defined, they will be used.
robert-hh