forked from Lephenixnoir/PythonExtra
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Glenn Ruben Bakke
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HAL_QSPIE_H__
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#define HAL_QSPIE_H__
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#ifdef HAL_QSPIE_MODULE_ENABLED
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#if NRF52840_XXAA
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#include <nrf.h>
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#else
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#error "Device not supported."
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#endif
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/**
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* @brief Quad SPI clock frequency type definition
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*/
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typedef enum {
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HAL_FREQ_2_Mbps,
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HAL_FREQ_4_Mbps,
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HAL_FREQ_8_Mbps,
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HAL_FREQ_16_Mbps,
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HAL_FREQ_32_Mbps
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} hal_qspi_clk_freq_t;
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/**
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* @brief Quad SPI mode type definition
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*/
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typedef enum {
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HAL_SPI_MODE_CPOL0_CPHA0 = 0, // CPOL = 0, CPHA = 0 (data on leading edge)
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HAL_SPI_MODE_CPOL1_CPHA1 = 3 // CPOL = 1, CPHA = 1 (data on trailing edge)
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} hal_qspi_mode_t;
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/**
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* @brief Quad SPI data line configuration type definition
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*/
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typedef enum {
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HAL_QSPI_DATA_LINE_SINGLE,
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HAL_QSPI_DATA_LINE_DUAL,
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HAL_QSPI_DATA_LINE_QUAD
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} hal_qspi_data_line_t;
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/**
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* @brief Quad SPI Configuration Structure definition
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*/
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typedef struct {
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uint8_t d0_mosi_pin;
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uint8_t d1_miso_pin;
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uint8_t d2_pin;
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uint8_t d3_pin;
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uint8_t clk_pin;
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uint8_t csn_pin;
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uint8_t d0_mosi_pin_port;
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uint8_t d1_miso_pin_port;
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uint8_t d2_pin_port;
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uint8_t d3_pin_port;
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uint8_t clk_pin_port;
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uint8_t csn_pin_port;
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bool use_csn;
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hal_qspi_mode_t mode;
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hal_qspi_data_line_t data_line;
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hal_qspi_clk_freq_t freq;
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} hal_qspi_init_t;
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/**
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* @brief Quad SPI handle Structure definition
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*/
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typedef struct __QSPI_HandleTypeDef
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{
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NRF_QSPI_Type *instance; /* QSPI registers base address */
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hal_qspi_init_t init; /* QSPI initialization parameters */
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} QSPI_HandleTypeDef;
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void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init);
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void hal_qspi_master_tx_rx(NRF_QSPI_Type * p_instance,
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uint16_t transfer_size,
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const uint8_t * tx_data,
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uint8_t * rx_data);
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#endif // HAL_QSPIE_MODULE_ENABLED
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#endif // HAL_QSPIE_H__
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